By Adam Taylor

We need to be able to create more advanced, event-driven applications for Xilinx Zynq UltraScale+ MPSoCs but before that can happen, we need to look at some of the more complex aspects of these devices. In particular, we need to understand how interrupts function within the Zynq MPSoC’s PS (processing system). As would be expected, the Zynq MPSoC’s interrupt structure is slightly more complicated than the Zynq SoC’s PS because the Zynq MPSoC has more processor cores.

Architectural view of the Interrupt System

The Zynq UltraScale+ MPSoC’s interrupt architecture has four main elements:

RPU Generic Interrupt Controller V1 (GIC) – Manages Interrupts within the RPU (real-time processing unit) APU Generic Interrupt Controller V2 (GIC) – Manages Interrupts within the APU (application processing unit) with support for virtualization Inter Process Interrupt (IPI) – Enables interrupts between processing units GIC Proxy – Collates Interrupts acting as a GIC for the PMU (performance monitor unit)

At the highest level, we can break these interrupts down into several groupings, which are supplied to each element of the architecture:

Shared Peripheral Interrupts – 160 interrupt sources. Can be generated by the peripherals within the PS (e.g. IOU peripherals, PCIe etc.) and the PL (programmable logic) within the design

Private Peripheral Interrupts – These interrupts are private to a specific processor core

Software Generated Interrupts – Interrupts generated by software

Shared Peripheral Interrupts can also be sourced by the PL, which is where it gets interesting. We can enable interrupts in either direction between the PS and PL, from within the PS-PL configuration tab of the Zynq MPSoC customization GUI.

For the RPU, we are provided an IRQ and an FIQ for each processor core. For fast, low-latency responses, we should use the FIQ. For typical interrupt sources, we should use the IRQ.

RPU IRQ and FIQ Interrupts Enabled for each Core on the MPSoC

When it comes to the APU, we have two options for connecting the interrupts. The first option is to use the legacy IRQ and FIQ interrupts. There’s one of each for each processor core within the APU. When enabled at the top level of the Zynq MPSoC’s IP Block, we get two 4-bit ports—one for the IRQ and one for the FIQ. Again, the FIQ input provides lowest-latency interrupt response.

APU IRQ and FIQ Interrupts Enabled for each Core on the MPSoC

The second approach to interrupts is to use interrupt groups. The APU’s GICv2 supports two interrupt groups: zero and one. You can assign interrupts within group zero to the IRQ or FIQ, while those within group 1 can only be assigned to IRQ. This assignment occurs internally within the GICv2. We can also use these interrupt groups when we implement secure environments, with group 0 being used for secure interrupts and group 1 for not-secure.

APU IRQ Groups Enabled for each Core on the MPSoC

We can use the Inter-Processor Interrupt (IPI) to enable interrupts between the APU, RPU, and PMU. The IPI enables processors within the APU, RPU and PMU to interrupt each other. There IPI also has the ability to interrupt one or more softcore processors implemented within the Zynq MPSoC’s PL.

IPI Interrupt Numbers in the SPI

In addition to the interrupt, the IPI also provides a 32-byte IPI payload buffer for each direction, which can be used for limited communication. The IPI provides eight masters: the APU, RPU0, RPU1, and PMU, along with the LPD and FPD S AXI Interfaces. These masters can be changed from the default allocation by selecting advanced, on the MPSoC Re-Customisation GUI.

The final element of the interrupt structure is the Proxy GIC, which collates the shared interrupts connected to the LPU GIC and provides a series of Interrupt Status Registers, used by the PMU.

Now that we understand Zynq UltraScale+ MPSoC interrupts a little more, we will look at how we can use these within our designs going forward.

Code is available on Github as always.

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