Last month, AMD made a number of critical announcements concerning the future of its products. We now know that the company is: building its own custom implementation of the ARM architecture (codenamed K12); that it intends to deploy HSA on its low-power ARM and x86 cores next year; that these parts will be socket-compatible; and that the company is also working on a new x86 architecture. Today, we’re going to talk about the final piece of the puzzle that AMD didn’t mention — an SoC architecture that we ultimately believe could combine ARM and x86 hardware on the same die.

This article is speculative — AMD has not acknowledged such a strategy at this point — but if you read between the lines a bit, the pattern fits. Making the Puma+ and ARM SoC’s pin-compatible next year means that the two chips will use a common memory controller, PCI-Express interface, and cache structure. They’ll standardize on the same HSA implementation, and they’ll have the same I/O standards. It’s a first step — but just a first step.

Read through AMD’s presentations at various financial events and the company continues to beat the drum around the idea of an ambidextrous heterogeneous compute strategy, with ARM as a vital component of that overall plan. The goal is to reuse as many IP blocks as possible across the company’s products, scale that IP across both the traditional PC market and new growth opportunities, and to build a portfolio of AMD products that emphasize the company’s unique advantages, not its “me-too” status vis-à-vis Intel.

To discuss why AMD might build a single chip with both ARM and x86 cores, we first need to cover the industry’s previous attempts at multi-ISA products. (Yes, chip makers have tried this before.)

Next page: A brief history of multi-ISA products