IBM and 3M have announced a program to develop heat-dissipating adhesives that would permit the construction of tall, 3D “towers” of silicon chips in 3D assemblies. The stated target: 100 stacked chips. Some things about 3D assembly are absolutely uncontroversial:

Wire-bonded 3D assembly is in widespread use today, pervasively in mobile phone handsets.

3D assembly is clearly the best way to improve performance by minimizing chip-to-chip interconnect parasitic.

3D assembly enables power reduction by allowing smaller I/O swings and slower interconnect speeds using massively parallel interconnect as in the Wide I/O memory interface spec.

However, other 3D issues are controversial:

How do you test a 3D stack? Pre-bond? Partial-bond? Post-bond? All three?

What interconnect standards are needed to enable widespread use of 3D assembly?

How do you get the power out of a 3D stack?

This last question is especially thorny, given the industry’s strong preference for pushing individual die designs to the limits of power consumption. PC processor die routinely dissipate 100W and server die run at almost double that power. Even application processor chips destined for mobile phone handsets dissipate Watts of power.

However, if there were two companies likely to lick the power problem, I’d pick IBM and 3M. IBM has been the world leader in stretching and straining silicon to do it’s bidding since the 1960s and 3M, well what company knows glue—er, sorry, specialty adhesives for the electronics industry—the way 3M does?

Here’s a cool 38-second video from IBM and 3M that shows the concept: