I’ve been tinkering with MyHDL lately on the Z-turn board by MYIR. I have to say this board is pretty fun to play with so far, and i’ve left some resources on my blog about it, that might get updated later: MYIR Z-turn FPGA Board Pin Assignments.

Back to the MyHDL. I’m only just starting Python, but from the looks of it, it’s been fairly painless to understand so far. The use of Python (MyHDL is in fact only a library that’s used to do hardware dev and simulation) makes it faaaar easier to simulate designs than using the very frustrating Verilog simulators out there.

With the RTL logic, the rest of the verification framework can be regular python. Run the project, and you get a neat GTKWave output file, load it in, check if everything is okay, iterate.

I’ve written a little LED blinker for the Z-turn. It’s not the most amazing project ever, but it’s good as a template perhaps.

from myhdl import * ## Not synthesizable, it is used for the bench. ## @block def ClkDriver(clk, period=20): lowTime = int(period/2) highTime = period - lowTime @instance def drive_clk(): while True: yield delay(lowTime) clk.next = 1 yield delay(highTime) clk.next = 0 return drive_clk @block def hello2_top(clk, reset_n, ledRed, ledGreen, ledBlue, led_period): """ clk: input, clock signal reset_n: input, reset signal, inverted. ledRed: output, signal inverted. ledGreen: output, signal inverted. ledBlue: output, signal inverted. """ count = Signal(intbv(0, 0, 2**64)) @always (clk.posedge) def led_driver(): if reset_n == 0: ledRed.next = not 0 ledGreen.next = not 0 ledBlue.next = not 0 else: next_count = count + 1 if next_count == led_period: next_count = 0 ledRed.next = not ledRed count.next = next_count return instances() @block def hello2(): clk1 = Signal(bool(0)) ledR = Signal(bool(0)) ledG = Signal(bool(0)) ledB = Signal(bool(0)) reset_n = Signal(bool(0)) clkdriver_1 = ClkDriver(clk1) hello2_top_1 = hello2_top(clk1, reset_n, ledR, ledG, ledB, 1000) @instance def stimul(): reset_n.next = 0 yield delay(100) reset_n.next = 1 return instances() inst = hello2() inst.config_sim(trace=True) inst.run_sim(100000) # # Rig up for synthesis. # clk1 = Signal(bool(0)) reset_n = Signal(bool(0)) ledRed = Signal(bool(0)) ledGreen = Signal(bool(0)) ledBlue = Signal(bool(0)) inst = hello2_top(clk1,reset_n,ledRed,ledGreen,ledBlue, 12000000) inst.convert(hdl="Verilog")

Running project looks like a board with a blinking LED.

