RAM Guide: Part I

DRAM and SRAM Basics by Jon "Hannibal" Stokes DRAM chips Now that we know how to read from and write to a simple SRAM chip, let's look at the more common DRAM chip and see how to use it. DRAM, as I've mentioned earlier, is more complicated than SRAM because the charges placed on its memory cells leak out over time. (One of my EE professors used to say, "the difference between SRAM and DRAM is that SRAM works and DRAM doesn't.") So most of DRAM's peculiar and complicated characteristics arise from the fact we're trying to take memory that actually doesn't work and make it work. But before we talk more about the "making it actually work" aspects of DRAM, let's look at a simple DRAM chip and discuss the pin-outs. One of the earliest, simplest, and most important DRAM chips was the 2118, introduced by Intel in 1979. The 2118 was a 16K x 1 DRAM packaged in an 18-pin DIP. That "16K x 1" part means that it had 16384 cells and it read or wrote 1 data bit at a time. (I couldn't find an online datasheet for the 2118, so I did some Paintshop Pro mojo on the above diagram to get the following one, which I based off a printed 2118 pin-out that I have.) Looking at the above diagram, you'll probably notice a few immediate differences from the earlier SRAM module. The primary difference, and the one from which all the others stem, is that the number of address lines is cut in half. So you're probably wondering, if this 16K DRAM has half the number of address lines as the 16K SRAM, then how does it address all 16K memory cells? The answer is simple, but it makes interfacing with the DRAM more complicated: the address is cut into halves, and the two halves are applied to the address pins on two separate clock cycles. So the 14-bit address would be split into two, 7-bit chunks, and the two chunks would be fed to the DRAM one after the other on two successive clock cycles. This multiplexing of the address pins means that you can cut the number of address pins for a DRAM in half, and is a fundamental feature of DRAMs. Why is it important to be able to halve the number of address pins? Remember when I said that DRAM cells are about 4 to 6 times smaller than SRAM cells? If you can fit four times the amount of cells on a DRAM chip, this would mean that you'd need more address pins on it. (Not four times the number of address pins, though.) As DRAM cells get smaller and you keep having to add address pins, the size of the package gets bigger and bigger. As the size of the package gets bigger, so do its cost and power consumption. So it's very important to keep the number of pins per chip down, which means that address multiplexing is an essential feature of modern, large capacity DRAMs. This address multiplexing greatly complicates design, though, because it adds to the number of steps you have to go through to perform a read and a write. This means that not only is the DRAM chip itself more complicated internally, but the DRAM interface has to be more complicated as well. Before we list the actual steps in a DRAM read and write, let's take a look at an internal diagram of a DRAM chip. In the diagram above, you can see that there are two extra elements with two extra lines attached to them: the Row Address Latch is controlled by the /RAS (or Row Address Strobe) pin, and the Column Address Latch is controlled by the /CAS (or Column Address Strobe) pin. You'll also notice that the address bus is half as big, because row and column addresses are placed onto the bus separately. Now let's go step by step through a DRAM read cycle, with diagrams every few steps to show what's going on. DRAM Read 1) The row address is placed on the address pins via the address bus. 2) The /RAS pin is activated, which places the row address onto the Row Address Latch. 3) The Row Address Decoder selects the proper row to be sent to the sense amps. 4) The Write Enable (not pictured) is deactivated, so the DRAM knows that it's not being written to. 5) The column address is placed on the address pins via the address bus. 6) The /CAS pin is activated, which places the column address on the Column Address Latch. 7) The /CAS pin also serves as the Output Enable, so once the /CAS signal has stabilized the sense amps place the data from the selected row and column on the Data Out pin so that it can travel the data bus back out into the system. 8) /RAS and /CAS are both deactivated so that the cycle can begin again. I'll leave outlining the DRAM write cycle as an exercise to the reader. I'm not kidding, actually, because if you truly understand the read cycle, then you should be able to figure out the steps in the write cycle by looking closely at the SRAM write cycle and thinking about which steps in the DRAM read should be modified and which ones should be added to make a DRAM write. I'll give you some hints: you've got to modify step 4, and you've got to insert steps for sending data from the data bus to the sense amps and from the sense amps to the cell. Next: Making it work Table of Contents I. Storage Theory

II. RAM Chips

i. SRAM chips

ii. DRAM chips

iii. DRAM refresh

III. RAM Module Basics

IV. RAM Banks

V. RAM Module Redux: SIMMS and DIMMS

VI. RAM Chip Redux: the rest of the story

VII. Conclusion to Part I