At IEDM this December Imec presented “Interconnect metals beyond copper – reliability challenges and opportunities”. In addition to seeing the paper presented I had a chance to interview one of the authors, Kristof Croes. Replacements for copper are a hot subject and I will summarize the challenges and Imec’s work.



Introduction

Since the early day of the semiconductor industry we have seen a steady progression in interconnect to finer lines, more layers and new metals. The electrical current in interconnect lines haven’t scaled down as fast as the lines cross sectional area and therefore the current density in the lines has steadily increased. Early interconnect was wide aluminum (Al) lines that eventually gave way to narrower aluminum-copper (AlCu) alloys and eventually copper (Cu). Today we are starting to see the move from Cu to alternate materials for the narrowest lines.

Interconnect for advanced logic is made of an interconnect hierarchy:

[LIST=1]

Local – at the lowest layers is the local interconnect between adjacent cells.

Intermediate – the intermediate level connects cells, modules and cores.

Global – the global interconnect provides clock and power. The characteristics of the three levels is summarized in figure 1. Figure 1. Interconnect Types. The narrowest lines occur at the local level and that will be the focus of this article. Interconnect Requirements

Interconnect must meet a variety of requirements: [LIST=1]

Resistance – the resistance of an interconnect line is determined by the line length, cross sectional area and resistivity of the material. The interconnect line resistance is shown in figure 2.



Figure 2. Interconnect Line Resistance. Figure 2. Interconnect Line Resistance. From the table in the figure we can see that Cu has the lowest bulk resistivity of materials shown. However, the resistivity values shown her are the bulk resistivity values. At very small cross-sectional area of an interconnect line, electron scattering increases the material resistivity. The electron mean free path also included in the table is useful for estimating the increases in resistivity for small cross sectional area line. As can be seen from the table Cu has the longest mean electron mean free path of the material shown and therefore see the largest resistance increase at small cross-sectional area. When thinking about resistivity a figure of merit has emerged that is the resistivity multiplied by the electron mean free path. [LIST=1]

Electromigration – electrons moving through an interconnect line transfer momentum to the interconnect material atoms. At high current densities and temperatures, the momentum transfer can cause migration of the atoms that make up the interconnect lines leading to voids and breaks in the line. Figure 3 presents a formula for estimating electromigration resistance.



Figure 3. Electromigration Reliability. Figure 3. Electromigration Reliability. You can see from the table that there is a wide range of activation energies for materials. Al, the material used for interconnect early in the industry development has a low activation energy and therefore tends to have poor electromigration resistance. As mentioned previously the addition of Cu to Al, AlCu can improve the electromigration resistance (still used today for larger linewidth technologies). Figure 4 Illustrates AlCu. Figure 4. Aluminum-Copper. For pure materials the electromigration resistance can be estimated from the materials melting point and melting point is another material figure of merit. [LIST=1]

Adhesion to, and migration through dielectric layers – when Al was the interconnect of choice it could be deposited right on the dielectric layers and it adhered well and didn’t migrate through the underlying films. With the switch to Cu, adhesion and migration became challenges. The standard practice with Cu is to use a tantalum-nitride (TaN) barrier film to prevent the Cu from migrating through the dielectric films and contaminating the underlying devices. The problem with barrier layers like this is that the barrier material has high resistivity and in order to have the needed barrier properties a minimum thickness is required. As interconnect linewidths shrink to smaller and smaller cross-sectional area the barrier layers become a larger percentage of the cross-sectional area and drive up resistance. The barrier resistance is a particular problem in the bottom of vias where the film is relatively thick compared to the area of the via. An ideal interconnect material would adhere well to the dielectric films and not require a barrier.

Patterning – in order to use a material for interconnect it must be patterned. With aluminum in the early days of the industry a simple wet etch was used with a photoresist pattern. As the linewidths shrunk the linewidths became more and more like the film thickness and an anisotropic etch solution was needed ushering in dry etching. Cu is difficult to dry etch and a switch to a damascene process was required. In a damascene process a trench is etched in the dielectric film, the trench is filled with Cu and then chemical mechanical planarization is used to remove any Cu above the trench opening. Any new material will need to be patterned by dry etch or a damascene process with CMP.