Near the end of his Global Technology Conference presentation last week, Senior VP of Technology and R&D Gregg Bartlett jumped to the future—namely 2014 to 2015. By then, GLOBALFOUNDRIES plans to be implementing the second production phase for its 20nm process technology and it is at that point, he said, they GLOBALFOUNDRIES will introduce EUV (extreme UV) lithography into the manufacturing flow.

Now if you’ve been following IC process technology for a while, you know we’ve been hearing about EUV for more than a decade. You read about the early development at Lawrence Livermore National Laboratory. Microprocessor Report named EUV lithography “Technology of the Year” ten years ago. Suffice it to say, there have been some bumps in the road and EUV hasn’t yet set the world on fire.

In fact, the industry has been working lithographic black magic for the last decade and has avoided the use of EUV with immersion lithography, optical parameter correction (OPC) and source-mask optimization (SMO)—stalling the need for EUV generation by generation. Bartlett said in his talk that EUV was not needed for the 20nm process node where double patterning once more postpones the need for EUV but that doesn’t mean that GLOBALFOUNDRIES is ignoring EUV.

Bartlett said that GLOBALFOUNDRIES’ R&D efforts had produced the first full-field EUV patterning in 2008 and that the company’s Dresden mask house had shipped more than 60 EUV masks already. More important, he said that GLOBALFOUNDRIES had ordered a production-level EUV lithography tool, to be installed in the company’s Fab 8 (located in New York State) during the second half of 2012, with a planned introduction into the second phase of the 20nm production process in 2014 or 2015. That way, GLOBALFOUNDRIES will have EUV experience and be ready for the jump to the 14nm process node, where EUV will be required.

Bartlett had similar remarks for FinFETS.

GLOBALFOUNDRIES has been working on FinFET technology for many years, he said. They’re not needed for the 20nm process node, like EUV, but they’re planned for the 14nm node—again like EUV. FinFETs permit smaller geometries to be used and the operate at lower voltage levels, which improves power consumption and performance. Bartlett’s slides also mentioned ETSOI (extremely thin silicon on insulator) as another planned innovation for the 14nm node but he did not elaborate.

As Bartlett’s remarks at the Global Technology Conference clearly demonstrate, there will be major upheavals in the basic technology of Silicon Realization over the next few years. Significant advances in both manufacturing and EDA technology are needed to keep Moore’s Law on track.

Other blog posts from last week’s Global Technology Conference: