The International Electron Devices Meeting (IEDM) is one of the premier technical conferences covering semiconductor technology and is a must attend event. This years conference will be held December 1[SUP]st[/SUP] through 5th, 2018 at the Hilton San Francisco Union

Square hotel.

Saturday September 1[SUP]st[/SUP] will feature 90 minute tutorials covering:

Reliability Challenges in Advanced Technologies, Ryan Lu, TSMC

STT-MRAM Design and Device Requirements, Shinichiro Shiratake, Toshiba Memory

Quantum Computing Primer, Mark B. Ritter, IBM

Power Transistors in Integrated BCD Technologies, Hal Edwards, Texas Instruments

Design-Technology Co-optimization at RF and mmWave, Bertand Parvais, IMEC

Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS

Sunday, September 2[SUP]nd[/SUP] will feature two full day “short courses”. I don’t typically arrive in time for the tutorials on Saturday but I always attend one of the short courses on Sunday and find them very useful:

It’s All About Memory, Not Logic!, organized by Nirmal Ramaswamy, Micron

DRAM: Its Challenging History and Future, Dong Soo Woo, Samsung

3D Flash Memories: Overview of Cell Structures, Operations and Scaling Challenges, Makoto Fujiwara, Toshiba Memory Corporation.

Emerging Memories Including Cross-Point, Opportunities and Challenges, Kiran Pangal, Intel

Memory Reliability, Qualification and their Relation to System-Level Reliability Strategies, Todd Marquart, Micron

Packaging Technology for High Bandwidth Memory, Nick (Namseog) Kim, SK Hynix

Processing in Memory (PIM): Performance and Thermal Challenges and Opportunities, Mircea Stan, UVA

Scaling Survival Guide in the More-than-Moore Era, organized by Jin Cai, TSMC

Extreme-UV Lithography – Principles, Present Status and Outlook, Tony Yen, ASML

MOSFET Scaling Knobs (GAA, NCFET…) and Future Alternatives, Witek Maszara, Globalfoundries

Overcoming Variation Challenges, Sivakumar Mudanai, Intel

Embedded Memory: Present Status and Emerging Architecture and Technology for Future Applications, Eric Wang, TSMC

3D Integration for Density and Functionality, Julien Ryckaert, Imec

Advanced Packaging: the Next Frontier for Moore’s “Law,” Subramanian Iyer, UCLA

The main conference begins Monday morning with three plenary addresses

Future Computing Hardware for AI, Jeffery Welser, Vice President, IBM Research-Almaden

“4th Industrial Revolution and Foundry: Challenges and Opportunities,” Eun Seung Jung, President of Foundry Business, Samsung Electronics

The Status, Challenges and Opportunities of 5G, Prof. Gerhard P. Fettweis, TU Dresden

The schedule of the sessions over the next three days have not been announced yet but some of the focus sessions will be:

Quantum Computing

Application Requirements for Quantum Computing, John Preskill, Caltech

Materials and Device Challenges for Near-Term Superconducting Quantum Processors, Jerry Chow, IBM

Towards Scalable Silicon Quantum Computing, Maud Vinet, CEA-Leti

Silicon Isotope Technology for Quantum Computing, Kohei Itoh, Keio University

Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology, Ravi Pillarrisetty, Intel

Scalable Quantum Computing with Single Dopant Atoms in Silicon, Andrea Morello, Univ. New South Wales

Majorana Qubits, Leo Kouwenhoeven, Microsoft

Future Technologies Towards Wireless Communications: 5G and Beyond

Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology, Hyung-Jin Lee, Intel

RFIC/CMOS Technologies for 5G, mmWave and Beyond, Ali Niknejad, UC Berkeley

GaN HEMTs for 5G Base Station Applications, Shigeru Nakajima, Sumitomo Electron Devices

Highly Integrated mm-Wave Transceivers for Communication Systems, Vadim Issakov, Infineon

BAW Filters for 5G Bands, Robert Aigner, Qorvo

Reconfigurable Micro/Millimeter-wave Filters, Dimitrios Peroulis, Purdue

Challenges for Wide Bandgap Device Adoption in Power Electronics

GaN and SiC Devices for Automotive Applications, Tetsu Kachi, Nagoya University

SiC MOSFET for Mainstream Adoption, Peter Friedrichs, Infineon

GaN Power Commercialization with Highest Quality-Highest Reliability 650V HEMTs- Requirements, Successes and Challenges, Primit Parikh, Transphorm

The Current Status and Future Prospects of SiC High Voltage Technology, Andrei Mihaila, ABB

Barriers to Wide Bandgap Semiconductor Device Adoption in Power Electronics, Isik Kizilyalli, ARPA-E

High to Ultra-High Voltage SiC Power Device Technology, Yoshiyuki Yonezawa, AIST

Effects of Basal Plane Dislocations on SiC Power Device Reliability, Robert E. Stahlbush, Naval Research Laboratory

Interconnects to Enable Continued Technology Scaling

Interconnect Design and Technology Optimization for Conventional and Exotic Nanoscale Devices: A Physical Design Perspective, A. Naeemi, Georgia Tech

Mechanisms of Electromigration Damage in Cu Interconnects, C. K. Hu, IBM

Interconnect Metals Beyond Copper: Reliability Challenges and Opportunities, K. Croes, Imec

Microstructure Evolution and Effect on Resistivity for Cu Nano-interconnects and Beyond, Paul Ho, UT Austin

Integrating Graphene into Future Generations of BEOL Interconnects, H.-S. Philip Wong, Stanford

Interconnect Trends for Single Digit Nodes, Mehul Naik, Applied Materials

Tuesday evening December 4[SUP]th[/SUP] will see an evening panel session: EUV: Too Little, Too Late, Too Expensive or the Ultimate Cure-All?, organized by Sanjay Natarajan, Senior VP of Applied Materials. Much progress has been made in EUV patterning technology, and yet manufacturing throughput, masks, pellicles and resists still persist as problems today. The complexity of reliably transferring features at the 7nm node and below using quadruple patterning and 193nm immersion is affecting yield, affecting the cost-per-gate reduction and slowing down Moore’s Law. The industry eagerly awaits EUV, but is it too little, too late and too expensive, or is it the ultimate panacea? A team of world-renowned experts from the leading logic and memory IDMs, foundries and fabless companies will vigorously debate the issue.

A Luncheon will be held Wednesday, December 5[SUP]th[/SUP]: The speakers are yet to be determined, but IEDM will have a new lunch event this year that features industry leaders engaging the audience on the state of the industry, and on careers in device and VLSI technology. There will also be a vendor exhibition and poster sessions.

You can register for the conference and follow the program as it develops here.