IBM, in partnership with Samsung and GlobalFoundries (which manufactures chips for Qualcomm and AMD, among others), has developed a process for building 5nm chips. Two years ago IBM unveiled a 7nm process, and Samsung will likely ship 7nm chips next year, but today's announcement sounds like an even more important breakthrough in chip design.

The 5nm chip uses a "gate-all-around" transistor (GAAFET), with the gate material wrapped around a trio of horizontal silicon "nanosheets," as compared to the vertical fin design (FinFET) that's used in current state-of-the-art chips. IBM claims that FinFET could possibly scale down to 5nm, but there's a performance ceiling on that design due to the limits of current flow through the minuscule fins at that scale. In a way, the gate-all-around architecture is more simple than FinFET, and can probably be scaled as far down as 3nm, according to Ars Technica.

IBM claims that chips based on this new design can have 40 percent performance gains over the 10nm chips currently in production, at the same level of power. Or, more interestingly, up 75 percent power savings at the current generation's level of performance. The new EUV lithography (Extreme Ultraviolet) process used here also allows for nanosheet width to be adjusted continuously in a single chip design, which means circuits can be fine-tuned for power and performance in one manufacturing pass.