iceRadio

Introduction

System Architecture

Figure 1: iceRadio System Diagram

Tuner

RF input from the antenna can optionally be tuned down from VHF/UHF frequncies to an IF frequency in the HF range before passing to the ADC.

ADC

Raw HF or downconverted VHF at an IF of 5MHz is digitized to 14-bit resolution. The maximum input signal allowed without exceeing the range of the ADC puts the 0dBfs point of this system at -10dBm in 50 ohms. The ADC runs at 40MSPS with a resolution of 10 bits, providing approximately 60dB of dynamic range and 20MHz of bandwidth which places the quantization noise floor at about -70dBm.

FPGA

From the ADC, data passes into the FPGA. This is an iCE5LP4k part which provides 20 4kb RAM blocks and 4 16x16 MAC blocks which are essential for the DSP required for the downconversion. In the FPGA the ADC data is pre-processed to a sample rate appropriate for the MCU. Figure 2 below shows the primary components of the FPGA design.

Figure 2: iceRadio FPGA Diagram

Sample Buffer

Input Data Formatting

Tuning and Real / Complex conversion

CIC Decimation

FIR Decimator

I2S Master

SPI Control Interface

Overall FPGA design

MCU

Filter The first step in the processing is to further filter the input data. The full 9kHz bandwidth is rarely useful for broadcast and amateur radio signals so a set of real-time selectable 6th-order IIR filters with bandwidths of 8kHz, 6kHz, 4kHz, 2kHz, 1kHz and 500Hz are available. AGC After decimation and filtering the total signal power can be significantly reduced so an AGC automatically adjusts the signal power to a pre-determined level. The attack and decay time constants of the AGC are separate, allowing for fast attack and slow decay which reduces leading-edge distortion of signals with wide dynamic range such as amateur SSB. Demodulation

At present the MCU application supports these demodulation types:

AM: For broadcast and Short-Wave listening, this algorithm uses a simple sqrt(I*I+Q*Q), followed by a DC blocker to remove the carrier component.

For broadcast and Short-Wave listening, this algorithm uses a simple sqrt(I*I+Q*Q), followed by a DC blocker to remove the carrier component. Synchronous AM: For broadcast and Short-Wave listening, this algorithm regenerates the local carrier reference using an extremely narrowband PLL for reduced noise in weak signal conditions.

For broadcast and Short-Wave listening, this algorithm regenerates the local carrier reference using an extremely narrowband PLL for reduced noise in weak signal conditions. Upper Sideband: This algorithm performs a phase shift of the I and Q signals by +/-45 degrees, followed by DC blocking and summation to cancel out the lower sideband. Phase shifting is performed with a pair of optimized 6th-order IIR allpass filters.

This algorithm performs a phase shift of the I and Q signals by +/-45 degrees, followed by DC blocking and summation to cancel out the lower sideband. Phase shifting is performed with a pair of optimized 6th-order IIR allpass filters. Lower Sideband: This uses the same algorithm as the Upper Sideband described above, but uses a differencing network to cancel upper sideband.

This uses the same algorithm as the Upper Sideband described above, but uses a differencing network to cancel upper sideband. Upper + Lower: This mode outputs both upper and lower SSB sidebands simultaneously on the stereo output channels. This produces a unique tuning experience that may be useful for finding signals.

This mode outputs both upper and lower SSB sidebands simultaneously on the stereo output channels. This produces a unique tuning experience that may be useful for finding signals. Narrowband FM: This is mode differentiates the phase of the complex I and Q signal to demodulate FM. Standard de-emphasis is included.

This is mode differentiates the phase of the complex I and Q signal to demodulate FM. Standard de-emphasis is included. Raw: This is the filtered and AGCed I and Q data applied directly to the left / right stereo channels.

The foreground process on the MCU is either a simple serial command-line interface with simple functions for manipulating the FPGA configuration, tuning setup and background demodulation parameters or a GUI based on a color LCD and rotary encoder.

Front-end Enhancements

The original design of iceRadio was based on a 10-bit 40MSPS ADC PMOD that I designed many years ago. In early 2017 I came across a good deal on some much higher performance ADC chips so I adapted iceRadio to use 14-bit input samples. The additional resolution has helped to improve overall sensitivity and allows me to extend to dynamic range of the CIC decimation filters by several bits. While these chips can operate at over 100MSPS I'm only running this one at 40MSPS for now, mainly due to the speed limitations of the FPGA. It may be possible to double the sampling rate with some careful redesign of the input logic and that's going on the To-Do list.

Another enhancement is the addition of a VHF-downconverter based on the Rafael R820T2 tuner. The iceRadio firmware has been extended to allow it to control the tuner chip via I2C bus and configure its DDC to the IF output center frequency of the tuner. This allows reception of narrowband FM signals used in amateur radio, business and public service frequencies.

Ultra Plus FPGA

In late 2017, Lattice Semiconductor's new Ultra Plus subset of the ice40 FPGA became available through the normal distribution channels. These parts are a nice extension of the Ultra FPGA originally used in iceRadio with additional logic elements, more DSP cores and more RAM. At about the same time the IceStorm FOSS FPGA toolchain added support for these parts. I picked up a few and updated the STM32F303 + ice5 board with one since the parts are pin-compatible with the earlier ones. The good news is that iceRadio's FPGA design ported over with virtually no changes required. On top of that, the additional resources in the Ultra Plus part will allow me to add some more features that I've been mulling over, including a hardware AGC, support for a panadapter to aid in tuning, wideband + stereo FM demodulation and possibly even wider input bandwidth.

Status

07-08-16 - Started coding.

07-22-16 - Basic functions working.

08-09-16 - Webpage created.

03-21-17 - Added 14-bit ADC, VHF downconverter, fancier GUI.

02-25-18 - Updated with Ultra Plus FPGA.

Future Work

Additional demodulation algorithms for both audio and digital modes.

Hardware AGC

Panadapter

Higher input sampling rate

Wideband + stereo FM demodulation

Design Resources

Return to Radio page.

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