The United States Patent for Intel’s multi-chip package and die-to-die interconnect has been published in full. Initially filed in January, 2018, the patent outlines a few weird and wonderful ways of connecting two chips together, namely silicon bridges, that could potentially negate the need for pricey interposers or passive interconnects.

As dies get smaller, and more efficient, the interconnects that run between them must improve dramatically, too. Intel posits that fabricating such interconnects with organic substrate material is inherently fraught with danger, hence why alternatives such as silicon interposers and silicon bridges have been proposed.

Silicon interposers are expensive, and Intel claims these negate the “perceived MCP-derived cost benefits.” Instead, silicon bridges (or even those manufactured out of other useful materials) will take their place, embedded or attached to the package substrate and connecting up multiple dies, processing logic cores or otherwise, into “super-dies”. These so-called super-dies will be able to utilise multiple processes, dies, traditional design methodologies, and more into a single, interconnected processor.

“These bridges need to support only the dense die-to-die interconnect from die edge to die edge and can consequently be much smaller than a silicon interposer,” the patent application reads. “The silicon bridge concept also eliminates the need for TSV technology.

“Certain embodiments of the invention may enable the fabrication of MCPs having unprecedented die-to-die interconnect densities that would in turn enable MCP-type cost savings, modularity, and architectural flexibility.”

It’s a strategy that Intel’s been touting for some time, and that AMD has already adopted with Zen 2. Heterogeneous “mix-and-match” computing adopting 10nm, 14nm, and 7nm dies of varying heights and uses all in a single optimised package. Intel’s chief technology office has said that a move to heterogeneous chips, and leaving I/O and non-core logic off the latest process node, could save Intel around 50% of its R&D costs.

Intel’s also been developing its own interconnecting and 3D stacking technologies, EMIB and Foveros, to ensure there’s plenty of throughput between chips.

What’s fascinating most of all, however, is Intel touting some active dies as playing a two-part role as both functional die and interconnect. One such potential outcome is the concept of having a local active die act as an interconnect between two processing units while also serving both with access to its onboard memory. Memory and interconnect all rolled into a single die.

“In some embodiments, [the] bridge can be a passive component, in that it has no functionality other than to provide a high-speed, high-density signaling pathway between dies. In other embodiments, [the] bridge comprises an active die, having its own functionality apart from a bridging function, that constitutes a third die of [a] multi-chip package.

As you can tell, the patent itself is a little dense – and that’s with the diagram references removed. The English language is seemingly ill-equipped to accurately depict what’s going on exactly.

“As illustrated in FIGS 1A-1C and FIG 2, multi-chip package 100 comprises a substrate 110 having a side 111, an opposing side 112, and a side 213 that extends from side 111 to side 112. Multi-chip package 100 further comprises a die 120 and a die 130, both of which are attached to side 111 of substrate 110, and a bridge 140 adjacent to side 213 of substrate 110 and attached to die and to die.”

You get the idea. An image is worth one thousand words, anyways. You can read the full application (with pictures) over at the United States Patent Office.