Hello,

Our next webinar is slightly different one. Its a Q&A webinar on RTL Synthesis, by Clifford Wolf. Clifford is architect of Yosys which is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.

Clifford will be answering below 23 queries on RTL synthesis. Entry to this 2-hour webinar is FREE, recording is paid. So, buy it, if you like it.

This webinar opens 2 new opportunities, one a chance to interact with architect of Synthesis, two a chance to get your question in TOP25 list. Since we have already started receiving queries, make sure you draft challenging queries.

Below TOP23 query submissions are directly eligible for certificates from our company VSD Corp. Pvt. Ltd. All the best and happy learning.

Note of Appreciation I have worked with Clifford in my course on TCL programming Part 1 & 2, and really Thank him for all his guidance for making of TCL programming course.

Yosys

OpenSCAD (now maintained by Marius Kintel)

SPL (a not very popular scripting language)

EmbedVM (a very simple compiler+vm for 8 bit micros)

Lib(X)SVF (a library to play SVF/XSVF files over JTAG)

ROCK Linux (discontinued since 2010)