NXP Creates Open-ISA.org

by Bryon Moyer

We’re probably all aware at some level of the new processor upstart, the open-source RISC-V… core? No… architecture? No… instruction set architecture (ISA)? Yeah, that’s pretty much what it is. Which means… if you want to use it, and you’re starting from scratch, then there are lots of steps necessary to do anything.

Given all the hoopla, it’s easy to think that you can simply go out and buy these handy new RISC-V chips, which will cost less, cuz open source, right? But, while excitement is high, an ISA must be turned into an architecture and a micro-architecture, to be followed by detailed chip design and fabrication. And that’s just for the core. Then you need the whole subsystem. At that point, you have a shot at a chip.

Try to use that chip, and you’re going to have to host an OS and then create code and apply middleware and install communications stacks and… and… and… Oh, and then, when you’ve got something working – or, more accurately, partly working – you need to be able to debug the dang thing.

Of course, if you’ve heard of RISC-V, then you’ve probably heard of SiFive, the first really visible company to commercialize RISC-V. But does that mean that this will become yet another single-sourced processor? What if there were options… choices… the kind you get when there is a deep community with real competition?

There are a couple of things buried in that last question: community and competition. NXP has an opinion on the state of the community, and they’re doing some work (for free, at least at present) to build more community. As far as I can tell, their goal isn’t specifically to create more competition, but that could be a side effect of a robust community.

Open-ISA

What they’ve done is to create a new site/community called Open-ISA.org. (Don’t omit the hyphen or you’ll end up on an Ubuntu page!) And they’re hoping to stimulate engagement, both by attracting ecosystem partners and by engaging with designers who are evaluating RISC-V. Their efforts are based on a development board, which in turn is based on a new chip that NXP designed just for this purpose. The chip is called VEGA (making the board the VEGAboard).

NXP is keeping something of a low profile with this – there’s nothing there that they’re specifically selling (although that could change); they’re touting this more as a benevolent thing for the sake of deepening the RISC-V ecosystem. Assuming that’s the case, even though they’ve said nothing specific about any future plans, I wouldn’t be surprised to see something commercial come out of it sometime, if not in the near term. (There’s a limit to how much “charity” companies do… especially when it comes to designing a new chip – not a frugal endeavor!)

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In addition to the board, they have a collection of middleware and communication stacks, along with development and debugging tools. Contributing members are:

Ashling Microsystems, with a C/C++ development platform;

ETH Zurich, whence the RISC-V cores (more in a second);

Express Logic, with an RTOS and middleware;

Foundries.IO, with a complete “microPlatform”;

IAR Systems, providing another development platform;

and Seggers Microcontroller Systems, with their collection of development tools, middleware, and debug tools.

And, at present, the board is free. If you’re a developer or an academic (their primary audience), you can simply sign up on the website.

The VEGAries of Computing

The VEGA chip isn’t your typical commercial computing platform; it’s clearly purpose-designed to allow folks to evaluate RISC-V, with another rather well-known company’s cores in there as a baseline. There is a total of four cores: a pair for applications and a pair to handle the communications. Each pair consists of one RISC-V core and one ARM core. For applications, there’s a RISC-V core (more on it in a minute) and an ARM Cortex-M4F (along with a meg of flash, 256K of SRAM, and 48K of ROM). For comms, there’s a different RISC-V core and an ARM Cortex M0+ (with 256K of flash and 128K of ROM).

(Image courtesy NXP)

Technically, all four cores can be independently used together, but the cores in each RISC-V/ARM pair share a bus with no arbitration, so that limits everyone running at the same time. Rather than this being a four-core multicore chip, it’s more like a two-core heterogeneous platform, with a choice between RISC-V and ARM for each core. So it would be much more appropriate for comparing apps or comms on one core vs. the other.

Not from Whom You Might Be Thinking

The RISC-V cores themselves aren’t from a commercial supplier, nor did NXP gin up their own cores. The cores they used come from the “Parallel Ultra-Low Power,” or PULP, platform – a project at ETH Zurich. Various different versions exist, and they picked two of them for VEGA. Applications run on the RI5CY core, a 32-bit, 4-stage core. The comms stuff runs on a Zero-RISCY core, 32 bits and 2 stages. The details of the architecture are shown below (you’ll want to click to enlarge it).

(Click to enlarge; image courtesy NXP)

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The board itself provides a connector for Arduino shields as well as a connector for an antenna to support wireless communication. In particular, the radio supports Bluetooth Low Energy 5.0 (up to 8 connections) and IEEE 802.15.4 (giving you ZigBee and Thread at the very least). But they also show support for NFC, WiFi, and other protocols.

The board also supports a range of wired connections, including USB 2.0 and a variety of other interconnects like UART, I2C, and SPI. They’ve layered in security, giving each chip a unique 80-digit ID number and access control to flash. CRCs, cryptography functions, and true random number generation (TRNG) are implemented in low-power hardware.

This has been a quiet announcement by Silicon Valley standards. There was no press release – just a conversation with a few of us newsy folks. Will this catch fire enough to take off? I guess that depends both on whether they’ve hit the right features on the board and whether enough people hear about it. We’ll have to watch and see…

More info:

PULP

Open-ISA