March 18, 2015 posted by Jared McNeill

The Hardkernel ODROID-C1 is a quad-core ARMv7 development board that features an Amlogic S805 SoC (quad-core Cortex-A5 @ 1.5GHz), 1GB RAM and gigabit ethernet for $35 USD.

The ODROID-C1 is the first Cortex-A5 board supported by NetBSD. Matt Thomas (matt@) added initial Cortex-A5 support to the tree, and based on his work I added support for the Amlogic S805 SoC.

NetBSD -current (and soon 7.0) includes support for this board with the ODROID-C1 kernel. The following hardware is supported:

Cortex-A5 (multiprocessor)

CPU frequency scaling

L2 cache controller

Interrupt controller

Cortex-A5 global timer

Cortex-A5 watchdog

UART console

USB OTG controller

Gigabit ethernet

SD card slot

Hardware random number generator

More information on the NetBSD/evbarm on Hardkernel ODROID-C1 wiki page.

Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015 The NetBSD Foundation, Inc. All rights reserved. Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. NetBSD 7.99.5 (ODROID-C1) #350: Wed Mar 18 19:45:17 ADT 2015 Jared@Jared-PC:/cygdrive/d/netbsd/src/sys/arch/evbarm/compile/obj/ODROID-C1 total memory = 1024 MB avail memory = 1008 MB sysctl_createv: sysctl_create(machine_arch) returned 17 mainbus0 (root) cpu0 at mainbus0 core 0: 1512 MHz Cortex-A5 r0p1 (Cortex V7A core) cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu0: 32KB/32B 2-way L1 VIPT Instruction cache cpu0: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache cpu0: 512KB/32B 8-way write-back L2 PIPT Unified cache vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals cpu1 at mainbus0 core 1 cpu2 at mainbus0 core 2 cpu3 at mainbus0 core 3 armperiph0 at mainbus0 armgic0 at armperiph0: Generic Interrupt Controller, 256 sources (245 valid) armgic0: 32 Priorities, 224 SPIs, 5 PPIs, 16 SGIs a9tmr0 at armperiph0: A5 Global 64-bit Timer (378 MHz) a9tmr0: interrupting on irq 27 a9wdt0 at armperiph0: A5 Watchdog Timer, default period is 12 seconds arml2cc0 at armperiph0: ARM PL310 r3p3 L2 Cache Controller (disabled) arml2cc0: cache enabled amlogicio0 at mainbus0 amlogiccom0 at amlogicio0 port 0: console amlogiccom0: interrupting at irq 122 amlogicrng0 at amlogicio0 dwctwo0 at amlogicio0 port 0: USB controller dwctwo1 at amlogicio0 port 1: USB controller awge0 at amlogicio0: Gigabit Ethernet Controller awge0: interrupting on irq 40 awge0: Ethernet address: 00:1e:06:c3:7e:be rgephy0 at awge0 phy 0: RTL8169S/8110S/8211 1000BASE-T media interface, rev. 6 rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto rgephy1 at awge0 phy 1: RTL8169S/8110S/8211 1000BASE-T media interface, rev. 6 rgephy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT-FDX, auto amlogicsdhc0 at amlogicio0 port 1: SDHC controller amlogicsdhc0: interrupting on irq 110 usb0 at dwctwo0: USB revision 2.0 usb1 at dwctwo1: USB revision 2.0 cpu3: 1512 MHz Cortex-A5 r0p1 (Cortex V7A core) cpu3: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu3: 32KB/32B 2-way L1 VIPT Instruction cache cpu3: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache cpu3: 512KB/32B 8-way write-back L2 PIPT Unified cache vfp3 at cpu3: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals cpu2: 1512 MHz Cortex-A5 r0p1 (Cortex V7A core) cpu2: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu2: 32KB/32B 2-way L1 VIPT Instruction cache cpu2: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache cpu2: 512KB/32B 8-way write-back L2 PIPT Unified cache vfp2 at cpu2: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals cpu1: 1512 MHz Cortex-A5 r0p1 (Cortex V7A core) cpu1: DC enabled IC enabled WB disabled EABT branch prediction enabled cpu1: 32KB/32B 2-way L1 VIPT Instruction cache cpu1: 32KB/32B 4-way write-back-locking-C L1 PIPT Data cache cpu1: 512KB/32B 8-way write-back L2 PIPT Unified cache vfp1 at cpu1: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals sdmmc0 at amlogicsdhc0 uhub0 at usb0: vendor 0000 DWC2 root hub, class 9/0, rev 2.00/1.00, addr 1 uhub1 at usb1: vendor 0000 DWC2 root hub, class 9/0, rev 2.00/1.00, addr 1 ld0 at sdmmc0: <0x03:0x5344:SU08G:0x80:0x1cda770b:0x0ca> ld0: 7580 MB, 3850 cyl, 64 head, 63 sec, 512 bytes/sect x 15523840 sectors ld0: 4-bit width, bus clock 50.000 MHz uhub2 at uhub1 port 1: vendor 05e3 USB2.0 Hub, class 9/0, rev 2.00/32.98, addr 2 uhub2: multiple transaction translators boot device: ld0 root on ld0f dumps on ld0b root file system type: ffs kern.module.path=/stand/evbarm/7.99.5/modules WARNING: no TOD clock present WARNING: using filesystem time WARNING: CHECK AND RESET THE DATE! Wed Mar 18 22:45:46 UTC 2015 Starting root file system check: /dev/rld0f: file system is clean; not checking Starting file system checks: /dev/rld0e: 5 files, 52556 free (13139 clusters) random_seed: /var/db/entropy-file: Not present Setting tty flags. Setting sysctl variables: ddb.onpanic: 1 -> 0 Starting network. Hostname: empusa IPv6 mode: host Configuring network interfaces:. Adding interface aliases:. Waiting for DAD completion for statically configured addresses... Starting dhcpcd. Building databases: dev, utmp, utmpx. Starting syslogd. Mounting all file systems... Clearing temporary files. Updating fontconfig cache: done. Creating a.out runtime link editor directory cache. Checking quotas: done. Setting securelevel: kern.securelevel: 0 -> 1 Starting virecover. Starting local daemons:. Updating motd. Starting ntpd. Starting sshd. Starting mdnsd. Mar 18 22:46:07 empusa mdnsd: mDNSResponder (Engineering Build) starting Starting inetd. Starting cron. Wed Mar 18 22:46:08 UTC 2015 NetBSD/evbarm (empusa) (console) login: