The CMSIS is a vendor-independent hardware abstraction layer for microcontrollers that are based on Arm® Cortex® processors. The CMSIS defines generic tool interfaces and enables consistent device support. It provides simple software interfaces to the processor and the peripherals, simplifying software re-use, reducing the learning curve for microcontroller developers, and reducing the time to market for new devices.

The CMSIS is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems, and middleware components. The CMSIS is intended to enable the combination of software components from multiple middleware vendors.

CMSIS Components

CMSIS-... Target Processors Description Core(M) All Cortex-M, SecurCore Standardized API for the Cortex-M processor core and peripherals. Includes intrinsic functions for Cortex-M4/M7/M33/M35P SIMD instructions. Core(A) Cortex-A5/A7/A9 Standardized API and basic run-time system for the Cortex-A5/A7/A9 processor core and peripherals. Driver All Cortex Generic peripheral driver interfaces for middleware. Connects microcontroller peripherals with middleware that implements for example communication stacks, file systems, or graphic user interfaces. DSP All Cortex-M DSP library collection with over 60 Functions for various data types: fixed-point (fractional q7, q15, q31) and single precision floating-point (32-bit). Implementations optimized for the SIMD instruction set are available for Cortex-M4/M7/M33/M35P. NN All Cortex-M Collection of efficient neural network kernels developed to maximize the performance and minimize the memory footprint on Cortex-M processor cores. RTOS v1 Cortex-M0/M0+/M3/M4/M7 Common API for real-time operating systems along with a reference implementation based on RTX. It enables software components that can work across multiple RTOS systems. RTOS v2 All Cortex-M, Cortex-A5/A7/A9 Extends CMSIS-RTOS v1 with Armv8-M support, dynamic object creation, provisions for multi-core systems, binary compatible interface. Pack All Cortex-M, SecurCore, Cortex-A5/A7/A9 Describes a delivery mechanism for software components, device parameters, and evaluation board support. It simplifies software re-use and product life-cycle management (PLM). Build All Cortex-M, SecurCore, Cortex-A5/A7/A9 A set of tools, software frameworks, and work flows that improve productivity, for example with Continuous Integration (CI). SVD All Cortex-M, SecurCore Peripheral description of a device that can be used to create peripheral awareness in debuggers or CMSIS-Core header files. DAP All Cortex Firmware for a debug unit that interfaces to the CoreSight Debug Access Port. Zone All Cortex-M Defines methods to describe system resources and to partition these resources into multiple projects and execution areas.

Motivation

CMSIS has been created to help the industry in standardization. It enables consistent software layers and device support across a wide range of development tools and microcontrollers. CMSIS is not a huge software layer that introduces overhead and does not define standard peripherals. The silicon industry can therefore support the wide variations of Cortex-M processor-based devices with this common standard.

The benefits of the CMSIS are:

CMSIS reduces the learning curve, development costs, and time-to-market. Developers can write software quicker through a variety of easy-to-use, standardized software interfaces.

Consistent software interfaces improve the software portability and re-usability. Generic software libraries and interfaces provide consistent software framework.

It provides interfaces for debug connectivity, debug peripheral views, software delivery, and device support to reduce time-to-market for new microcontroller deployment.

Being a compiler independent layer, it allows to use the compiler of your choice. Thus, it is supported by mainstream compilers.

It enhances program debugging with peripheral information for debuggers and ITM channels for printf-style output.

CMSIS is delivered in CMSIS-Pack format which enables fast software delivery, simplifies updates, and enables consistent integration into development tools.

CMSIS-Zone will simplify system resource and partitioning as it manages the configuration of multiple processors, memory areas, and peripherals.

Coding Rules

The CMSIS uses the following essential coding rules and conventions:

Compliant with ANSI C (C99) and C++ (C++03).

Uses ANSI C standard data types defined in <stdint.h> .

. Variables and parameters have a complete data type.

Expressions for #define constants are enclosed in parenthesis.

Conforms to MISRA 2012 (but does not claim MISRA compliance). MISRA rule violations are documented.

In addition, the CMSIS recommends the following conventions for identifiers:

CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.

names to identify Core Registers, Peripheral Registers, and CPU Instructions. CamelCase names to identify function names and interrupt functions.

names to identify function names and interrupt functions. Namespace_ prefixes avoid clashes with user identifiers and provide functional groups (i.e. for peripherals, RTOS, or DSP Library).

The CMSIS is documented within the source files with:

Comments that use the C or C++ style.

Doxygen compliant function comments that provide: brief function overview. detailed description of the function. detailed parameter explanation. detailed information about return values.

that provide:

Doxygen comment example:

/** * @brief Enable Interrupt in NVIC Interrupt Controller * @param IRQn interrupt number that specifies the interrupt * @return none. * Enable the specified interrupt in the NVIC Interrupt Controller. * Other settings of the interrupt such as priority are not affected. */

Validation

The various components of CMSIS Version 5 are validated using mainstream compilers. To get a diverse coverage, Arm uses the Arm Compiler v5 (based on EDG front-end), the Arm Compiler v6 (based on LLVM front-end), and the GCC Compiler in the various tests. For each component, the section "Validation" describes the scope of the various verifications.

CMSIS components are compatible with a range of C and C++ language standards. The CMSIS components comply with the Application Binary Interface (ABI) for the Arm Architecture (exception CMSIS-RTOS v1). This ensures C API interfaces that support inter-operation between various toolchains.

As CMSIS defines API interfaces and functions that scale to a wide range of processors and devices, the scope of the run-time test coverage is limited. However, several components are validated using dedicated test suites.

The CMSIS source code is checked for MISRA C:2012 conformance using PC-Lint. MISRA deviations are documented with reasonable effort, however Arm does not claim MISRA compliance as there is today for example no guideline enforcement plan. The CMSIS source code is not checked for MISRA C++:2008 conformance as there is a risk that it is incompatible with C language standards, specifically warnings that may be generated by the various C compilers.

License

The CMSIS is provided free of charge by Arm under the Apache 2.0 License.

CMSIS Software Pack

The CMSIS software components are delivered in CMSIS-Pack format. The ARM::CMSIS Pack contains the following:

File/Directory Content ARM.CMSIS.pdsc Package description file in CMSIS-Pack format. LICENSE.txt CMSIS License Agreement (Apache 2.0) CMSIS CMSIS components (see also table below) Device CMSIS reference implementations of Arm Cortex-M processor based devices

CMSIS Directory