Last week Intel held a manufacturing day where they revealed a lot of information about their 10nm process for the first time and information on competitor processes continues to slowly come out as well. I thought it would be useful to summarize what we know now, especially since some of what Intel announced was different than what I previously forecast.



Process density

Comparing process density keeps getting more and more complex. Many years ago, node names meant something and were related to real process features. As node names became disconnected from actual process dimensions many of us turned to contacted poly pitch (CPP) multiplied by minimum metal pitch (MMP) as a density metric. Standard cells used in logic design have a height that is related to MMP and a width that is related to CPP. Recently companies have begun to push down the number of tracks and since cell height is the number of tracks multiplied by MMP we need to include tracks in our comparisons. Cell width is also getting more complicated, for example Intel discussed single versus dual dummy gates last week and for a two input NAND gate commonly used in logic designs, the cell width is ~4CPP for a dual dummy gate and ~3CPP for a single dummy gate. As I discussed in a previous article Intel has proposed a metric to try to include these factors but the metric has not been adopted by others yet (they just proposed it last week) and all of the information needed to calculate the Intel metric is not available for companies other than Intel. In spite of this I will present my estimates for this metric based on what I consider to be reasonable assumptions.

Logic designs also include large areas of cache (typically SRAM), input-output and analog. For cache the standard density metric is 6T SRAM cell size although even here there will be multiple variants with different sizes and practical array sizes will be bigger than just the number of bits multiplied by the cell size due to overhead and routing requirements.

My article about the Intel density metric is available here.

Performance

Process density is just one dimension of process performance that needs to be considered. On-state drive current per unit length, off-state leakage, power consumption and process complexity or cost are also critical metrics.

In the balance of this article I will discuss what is known about each of these factors at the major process nodes.

14nm/16nm

GLOBALFOUNDRIES (GF) licensed the Samsung 14nm process and we have combined them here as GF/SS. There was an LPE – early, version of the process followed by, LPP – performance, and LPC – cost version. LPP offers a 14% performance boost and LPC offers lower cost and RF support.

Intel’s 14nm has the smallest CPP and MMP of any 14nm/16nm node process and combined with a 7.67 track cell provides the densest 14nm process. We estimate that the Intel 14nm process provides >1.5x the native logic density of the other processes at this same node. At 0.0588 um2 the high-density SRAM cell size is also smaller than the other processes.

Intel has followed up their original 14nm process with 14+ and 14++ offering 12% and 23-24% higher drive current improvement respectively. For the 14++ process the CPP is relaxed from 70nm to 84nm, see figure 1 (note pp = poly pitch, what we call CPP). With the improved performance, it isn’t clear what impact the relaxed CPP has on density. In figure 1 Intel has plotted what they believe to be the performance of the processes from their competitors is versus Intel’s 14, 14+ and 14++ processes. Based on this plot Intel’s 14++ process has the best performance although it isn’t clear to me what process versions are plotted for the competitors (14LPE/16FF or 14LPP/16FFP).

TSMC called their process at this “node” 16nm to reflect relaxed pitches. The initial process was 16FF followed quickly by 16FF+ with a 15% performance boost. 16FFC is now available and is reported to have 8 to 10 less masks driving lower cost while offering 0.55 volt operation for low power (50% lower power).



Figure 1. Intel 14, 14+ and 14++ transistor performance versus competitor processes at the same “node”

Table 1 summarizes what we know about the 3 processes.

[table] border=”1″

|-

| style=”width: 156px” |

| style=”width: 156px” | GF/SS

| style=”width: 156px” | Intel

| style=”width: 156px” | TSMC

|-

| style=”width: 156px” | CPP (nm)

| style=”width: 156px” | 78

| style=”width: 156px” | 70

| style=”width: 156px” | 90

|-

| style=”width: 156px” | MMP (nm)

| style=”width: 156px” | 64

| style=”width: 156px” | 52

| style=”width: 156px” | 64

|-

| style=”width: 156px” | Cell height (nm)

| style=”width: 156px” | 480

| style=”width: 156px” | 399

| style=”width: 156px” | 480

|-

| style=”width: 156px” | Tracks

| style=”width: 156px” | 7.5

| style=”width: 156px” | 7.67

| style=”width: 156px” | 7.5

|-

| style=”width: 156px” | Estimated transistor density – Intel metric (MTr/mm[SUP]2[/SUP])

| style=”width: 156px” | 32.5

| style=”width: 156px” | 43.5

(Intel reported 37.5)

| style=”width: 156px” | 28.2

|-

| style=”width: 156px” | 6T SRAM cell size – high density (um2)

| style=”width: 156px” | 0.0650

| style=”width: 156px” | 0.0588

| style=”width: 156px” | 0.0700

|-

| style=”width: 156px” | Idsat – NMOS/PMOS (mA/um)

| style=”width: 156px” | NA

| style=”width: 156px” | 1.04/1.04

| style=”width: 156px” | 0.925/0.960

|-

| style=”width: 156px” | Ioff (nA/um)

| style=”width: 156px” | NA

| style=”width: 156px” | 10

| style=”width: 156px” | 50 (lower leakage long gate length available)

|-

| style=”width: 156px” | Vdd (V)

| style=”width: 156px” | 0.80

| style=”width: 156px” | 0.70

| style=”width: 156px” | 0.75

|-

| style=”width: 156px” | Variants

| style=”width: 156px” | LPE: initial process

LPP: 14% performance boost

HPC: low cost with RF

| style=”width: 156px” | 14: initial process

14+: 12% performance boost

14++: 23-24% performance boost

| style=”width: 156px” | FF: initial process

FF+: 15% performance boost.

FFC: 0.55 volt, 50% less power and 8 to 10 less masks

|-

| style=”width: 156px” | Relative process complexity [1]

| style=”width: 156px” | 1.09

| style=”width: 156px” | 1.06

| style=”width: 156px” | 1.0

|-



[1] Relative mask count as estimated by IC Knowledge for the same number of metal layers. Lowest mask count is set to 1.0.



Table 1. 14nm/16nm node process comparison.

10nm

At 10nm Samsung was first to begin ramping their process, TSMC is also ramping 10nm and Intel is due to ramp 10nm later this year.

At 10nm Samsung will once again release a 10LPE – early version, followed by a 10LPP – performance version, and eventually a 10LPC – low cost versions. At VLSIT Samsung disclosed a CPP of 64nm and an MMP of 48nm. A “Power-speed gain” of 27% is provided versus their 14nm technology. We do not know the specific track height but we are assuming they have reduced the track height to 7.5 tracks to be competitive with TSMC and Intel. The process is reported to use Litho-Etch Litho-Etch Litho-Etch (LE3) for critical metal layers to enable 2D metal layouts for improved routing.

TSMC hasn’t talked about 10nm very much. We believe is has a 64nm CPP and 42nm MMP with a 7.5 track height.

Intel’s 10nm process was disclosed at Intel’s Manufacturing Day to have a CPP of 54nm and an MMP of 36nm with a cell height of 272nm, this works out to a 7.56 track height. The initial 10nm process has 25% better performance or 0.56x better active power than the initial 14nm process. Interestingly both the 10 and 10+ versions will have lower performance than 14++ although much better dynamic capacitance and therefore lower power, see figure 2. We estimate the Intel process is ~1.7x the density of the next densest process and has the smallest SRAM cell size although we also estimate it is 1.23x as complex as the TSMC process. Although the SS and TSMC 10nm processes are denser than Intel’s 14nm process, they are closer to Intel’s 14nm process in density than they are to Intel’s 10nm process.



Figure 2. Intel performance and dynamic capacitance trends.

[table] border=”1″

|-

| style=”width: 156px” |

| style=”width: 156px” | SS

| style=”width: 156px” | TSMC

| style=”width: 156px” | Intel

|-

| style=”width: 156px” | CPP (nm)

| style=”width: 156px” | 64

| style=”width: 156px” | 64 est

| style=”width: 156px” | 54

|-

| style=”width: 156px” | MMP (nm)

| style=”width: 156px” | 48

| style=”width: 156px” | 42 est

| style=”width: 156px” | 36

|-

| style=”width: 156px” | Cell height (nm)

| style=”width: 156px” | 360 est

| style=”width: 156px” |

| style=”width: 156px” | 272

|-

| style=”width: 156px” | Tracks

| style=”width: 156px” | 7.5 est

| style=”width: 156px” | 7.5 est

| style=”width: 156px” | 7.56

|-

| style=”width: 156px” | Estimated transistor density – Intel metric (MTr/mm[SUP]2[/SUP])

| style=”width: 156px” | 52.8

| style=”width: 156px” | 60.3

| style=”width: 156px” | 103.0

(Intel reported 100.8)

|-

| style=”width: 156px” | 6T SRAM cell size – high density (um2)

| style=”width: 156px” | 0.040 HD

0.049 HP

| style=”width: 156px” | 0.034 Est HD

| style=”width: 156px” | 0.0312 HD

0.0367 LV

0.0441 HP

|-

| style=”width: 156px” | Idsat – NMOS/PMOS (mA/um)

| style=”width: 156px” | NA

| style=”width: 156px” | NA

| style=”width: 156px” | NA

|-

| style=”width: 156px” | Ioff (nA/um)

| style=”width: 156px” | NA

| style=”width: 156px” | NA

| style=”width: 156px” | NA

|-

| style=”width: 156px” | Vdd (V)

| style=”width: 156px” | 0.75

| style=”width: 156px” | NA

| style=”width: 156px” | 0.70

|-

| style=”width: 156px” | Variants

| style=”width: 156px” | LPE: initial process

LPP: 10% performance boost

LPC: low cost

| style=”width: 156px” | NA

| style=”width: 156px” | 10: Initial

10+:

10++: 15% better performance than 10 or 0.7x power improvement

|-

| style=”width: 156px” | Relative process complexity [1]

| style=”width: 156px” | 1.06

| style=”width: 156px” | 1.00

| style=”width: 156px” | 1.23

|-



[1] Relative mask count as estimated by IC Knowledge for the same number of metal layers. Lowest mask count is set to 1.0.

Table 2. 10nm node process comparison.

7nm

Intel hasn’t talked about 7nm at all yet but both SS and TSMC have revealed a fair amount of information and we will summarize it here and compare the 7nm processes to intel’s 10nm process.

TSMC published a MMP of 40nm at IEDM this year, they haven’t published CPP but we believe the CPP is 54nm and TSMC did disclose a cell height of 240nm at their technology forum yielding a 6 track cell height. The 7nm process offers 35% to 40% performance gains over 16nm or a >65% power reduction. There will be a 7nm process with a 240nm cell height, a HPC versions for reduced cost with 300nm and 360nm cell heights and eventually a 7+ process using EUV to provide a 15% to 20% area reduction.

Samsung has stated their 7nm process will use EUV and we therefore expect it to be the simplest process due to the reduction in multi-patterning masks. At IEDM Samsung, IBM and GF disclosed a CPP of 44nm and a MMP of 36nm. Assuming these pitches are representative of Samsung’s production process and assuming a 7.5 track height we get a cell height of 270nm.

After skipping 10nm GF is also introducing a 7nm process that will initially be optically based. We don’t currently have much information on this process but believe it will be similar to the SS process possibly with a relaxed MMP to avoid quadruple patterning. GF is expected to introduce EUV at 7nm once it is ready.

[table] border=”1″

|-

| style=”width: 156px” |

| style=”width: 156px” | TSMC

(7nm)

| style=”width: 156px” | SS

(7nm)

| style=”width: 156px” | Intel

(10nm)

|-

| style=”width: 156px” | CPP (nm)

| style=”width: 156px” | 54

| style=”width: 156px” | 44

| style=”width: 156px” | 54

|-

| style=”width: 156px” | MMP (nm)

| style=”width: 156px” | 40

| style=”width: 156px” | 36

| style=”width: 156px” | 36

|-

| style=”width: 156px” | Cell height (nm)

| style=”width: 156px” | 240

| style=”width: 156px” | 270 est

| style=”width: 156px” | 272

|-

| style=”width: 156px” | Tracks

| style=”width: 156px” | 6

| style=”width: 156px” | 7.5 est

| style=”width: 156px” | 7.56

|-

| style=”width: 156px” | Estimated transistor density – Intel metric (MTr/mm[SUP]2[/SUP])

| style=”width: 156px” | 116.7

| style=”width: 156px” | 127.3

| style=”width: 156px” | 103.0

(Intel reported 100.8)

|-

| style=”width: 156px” | 6T SRAM cell size – high density (um2)

| style=”width: 156px” | 0.0270 HD

| style=”width: 156px” | 0.0300 HD

| style=”width: 156px” | 0.0312 HD

0.0367 LV

0.0441 HP

|-

| style=”width: 156px” | Idsat – NMOS/PMOS (mA/um)

| style=”width: 156px” | NA

| style=”width: 156px” | NA

| style=”width: 156px” | NA

|-

| style=”width: 156px” | Ioff (nA/um)

| style=”width: 156px” | NA

| style=”width: 156px” | NA

| style=”width: 156px” | NA

|-

| style=”width: 156px” | Vdd (V)

| style=”width: 156px” | 0.50

| style=”width: 156px” |

| style=”width: 156px” | 0.70

|-

| style=”width: 156px” | Variants

| style=”width: 156px” | 7: initial process

7HPC: lower cost and density

7+: 15% to 20% reduced area

| style=”width: 156px” | LPE: initial process

LPP: improved performance

| style=”width: 156px” | 10: Initial

10+:

10++: 15% better performance than 10 or 0.7x power improvement

|-

| style=”width: 156px” | Relative process complexity [1]

| style=”width: 156px” | 1.21

| style=”width: 156px” | 1.00

| style=”width: 156px” | 1.34

|-



Table 2. TSMC and SS 7nm and Intel 10nm node process comparison.

Conclusion

Intel’s 14nm process is significantly denser than the competing processes from GF/SS and TSMC, >1.5x. It has taken roughly 3 years for SS and TSMC to introduce 10nm processes that are only slightly denser than Intel’s 14nm process.

Later this year when Intel introduces their 10nm process they will again take the process density lead, ~1.7x denser until TSMC’s releases their 7nm process with slightly better density.

When TSMC introduces their 7nm process they will have a 1.13x density advantage over Intel’s 10nm process. In late 2018 Samsung is later expected to introduce their 7nm process with 1.23x the density of Intel’s 10nm process, also later in 2018 TSMC will introduce 7+ with a further density improvement.

Intel’s 10nm is more similar to TSMC and GF/SS 7nm processes than to the competing 10nm processes. Even though Intel has a significant density advantage at each node the forthcoming 7nm foundry process will likely pass Intel for process density and maintain that yield for at least a few years.