AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans

A lot will change, especially with Genoa.

| Source: AMD - Via HPC AI Advisory Council Author: Mark Campbell

AMD reveals early Zen 3/Milan architecture details and Zen 4/Genoa plans

At the HPC AI Advisory Council's 2019 UK Conference, which took place on September 16/17th 2019, AMD's Martin Hilgeman revealed some early details about AMD's next-generation Zen 3 Milan architecture and the company's planned Zen 4/Genoa architecture.



During his presentation, AMD's Martin Hilgeman, their Senior Manager of HPC applications, revealed slides which confirm that AMD's upcoming "Milan" series of Zen 3 processors will release on AMD's existing SP3 server socket, support DDR4 memory and offer the same TDP and core count ranges as the company's ROME series of processors.



This slide appears to dispell the rumours that AMD planned to release Milan with a 4x SMT implementation, which alleged that Zen 3 would offer users four threads per CPU core. It looks like the main source of performance improvements from Zen 3 will come from IPC enhancements and clock speed gains, rather than increases in core/thread count. Hopefully, this means that Zen 3 will focus on single-threaded performance and core architecture improvements.



Moving on to Zen 4/Genoa, Helgeman states that Zen 4 is still in its design stages, which means that server makers and other customers have the opportunity to influence Genoa's design. It is also confirmed that Zen 4/Genoa will release on a new SP5 socket, support a new memory type (likely DDR5) and offer users "new capabilities".

Zen 3



Over halfway through his presentation, AMD's Martin Hilgeman confirmed that Zen 3 would move away from Zen/Zen 2's split cache design, which split the L3 cache on AMD's CPU dies between two quad-core CCXs. This means that AMD could be moving away from its quad-core CCX design, creating an 8-core CCX design with Zen 3 or a CPU design that uses a different design scheme.



Instead of offering two L3 caches that are 16MB in size (as seen in AMD's current Zen 2 design), AMD's Zen 3 core design will offer a combined "32+MB" of L3 cache between all eight CPU cores. This will lower potential inter-CCX latencies between the CPU cores in a single die and grant CPU cores better access to each chip's onboard L3 cache memory.



The slide below also suggests that Zen 3's L3 cache will be bigger than what was seen in Zen 2. This means that Zen 3 could offer a larger, combine L3 cache, granting all CPU cores better cache access while also providing the potential for more cache capacity. This could lower some internal CPU latencies, and allow Zen 3 processors to cache more data on-die. These changes could be beneficial for Zen 3's gaming performance, given AMD's existing marketing for "GameCache", and its benefits for Zen 2.







Based on these slides, Zen 3 will mark another major design change for AMD's Zen CPU architecture, offering changes what will be hugely beneficial for the processor's internal cache latencies. While little is known about AMD's Zen 3 core design, these slides show us that AMD's next-generation architecture aims to mitigate more of the shortcomings of AMD's existing designs. These downsides were already largely reduced with Zen 2, but Zen 3 seeks to take things to another level.



You can join the discussion on AMD's Zen 3 core design, and Zen 4/Genoa plans on the OC3D Forums.

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