ANTWERP – The next-generation transistor may come in Intel, Samsung and TSMC flavors. It’s just one sign of how the semiconductor roadmap is fanning out as it approaches a frightening wall a few nodes ahead.

At an annual event here, Imec researchers laid out what one observer called “a Cambrian explosion” of options to squeeze advances out of silicon. They span new kinds of transistors, materials, architectures and packages.

“Generic devices may no longer be possible…the one-dimensional roadmap may not be sufficient anymore. The future is not clear, but we need more options,” Luc van den Hove, chief executive of the research institute, said in a keynote.

Engineers will need all the knobs and levers they can get given a sobering roadmap Imec showed. It forecasts feature sizes will plod forward with shrinks at a pace measured in single-digit nanometers for the next few nodes. Beyond 40nm gate lengths and 16nm metal pitches at a 2-nm node, they may not shrink at all.

Researchers showed a frank and aggressive road map with an N7 similar to current foundry N5 nodes. Click to enlarge. (All images: Imec)

The result is chip performance may no longer scale for the highest-end parts. Shy of the top-end in active power, advances still are possible, especially for those willing to switch from FinFETs to more compact nanosheet transistors.

Chip makers focused on area and power shrinks for mobile systems may cling to FinFETs as long as possible. Those most hungry for performance gains will shift early to nanosheets that Imec expects will eke out an extra 8% in frequency, sacrificing reductions in area.

Nanosheets will have an emerging mid-life kicker in what Imec calls the forksheet, a design still being defined that pushes n- and p- devices closer together. The ultimate in compact transistors is a complementary or vertical FET that could get down to four or even three tracks by stacking n and p elements.

Along the way, engineers may try to push spacers to k values as low as 3.3 or even make a mad leap to germanium structures. “It’s a lot of each going their own way,” said Julien Ryckaert, director of Imec’s logic scaling program.

Designers working at standard cells and higher levels can ignore the transistor variations but will face extra cross-checks if they want to change foundries. Fabless companies with their own memory macros and cell libraries will need to be “profoundly aware of what’s happening on the technology side,” said Diederik Verkest, an Imec program director.