Wave Computing will follow in RISC-V’s path by offering its MIPS ISA as “open source” code without royalties or proprietary licensing. The MIPS Open initiative will focus on the development of SoCs for emerging IoT edge applications.



The RISC-V Foundation, which promotes the development of processors built on a standardized, open source instruction set architecture (ISA) is widely seen as a potential threat to Arm’s proprietary RISC ISA juggernaut. Yet, it’s also affecting other computer architectures, from Intel’s x86 to fading, legacy platforms such as Power and MIPS. This week, Wave Computing, which acquired the MIPS chip business from Imagination Technologies in June, announced a MIPS Open Initiative to reinvigorate MIPS development by offering access to the most recent 32- and 64-bit MIPS ISA versions free of charge with no licensing or royalty fees.

Wave Computing will “open source its MIPS instruction set architecture (ISA) to accelerate the ability for semiconductor companies, developers and universities to adopt and innovate using MIPS for next-generation system-on-chip (SoC) designs,” says the company. Freely available code will include 32- and 64-bit MIPS ISAs (Release 6), as well as MIPS SIMD Extensions, MIPS DSP Extensions, MIPS Multi-Threading, MIPS MCU, microMIPS Architecture, and MIPS Virtualization.

Participants in the MIPS Open program will be protected under MIPS’ existing worldwide patents that cover some 8.5 billion MIPS-based chips that have shipped in thousands of commercial designs, says Wave Computing. The MIPS Open initiative “will help greatly expand the existing MIPS ecosystem…by offering new opportunities to create innovative solutions from third-party tool vendors, software developers and universities,” says the company. The program will launch in Q1 2019, at which point more details on open source licensing and governance will be revealed.

The MIPS Open ISA will align with Wave’s “AI for All” edge AI vision and target a “broad set of edge applications such as home automation systems, IoT devices and FuSA enabled autonomous vehicles,” says Wave. Although there’s no mention of OS support, MIPS has traditionally been a Linux-focused architecture, and that is unlikely to change with the latest MIPS Open initiative.



Open ISA but paid licensing and registration

As noted in a story by The Register MIPS Open chips will not be fully free and open source in that MIPS licensees will still need to pay for a registration and certification process in order to enjoy MIPS patent protection. Also, while the ISAs will be freely accessible, offering in-depth access to the architecture, there’s no promise of open blueprints of Wave’s MIPS processor cores. Art Swift, president of Wave Computing’s MIPS IP Business, and formerly with with MIPS Technologies before joining Imagination Technologies and Wave Computing, told The Register that the company “is considering the release of one or two” core blueprints.

The Register notes that Wave Computing has not yet offered details on the license, only that it will be a “simple, non-royalty bearing license.” According to the MIPS Open FAQ, licensees will be free to “develop and maintain proprietary source code for any core it developed using the MIPS Open architectures.”

In Wave’s announcement, Lee Flanagin, SVP and chief business officer, stated: “The MIPS-based solutions developed under MIPS Open will complement our existing and future MIPS IP cores that Wave will continue to create and license globally as part of our overall portfolio of systems, solutions and IP.”

Current licensees for MIPS Release 5 or earlier can move up to MIPS 6. Yet, they must “follow the terms and conditions of the MIPS Open license and cannot ‘mix’ their licenses or earlier-licensed deliverables with the MIPS Open license,” says Wave.



RISC-V gives MIPS little choice but to open up

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Despite these caveats and uncertainties, the opening of the RISC-based MIPS is a milestone in computing history. This is the first major existing computer architecture to switch to an open ISA.

MIPS still has a significant market presence, from IoT chips like the SoC that power the new Omega2 Pro SBC to high-end networking SoCs such as legacy models in the Cavium Octeon family. Still, we’ve seen steady reversals in both MIPS segments.



Creator Ci40

Cavium and other MIPS licensees have steadily transitioned to Arm-based designs, a process that should continue now that the chipmaker has been acquired by Marvell. The early IoT market was awash in low-power networking boards running OpenWrt Linux on WiFi-enabled MIPS SoCs like Qualcomm Atheros chips or the MediaTek MT7688. These MIPS-based boards, such as the Arduino Yun, have largely given way to boards running Yocto Project based Linux stacks on Arm Cortex-A7 SoCs such as the NXP i.MX UL or ULL.

Given the continuing decline of MIPS, the swift rise of RISC-V, and the similarity between the RISC-V and MIPS architectures, going open source was probably Wave’s only choice. As Swift suggested to The Register, the main MIPS advantage over RISC-V chips is the platform’s maturity and existing customer base.

Before selling the MIPS unit to Wave, Imagination Technologies flirted with open hardware with its Prpl Foundation and the now defunct, open spec Creator SBCs, both of which started the MIPS pivot toward IoT. This followed an earlier failed attempt to spin MIPS into the smartphone market in partnership with hardware partners like Ingenic (Xburst). However, the MIPS phone campaign was shot down even quicker than Intel’s Cherry Trail Atom foray into the mobile market.

In 2015, Imagination Technologies experimented with opening its processor designs by releasing a free version of its Linux-ready MIPS MicroAptiv CPU to universities called MIPSfpga. The chip design was available as a production-quality RTL (register transfer level) design abstraction intended to run on industry standard FPGAs.







MIPSfpga architecture

(click image to enlarge)



RISC-V has continued to show momentum in the latter half of 2018. In late October, SiFive announced a slate of next-generation cores, including two Linux-ready models: the Cortex-A55 like U74 and U74-MC . Last month, the RISC-V Foundation announced a partnership with the Linux Foundation.

Earlier this month, Microchip’s Microsemi unit unveiled a low power, real-time deterministic PolarFire SoC architecture for Linux edge devices that combines its PolarFire FPGA with 4x RISC-V CPU cores supplied by SiFive. In addition, Western Digital announced a RISC-V based SweRV core.



Further information

More information on the MIPS Open Initiative will be revealed in Q1 2019. For now, you can check out the MIPS Open announcement and website, which provides a FAQ.

