The most complex electronic device yet built from carbon nanotubes has been demonstrated. The system is a functional universal computer, and represents a significant advance in the field of emerging electronic materials. See Letter p.526

Transistors made from semiconducting carbon nanotubes have been touted as a more energy-efficient replacement for conventional silicon transistors in future generations of microchips. However, owing to imperfections inherent in carbon-nanotube devices, it is difficult to integrate them into large-scale electronic circuits. As a result, progress on this technology has been sluggish. On page 526 of this issue, Shulaker et al.1 report a promising advance in this field — the first carbon-nanotube computer.

Usually it takes a whole armada of engineers to design and fabricate a functional computer from scratch, so it is worth noting how this small research group has made a nanotube computer. The authors took a two-pronged approach. First, they built on their technical know-how and experience of growing and aligning arrays of carbon nanotubes on a substrate. They developed methods to disable, on the substrate, all metallic carbon nanotubes, which would jeopardize the desired semiconducting behaviour of the system. The resulting substrate surface was covered with a highly aligned array of semiconducting nanotubes. The researchers were then able to create perfectly working transistors using advanced transistor-layout design and lithographic techniques, with each transistor consisting of a parallel arrangement of several individual semiconducting nanotubes.

By properly interconnecting the nanotube transistors, the authors succeeded in forming arbitrary logic elements and circuits. The underlying logic of the devices is the same as the p-type metal-oxide-semiconductor (PMOS) logic that was used in the early days of semiconductor transistors, before n-type metal-oxide-semiconductor (NMOS) logic took over around 1970. A PMOS transistor is switched on when a negative voltage is applied to its control (gate) electrode. By contrast, an NMOS transistor turns on if a positive voltage is applied to the gate.

The second aspect of Shulaker and colleagues' approach involved choosing the simplest-possible computer design — thus reducing the complexity of the hardware circuitry, and so the number of transistors, required to attain the computer's desired functionality. The authors opted for a computer that operates on only 1 bit of information and uses a single instruction; today's computers normally involve 32 or 64 bits and use many instructions. But it has been shown that any n-bit operation can be obtained by using multiple 1-bit operations, although at the expense of being more time consuming. So the authors' method does not compromise on generality.

The only instruction that the computer executes is the SUBNEG (subtract and branch if negative) command2, which in this design can be implemented with only 20 nanotube transistors. SUBNEG takes the content of a first memory address, subtracts it from the content of a second memory address and stores the result in the second memory address. If the result of this subtraction is negative, it goes to a third memory address. Because the instruction contains this conditional statement, it guarantees Turing completeness — that is, it can make any calculation if the computer has enough memory available. In other words, the instruction enables a universal computer to be made2. With this one instruction, Shulaker and colleagues' nanotube computer was able to run counting and integer-sorting algorithms concurrently.

In terms of performance, this computer is far from being competitive with current standards, but had this machine been made in 1955, it would have been. The use of PMOS-only logic limits the scalability of the approach because this logic requires that the smallest transistor differs in width from the largest transistor by more than a factor of 20 or so. What is more, PMOS logic consumes electric power at all times, because there is always current flowing in the underlying circuitry. Today's silicon-based computer microchips operate with complementary metal-oxide-semiconductor (CMOS) technology, which uses PMOS and NMOS transistors of almost equal width in a serial connection. This allows CMOS logic to be considerably more scalable and to consume less power than PMOS or NMOS logic.

Implementing CMOS logic in carbon-nanotube circuitry is straightforward3,4. For Shulaker et al., CMOS implementation would just have doubled the number of steps in the computer's fabrication. However, the fabrication yield (the number of functional transistors) would have dropped. This is due to the fact that every step has a certain probability of creating defects in the devices. Consequently, if the number of steps increases, the probability of getting non-working devices increases. But the history of chip manufacturing has shown that yield increase is basically a matter of effort, and so there is no roadblock to engineering nanotube-based circuits in CMOS design.

The smallest transistor width used by Shulaker and colleagues is roughly 8 micrometres, owing to the statistical nature of the authors' nanotube-growth process. This leaves open the question of the ultimate scalability of their method, and so of the potential to bring it on a par with, or ahead of, current silicon technologies. The answer will depend on how precisely nanotubes can be arranged on a substrate. Fortunately, advances on this front have not stopped5, and a density of 500 nanotubes per micrometre might be feasible in the near future6. Therefore, if research efforts are focused towards delivering a scaled-up (64 bits) and scaled-down (20-nanometre transistor size) version of Shulaker and colleagues' nanotube computer, we might be able to type on one soon.

References 1 Shulaker, M. M. et al. Nature 501, 526–530 (2013). 2 Gilreath, W. F. & Laplante, P. A. Computer Architecture: A Minimalist Perspective (Springer, 2003). 3 Chen, C., Xu, D., Kong, E. S.-W. & Zhang, Y. IEEE Electron Dev. Lett. 27, 852–855 (2006). 4 Wang, C., Ryu, K., Badmaev, A., Zhang, J. & Zhou, C. ACS Nano 5, 1147–1153 (2011). 5 Franklin, A. D. Nature 498, 443–444 (2013). 6 Cao, Q. et al. Nature Nanotechnol. 8, 180–186 (2013). Download references

Author information Affiliations Franz Kreupl is in the Department of Hybrid Electronic Systems, Technische Universität München, 80333 München, Germany. Franz Kreupl Authors Franz Kreupl View author publications You can also search for this author in PubMed Google Scholar Corresponding author Correspondence to Franz Kreupl.

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