At the VLSI Technology Symposium, IMEC presented a paper entitled “Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Silicon Wafers”. I have wanted to blog about this paper since the symposium was held but also wanted to tie it in with an interview with someone from IMEC who worked on the technology. This last week I got a chance to speak with Dan Mocuta of IMEC about the work.

The first question you may ask is why Horizontal Nanowire (HNW) technology is interesting. In my previous blog on An Steegen’s “Secrets of Semiconductor Scaling” presentation I discussed the looming limits on FinFETs. Basically FinFET scaling is expected to end at the 7nm node (real node, 5nm node at the foundries). To continue to scale some type of new device structure is needed. HNW processing is very similar to a FinFET process and they provide improved electrostatics and scaling. Many researchers and leading technologists believe HNW will be the successor to FinFEts.

You can read my blog about An Steegen’s paper HERE.

In the IMEC work they created 2 – 8nm diameter horizontal silicon nanowires stacked on top of each other. The pitches are slightly relaxed from what is needed for a 7nm node in order to demonstrate the devices.

The process to fabricate the nanowires is as follows:

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Ground plane implant – this is used to dope the surface of the wafer and suppress leakage due to parasitic transistors – this step is also typically seen in bulk FinFET processes.

Deposit a stack of Si/SiGe/Si/SiGe (Si = silicon, SiGe = silicon germanium) using an epitaxial reactor. This step is unique to HNW fabrication.

Fin formation – mask and etch to create “fins” and shallow trench isolation trenches. Refill the trenches with oxide and etch back the oxide to expose the “fins” – this is very similar to FinFET processing except the temperature for the fill needs to be lower for HNW and you are etching a Si/SiGe stack instead of just Si.

Dummy gate formation – deposit polysilicon, planarize and pattern it – same as FinFET fabrication.

Extension implants and spacer formation – same as FinFET fabrication.

Raised silicon source/drain – selective epitaxial growth of a raised silicon source/drain to make contact to the nanowire – for a typical FinFET process there would be Si raised source/drains for NMOS and SiGe raised source/drains for PMOS (more on this later).

HDD implants – ion implants into the raised source/drains – same as FinFET fabrication.

ILD0 – interlevel dielectric to cover the fins and planarization back to the tops of the dummy polysilicon gates – same as FinFET fabrication.

Dummy gate removal – etch out the polysilicon dummy gate – same as FinFET fabrication.

SiGe etch – a vapor phase HCl etch is used to etch out the SiGe in the “fin”, this releases the Si nanowires. This step is unique to HNW fabrication.

WF – the metal work functions are deposited and the gate area is filled – similar to FinFET fabrication.