By Adam Taylor

So far, we have addressed how to communicate, control, and read conversions from the Sysmon block in the Zynq UltraScale+ MPSoC’s PS (processing system). However, we have not addressed the Sysmon in the Zynq UltraScale+ MPSoC’s PL (programmable logic), which provides us the ability to monitor external signals.

As I mentioned in my first blog looking at the Zynq UltraScale+ MPSoC’s AMS capabilities, the first thing we need to do to use the PL Sysmon is check that it is available. We do this by reading the AMS block’s combined status register, which resides at address 0xFFA50044, named PL_SYSMON_CONTROL_STATUS. Only the LSB is used within this register. If that bit is set high, then the PL Sysmon is available. Otherwise, we should not try to address it.

We can access this register using a simple call to read the address as below:

pl_status = Xil_In32(0xFFA50044); // pl_status is a u32

Once we have confirmed availability, we can use the same approach that we did in the previous blog to configure the PS Sysmon. The only difference is that this time we will be configuring and using PL Sysmon, not the PS Sysmon. The exception this time it that as opposed to using the XSYSMON_PS block identifier, which says we wish to us the PS Sysmon, this time we need to use the XSYSMON_PL block identifier to use the PL Sysmon. This block identifier establishes the base address of the Sysmon we wish to use.

We can select the Sysmon channel wish to monitor using the sequencer masks available within xsysmonpsu_hw.h. Most of these sequencer channels are named as per their channel (e.g. VP_VN) as they are dedicated to one or the other Sysmon. The supply channels are not so named. As such, we need to understand when addressing either the PL or PS Sysmon what voltage parameter we are monitoring. The table below shows to monitored parameter for the both the PS and the PL channels.

What is very helpful is the ability of the PL Sysmon to monitor the PS core voltages. This is especially of interest for mission-critical applications. We will talk more about this in future blogs.

Putting this all together in a simple application that we run on the Zynq UltraScale+ MPSoC’s ARM cortex-A53 cores (the ARM Cortex-R5 cores can do the same), we can see the following results when reading both the PL and PS Sysmons:

Mapping the supplies above against the Zynq UltraScale+ MPSoC’s data sheet and IOCC user guide, voltages for the IO banks show both Sysmons are reading the correct values.

At this point, we have addressed either one or the other of the Sysmon blocks available using the block identifier. However, we can also read back several other critical voltages via the AMS block. This AMS Block is the third block identifier available which is XSYSMON_AMS.

We use this third block identifier to address the AMS block, within which we can read back the values of several other system critical voltages. These voltages include the five Zynq UltraScale+ MPSoC PS PLL voltages; the DDR PLL voltage; the battery voltage; and the VCC INT, BRAM, and AUX voltages.

We can address these voltages within the AMS block using the correct channel number and the “get ADC data” function as shown below:

XSysMonPsu_GetAdcData(InstancePtr, XSM_CH_VCC_PSLL0, XSYSMON_AMS);

When we are working with these channel numbers, it can get confusing as to what block identifier we should be using. It is worthwhile remembering that channels 0-6, 8-10 and 13-37 are addressed by the PL or PS Sysmon block identifiers while channels 38-53 to are addressed only by the AMS identifier.

I have uploaded the code to GitHub and you can find back issues here.

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

First Year E Book here

First Year Hardback here