Announced briefly two years ago, the chip is a prototype CPU for the computer currently known as ‘post-K’ and intended take the fastest computer crown back to Riken, starting operations in 2021.

The 512bit CPUs have the ARMv8-A scalable vector extension (SVE) instruction set architecture (ISA) to which Fujitsu contributed.

The hardware architecture is based on that Fujitsu has learned from implementing SPARC64-based processors and mainframes – “building on the micro-architecture hardware design experience Fujitsu has cultivated through previous supercomputer development projects, including the K computer”, it said. “Memory bandwidth is delivered by high performance stacked memory.”

It has double-precision arithmetic like K computer – useful for simulation, said Fujitsu, plus the firm has added half-precision arithmetic for artificial intelligence algorithms like deep learning.

“Because an architecture suited for high performance computing was co-designed by Fujitsu and R-CCS,” said R-CCS director Satoshi Matsuoka, “the post-K processors are expected to deliver performance far surpassing that of existing general-purpose server processors for many supercomputer applications, and considerably raise the system’s usability by using a broad software ecosystem through the adoption of the Arm instruction set, while at the same time delivering top-class performance not just in simulations, but also in a wide range of fields related to Society 5.0, including artificial intelligence and machine learning, security and blockchain technology, big data, and IoT.”

The chip prototypes have been verified for initial operation and are entering functionality trials.

post-K system software, including in the program development environment, will be compatible with K computer, according to Fujitsu. “By maintaining continuity in language specifications and micro-architecture, the program assets built up for the K computer can be reliably migrated by recompiling them, which can preserve performance standards”, it said.

System software developed by Riken, including McKernel, XcalableMP, and FDPS (framework for developing particle simulator) can also be used.

With Arm compatibility, post-K gets access to its ecosystem. “Joining this community will make it possible for post-K to utilise a wide range of software assets, including open source software,” said Fujitsu. “By simultaneously feeding back the results and technology attained through the development of post-K into the community, Fujitsu also hopes it will contribute to the creation of an ecosystem around the Arm architecture.”

Initial estimates are that post-K will have 100x the application execution performance of the K computer, while consuming 30-40MW compared with K’s 12.7MW.

The post-K prototype was exhibited at ISC 2018 in Germany.

Post-K specification Category Details CPU Instruction set architecture Armv8-A SVE (512bit) Number of cores Computational nodes: 48 cores + 2 assistant cores

I/O and computational nodes: 48 cores + 4 assistant cores Built-in interconnect Tofu (6D Mesh/Torus) System structure Nodes 1 CPU/node Racks 384 nodes/rack Software Operating system Linux (RHEL-based) + McKernel (Lightweight Kernel) System software Successor to the Fujitsu Software Technical Computing Suite Global file system FEFS (Lustre-based) Language Successor to the Fujitsu Software Technical Computing Language (Fortran/C/C++, OpenMP, MPI), XcalableMP Library framework FDPS (Framework for Developing Particle Simulator)

Fujitsu is also building a 37 petaflops supercomputer for Japan’s National Institute of Advanced Industrial Science and Technology (AIST) to be installed at the AI research centre being built at Tokyo University – using Intel CPUs and Nvidia GPUs.