Assembling nanocrystal devices A wide range of materials can be grown as high-quality colloidal nanocrystals, with properties spanning from conductors to semiconductors and insulators. Although these materials have been included in electronic devices, they usually only form a single component within the device. Choi et al. took a variety of solution-processable colloidal nanocrystals to form all of the device components. Through the development of the right materials, interfaces, and processing steps, they constructed an all-colloid field effect transistor. Science, this issue p. 205

Abstract Synthetic methods produce libraries of colloidal nanocrystals with tunable physical properties by tailoring the nanocrystal size, shape, and composition. Here, we exploit colloidal nanocrystal diversity and design the materials, interfaces, and processes to construct all-nanocrystal electronic devices using solution-based processes. Metallic silver and semiconducting cadmium selenide nanocrystals are deposited to form high-conductivity and high-mobility thin-film electrodes and channel layers of field-effect transistors. Insulating aluminum oxide nanocrystals are assembled layer by layer with polyelectrolytes to form high–dielectric constant gate insulator layers for low-voltage device operation. Metallic indium nanocrystals are codispersed with silver nanocrystals to integrate an indium supply in the deposited electrodes that serves to passivate and dope the cadmium selenide nanocrystal channel layer. We fabricate all-nanocrystal field-effect transistors on flexible plastics with electron mobilities of 21.7 square centimeters per volt-second.

Electronics are increasingly pervasive as new applications in mobile, wearable, and implantable devices for communication, computation, and sensing are introduced. Many of these applications require high-mobility, low-cost, large-area, and flexible semiconductor devices and are therefore driving the development of new, solution-processable materials and fabrication processes to meet the demand. Colloidal, inorganic nanocrystals (NCs) are a promising class of solution-processable materials. Wet-chemical synthetic methods have enabled the preparation of colloidal, NC inks that are metallic (1, 2), semiconducting (3–5), and insulating (6). These NCs are attractive building blocks for the solution-based assembly of NC solids with emergent physical properties that are derived from the size, shape, and composition-dependent characteristics of the constituent NCs and the collective interactions between the NCs in the solid state (7, 8). The strength of the NC-NC interactions in solids can be tailored by the length and composition of NC surface ligands (9, 10). The recent introduction of compact, inorganic ligands and processes for NC surface exchange has led to demonstrations of strongly coupled, high–electrical conductivity and -mobility, metallic and semiconducting NC solids (11–13). These NC solids have been used to form the metallic wiring and semiconducting active layer of electronic (14–17) and optoelectronic (18–21) devices.

However, NCs are typically only used to form a single element in these devices, and the remainder of the device architecture is realized with characteristically costly and slow, conventional vacuum-based deposition methods. Unlike conventional microelectronics, protocols for the integration of multiple, dissimilar, solution-processable NC materials to construct high-performance devices do not exist. Integration is a challenging feat and requires the development of orthogonal solution-based processes that do not detrimentally alter NC surface chemistry and that allow the complex stacking and patterning of NC thin films, and at the same time the design of chemically compatible, structurally stable, and physically cooperative materials and interfaces to achieve excellent device function.

Here we integrate metallic, semiconducting, and insulating NCs and design the materials, interfaces, and processes to enable the construction of all the components of high-performance, solution-processable, and flexible field-effect transistors (FETs) using colloidal NCs (Fig. 1A). Organic phase dispersions of Ag NCs, aqueous dispersions of Al 2 O 3 NCs, and organic phase dispersions of CdSe NCs are selected for their properties and orthogonal processing to form and stack the gate electrode, gate insulator, and semiconducting channel layers of the FET, respectively. We introduce In in the form of colloidal NCs and codisperse the In NCs with Ag NCs to create a solution-processable NC ink used to construct the source and drain electrodes and to supply atomic In upon annealing that passivates and dopes the NC semiconducting channel. Surface exchange of the Ag and CdSe NCs with the compact ligand thiocyanate (SCN) is used here not only to create high-conductivity electrodes and high-mobility semiconductor channel layers, as we have shown previously (13, 22), but to allow the stacking of NC device layers. We modify the Ag, Al 2 O 3 , and CdSe NC thin-film surfaces with polyelectrolytes to control surface charge and passivation and to exploit their high dielectric constants, to engineer chemically compatible, structurally stable, and physically cooperative device layers. By designing the constituent materials, interfaces, and processes, we successfully integrate different NC building blocks using solution-based processes to realize high-performance and flexible electronic devices, rivaling the high-mobility, low-hysteresis, and low-voltage operation of previously reported FETs fabricated from only a single-semiconductor NC layer but otherwise constructed using conventional processes.

Fig. 1 Colloidal NC FET building blocks. (A) Schematic of an FET assembled from metallic, semiconducting, and insulating NCs. Photographs and TEM images of colloidal dispersions of (B) CdSe NCs forming the semiconducting channel, (C) In and Ag NC mixtures forming the source and drain electrodes, (D) Ag NCs forming the gate electrode, and (E) Al 2 O 3 NCs forming the gate insulator layer.

Figure 1, B to E, shows photographs of the dispersions and transmission electron microscopy (TEM) images of the NC building blocks used as colloidal inks for FET fabrication. The process flow that enables us to integrate these NCs and to fabricate all-NC FETs is illustrated in Fig. 2A. To define Ag NC bottom gate electrodes, we lithographically pattern photoresist on a flexible Kapton substrate and then twice spin-coat a Ag NC dispersion (40 mg/ml) and immerse the Ag NC-coated substrate in a 1% NH 4 SCN methanolic solution to exchange the native capping ligand (22). The resist is lifted off, yielding patterned, Ag NC gate electrodes 80 ± 10 nm in thickness.

Fig. 2 Fabrication of flexible, all-NC FETs. (A) Schematic of the all-NC FET fabrication process on a flexible Kapton substrate via (i) photolithographic patterning and Ag NC spin-coating and ligand exchange; (ii) resist lift-off to define Ag NC gate electrodes; (iii) layer-by-layer spin coating of PDDA and PSS and then alternately Al 2 O 3 NCs and PSS to grow the gate insulator layer; (iv) spin coating of SCN-exchanged CdSe NCs to form the semiconductor channel layer; (v) photolithographic patterning and Ag NC/In NC spin coating and ligand exchange; and (vi) resist lift-off to yield patterned electrodes. Devices are thermally annealed at 250°C for 10 min in the nitrogen glovebox. (B) Photograph of a flexible, all-NC FET array and (inset) a higher-magnification optical image of a single-NC FET.

We treat the Ag NC gate electrode surface with the polyelectrolytes poly(dimethyldiallyl ammonium chloride) (PDDA) and poly(styrenesulfonate) (PSS) and then deposit the Al 2 O 3 NCs to form the gate insulator layer. Modification of the Ag NC gate electrode surface with the negatively charged PSS electrostatically enhances the adsorption of the positively charged Al 2 O 3 NCs (fig. S1) and is necessary to assemble uniform Al 2 O 3 NC layers (fig. S2). Subsequently, PSS and Al 2 O 3 NCs are deposited layer by layer (LBL) by spin coating to construct the gate insulator layer (fig. S3). Here, modification of the positively charged Al 2 O 3 NC surface with negatively charged PSS is required to grow the gate insulator layer, as the Al 2 O 3 NCs cannot be sequentially deposited on themselves (fig. S4). To form low-leakage FETs, a gate insulator layer of ~80 nm is prepared by depositing three layers of a Al 2 O 3 NC dispersion (25 mg/ml) alternately with PSS. The gate insulator layer is cured at 100°C for 30 min in air to remove residual solvent.

The organic ligands used to synthesize CdSe NCs are exchanged with compact SCN– ligands (10, 13). SCN-exchanged CdSe NC dispersions (25 mg/ml) are spin-cast onto the Al 2 O 3 NC gate insulator layer to form 60 ± 5 nm thick films (13). Before depositing the source and drain electrodes, the CdSe NC layer must be passivated to prevent delamination that is frequently observed during subsequent photolithographic patterning (15). Previously, we deposited an ultrathin (<1 nm) Al 2 O 3 layer by vacuum-based, atomic-layer deposition (ALD) to provide the required passivation (15). Here we show that the solution-based deposition of a PDDA/PSS bilayer successfully prevents delamination (fig. S5). Structural, optical, electrochemical, and electrical characterization of the CdSe NC layer after the PDDA/PSS surface treatment shows that the treatment has little effect on the CdSe NC film, and analytical measurements show that surface SCN– ligands are displaced by Cl– introduced in the PDDA (23) (figs. S6 to S8). Surface halogenation in IV-VI NCs is known to passivate NC films electronically and to stabilize NC films toward processing in air (24). We show that surface halogenation through the PDDA/PSS treatment stabilizes the CdSe NC films in the “harsh” chemical environments needed for their solution-based device integration.

Finally, 100 ± 10–nm-thick source and drain electrodes are patterned atop the CdSe NC layer, and the surface ligands are exchanged by immersion in a solution of NH 4 SCN, following the same procedure used to define the gate electrode layer. Here we highlight that a codispersion of Ag NCs and In NCs is used to provide an In supply key to doping and passivating the CdSe NC channel. The fabricated devices are then thermally annealed at 250°C for 10 min in a nitrogen glovebox to densify the CdSe NC film and activate In diffusion from the colloidal NCs introduced in the source and drain electrodes. Figure 2B shows a photograph of an array of all-NC FETs fabricated on Kapton via this solution-based process; the inset shows a higher-magnification image detailing the NC-based metallic electrodes, semiconducting channel, and gate insulator layer that are stacked to form the FET.

To confirm the function of each NC component contributing to the integrated device performance, we examine their structural and electrical properties. The SCN-exchanged, Ag NC films are robust to immersion in the solvents used in photolithography, allowing the patterning of well-defined Ag NC electrodes (Fig. 3A, inset). The patterned ~80-nm Ag NC films are highly uniform and crack-free, with a root mean square (RMS) roughness of ~7 nm (fig. S9) and a conductivity σ of 2.45 × 103 S/cm, similar to that of unpatterned Ag NC films (2.84 × 103 S/cm) (Fig. 3A). Annealing the Ag NC electrodes to 250°C, corresponding to the temperature seen in complete device fabrication, increases the conductivity to 2.38 × 104 S/cm, akin to that of vapor-deposited silver films (25).

Fig. 3 NC device component characterization. (A) Two-point resistivity measurements of patterned and unpatterned Ag NC films and (inset) photograph of a patterned Ag NC–based gate electrode. (B) Frequency-dependent dielectric constant for the Al 2 O 3 NC dielectric layer, (inset, top) schematic of the metal-insulator-metal measurement configuration, and (inset, bottom) the leakage current density as a function of electric field. (C) Current-voltage characteristics and (inset) photograph of CdSe NC films with patterned Ag/In NC electrodes as a function of the In NC concentration.

The Al 2 O 3 NC insulator layers prepared by LBL assembly are continuous and smooth (fig. S10A). The film thickness increases linearly and the RMS roughness increases marginally as the number of spin-coating cycles is increased from 1 to 10 (fig. S10B). We probe the frequency dependence of the dielectric constant of the Al 2 O 3 NC insulator layers in a metal-insulator-metal configuration by capacitance-voltage measurements (Fig. 3B). The dielectric constant is ∼15.1 at 50 Hz and shows <5% dispersion between 50 and 106 Hz for the 100°C, 30-min annealed Al 2 O 3 NC layer, which is larger than the ~8 dielectric constant typical of Al 2 O 3 layers grown by ALD (26), sputtering (27), and anodization (28). The increased dielectric constant is consistent with the incorporation of PSS, which has a high dielectric constant of ~30 to 120 (29). Upon further annealing of the films at 250°C for 10 min to mimic the thermal processing seen in device fabrication, the dielectric constant is marginally smaller (~14.9), implying that the intervening PSS still contributes to the properties of the gate insulator layer in the completed FET. The increased dielectric constant of the Al 2 O 3 NC insulator layer by the PSS allows more efficient charge accumulation in the semiconducting channel for low-voltage FET operation. The leakage current densities (Fig. 3B, inset) are ~7.16 × 10−7 A/cm2 and ~2.2 × 10−7 A/cm2 at an applied electric field of 300 kV/cm for 80-nm films annealed at 100°C for 30 min and further annealed at 250°C for 10 min, respectively. The thin, yet low-leakage and high–dielectric constant Al 2 O 3 NC-based gate insulator layers enable our realization of low-voltage and high-performance, flexible NC electronics.

To form high-mobility CdSe NC FETs, we previously introduced thermal evaporation and diffusion of elemental In to form ohmic contacts by n+ doping the contact regions and to electronically passivate and dope the NC channel (15). Here, we introduce colloidal In NCs into the Ag NC dispersion used to form the source and drain electrodes as a solution-based, NC route to provide the supply of atomic In upon thermal annealing. Time-of-flight secondary ion mass spectrometry (ToF-SIMS) is used to monitor the lateral and depth profile of In in and across the FET channel. Before annealing, no In is observed in the channel; however, after annealing, In is found uniformly distributed in the FET channel (fig. S11). The electrical characteristics of CdSe NC layers patterned with In NC-containing electrodes and annealed at 250°C for 10 min (Fig. 3C) show ohmic behavior at low voltages with conductivities that increase from ~10−7 S/cm for 0 weight % (wt %) In NCs (fig. S12) to ∼2.7 × 10−4 S/cm at 40 wt % of In NCs. By controlling the concentration of colloidal In NCs mixed with Ag NCs to form the source and drain electrodes, we can design the doping level of the CdSe NC channel.

We integrate the metallic, semiconducting, and insulating NCs to construct all-inorganic NC FETs, as depicted in the schematic in Fig. 1 and shown by scanning electron micrographs in fig. S13. Figure 4, A and B, shows representative output and transfer characteristics of our all-NC, solution-processed, flexible FETs fabricated from 40 wt % In NCs mixed in the Ag NC source and drain electrodes, a SCN-exchanged CdSe NC semiconducting channel, an Al 2 O 3 NC gate insulator layer, and a Ag NC gate electrode. The devices operate at low voltages and exhibit well-behaved n-type FET characteristics in the linear and saturation regimes (Fig. 4A) with an average electron mobility of μ = 21.7 ± 4.5 cm2/V-s, a threshold voltage V T = 0.36 ± 0.21 V, and a subthreshold swing S = 0.31 ± 0.05 V/decade, characterized from four independently prepared devices (fig. S14). The FETs show low hysteresis, as characterized by ΔV T = 0.21 ± 0.06 V at a drain-source voltage V DS = 2 V. The low-voltage and low-hysteresis FET operation is attributed to the high capacitance (0.176 μF/cm2) of the Al 2 O 3 NC insulator layer and the low-interface trap density at the Al 2 O 3 NC/CdSe NC interface. The transfer characteristics of all-NC FETs fabricated with lower concentrations of 0 and 20 wt% In NCs in the Ag NC source and drain electrodes show lower on-currents and current modulations (Fig. 4C), consistent with their low doping levels (fig. S15). Increasing the In NC concentration to 40 wt % in the Ag NC-based source and drain electrodes increases the on-current and current modulation to realize all-solution–processed CdSe NC FETs with a high performance similar to that of other state-of-the-art NC FETs fabricated by vacuum-based deposition of the electrodes and gate insulator layer (11, 13, 15, 16).

Fig. 4 Device characteristics of flexible, all-NC FETs. (A) Output and (B) transfer characteristics of an all-NC FET (channel length L = 30 μm, width W = 450 μm). (C) Transfer characteristics of all-NC FETs fabricated with 0, 20, and 40 wt % of In NCs in the source and drain electrodes.

In conclusion, we report all-NC FETs through the solution-based deposition, patterning, and integration of metallic, semiconducting, and insulating colloidal NC inks to construct the device components. The high performance of these all-NC FETs demonstrates the competitive advantage of colloidal NC materials for large-area, low-cost, and flexible electronics, eliminating the need for conventional vacuum-processed materials and setting the stage to exploit colloidal NC materials for additive manufacturing of devices. The materials integration and fabrication processes reported here may be applied more broadly to the construction of NC-based electronic, optoelectronic, and thermoelectric devices from the wide range of size, shape, and compositionally designed colloidal NC building blocks.

Supplementary Materials www.sciencemag.org/content/352/6282/205/suppl/DC1 Materials and Methods Figs. S1 to S15 References (30, 31)