Part 1 of this article defines and describes the designs that carry these low currents, explains the problems that arise when you design these circuits, and examines the application of shielding and guarding methods. Part 2 examines how your component selection affects the performance of your low-leakage circuits and discuss how noise creeps into low-leakage designs.

Low-Current Design Techniques

a. Leave things up-in-the-air

For proper operation of critical sub-picoamp circuits, some “unconventional” construction techniques may be required.

The classic low-current technique is the “up-in-the-air” wiring technique, where leads of the components in the critical path or circuit node are soldered together above the board. These component leads and traces do not come in contact with the board, so the influences of the PC board are effectively eliminated.

Teflon standoff terminals can be used to support large components or heavily populated nodes. The area below the components should be a solid, bare guard plane.

Figure 1: Up-In-The-Air wiring

This technique provides the lowest leakage, lowest stray capacitance and best overall low current performance, but requires hand assembly and is not easy to do in mass production or limited space areas. The entire circuit does not have to be placed above the board, only the critical nodes. In Figure 1 above, the inverting node of the circuit, which includes the input signal, feedback resistor and capacitor, are all soldered directly to the bent-up leg of the Op Amp inverting terminal.

b. Use Second Channel of a Dual

Here is a little tip: If you are designing a circuit that uses the non-inverting configuration, use the second (“B”) channel of a dual as your main amplifier.

Figure 2: Standard Dual Op-Amp Pinout

In the standard dual pinout, the “B” non-inverting input is farther away from the negative power supply pin, and is also “guarded” to the north by the inverting pin, and the input is on the corner of the package for easy connection to the source. There is also more room to run a guard trace between V- and the “B” non-inverting pin. The “A” channel amplifier can be used as a guard driver.

The single pinout suffers the same issue as the “A” channel, where the non-inverting input is close to the power supply. With the exception of a tiny single option, it may be more advantageous to use a dual version if both the single and dual are in the same 8-pin package.

c. Small packages may not be so good…

Figure 3: Small Package comparison

(top row) SOT-23, SC-70, TSSOP-14, (bottom row) SOIC-8 and MSOP-8

Packages with tighter lead pitches tend to have higher leakages. This is mainly because of the tight lead spacing and closer proximity to the supply lines and other pins. The board’s resistivity per square stays the same, but moving the pads closer reduces the distance, decreasing the resistivity.

Also, the tighter pitch can trap dirt quicker and it is more difficult to properly clean at these tight pitches. This is one of the few times a SOIC-8 would be better than a MSOP-8 if space is not at a premium. The old DIP package is still the best package in this regard. For these same reasons, the SOT-23 single is preferred to the SC-70 single.

Design and Layout Suggestions

Here are some general suggestions to keep in mind for your own design.

Guard traces should surround all the input stages. Guard PC board on the inner-layers and the bottom layer, too. The output does not need to be guarded, as it is low impedance, but it should be shielded from the input stages.

There is a tradeoff between guard spacing and input capacitance. A wider gap between the guard and input trace reduces the input capacitance.

Minimize the input surface area to reduce the effects of stray capacitance and ionization strikes. Since I-R drop is not a big issue at picoamp signal levels, and the speeds are generally low, use as narrow a trace width as possible to reduce strays. Use minimum size SMT pads to maximize space between pads.

Secure all loose wires. Sensitive high-impedance circuits can “see” a wire moving (ΔC). Within the guarded area, jumper or interconnection wires should be bare (no insulation, tinned solid copper preferable).

PC Board areas with solder mask removed should be enclosed within a sealed guard or shield to protect from moisture and dust.

Only use as much Teflon or other insulation around conductors as needed. Guard the rest of the area. Beware of spacing required for high voltage.

Watch out for plastic and tape use on the board. Use ESD conductive tape.

Ceramic capacitors are piezoelectric – mechanical vibrations and noises will create charge across the capacitor. Be careful when using ceramic caps in the input, integration, feedback or biasing networks.

The entire enclosure should be environmentally sealed, and desiccant packs should be used when humidity may be an issue. These packs should be easy to replace by the user or the metrology lab as part of a regular calibration or field service.

Minimize board flexing and stresses. Use multiple board mounting points or supports and do not support external user controls and connectors only by the board.

As was mentioned in the beginning of the article, designing successful circuits at sub-picoamp levels requires different design practices compared to “conventional” circuits. By following the simple advice above, a high level of first-time success can be achieved.

Design Challenge

The author was tasked with improving the performance of an evaluation board for the LMP7721 low-input-bias-current CMOS operational amplifier. The board needed to showcase the near-femtoamp input current performance of the device, while still using standard low-cost FR4 board and conventional surface-mount components. The board also had to support multiple circuit configurations.

Figure 4: LMP7721 Evaluation Board

The first step was minimizing the input surface area. This reduces the stray input capacitance, makes the input easier to guard, minimizes the effects of electrostatic coupling and ionization strikes.

Figure 5: Input Section of board showing guarded area

An extensive buffered guarding system was added surrounding the input circuit. Wide traces were added to the perimeter to allow the attachment of an optional metallic shield surrounding the entire circuit.

The input traces and all the sensitive feedback components are located within the perimeter of the smaller guard box. The larger outer bare copper square box is for soldering on a metal guard shield to cover the entire input circuit.

The LMP7721 has a unique pinout that separates the input pins (pins 1 and 8) from the power and output pins with guard pins (pins 2 and 7). These pins are connected to the guard to provide guarding all the way down to the lead frame level.

The solder mask has also been removed from this area to reduce charge accumulation.

Figure 6: Multi-Use Resistor Pads

To minimize input capacitance, and to reduce the physical surface area of the input, the input traces are very thin and the resistor pads serve double duty as jumpers.

The layout is designed to accommodate inverting, non-inverting and buffer configurations by changing a few resistors and jumper resistors (the “buffer” configuration is shown in the photo).

Normally, each resistor, and even the unused resistor options, would have their own pads. This would leave several unconnected pads “floating” unused.

Instead, the pads were laid out so that placing the resistor in the appropriate position completed the circuit and selected the configuration.

The result is a very tight, compact layout with minimum exposed input conductors. Of course, a dedicated circuit would be much smaller and compact.

Properly cleaning the board

Proper cleaning of the board is ultra-critical to provide the expected sub-picoamp performance.

Properly cleaning the board and components takes a few extra steps over conventional methods. Leftover flux residue, moisture and cleaning residues will severely degrade the low current performance.

The use of “no wash” spray flux is not recommended for the final cleaning. Water soluble fluxes can still leave a film behind.

The board should be re-cleaned after any rework to components within the guarded areas.

The board should be washed with isopropyl alcohol or methanol, making sure all remaining traces of moisture are removed from the board. Areas between the component leads should be scrubbed and areas under surface mount devices thoroughly flushed.

Figure 7: Cleaning board with Acid Brush

In the picture above, the board is scrubbed using an acid brush that has had the long bristles cut to a short length to increase the bristle stiffness. This is to allow for better scrubbing in between the device pins.

After a “standard” cleaning, the recommended extended cleaning procedure would be:

Remove all traces of moisture – otherwise it will react with the alcohol and leave white powdery deposits behind.

Flood board with alcohol (80% or better).

Scrub between device leads, connectors and around components with stiff brush.

Flood with alcohol again to flush out debris and blow excess off with compressed air. Also flush and blow under SMT devices. Don’t forget about the bottom of the board!

Quickly dab dry and then wipe dry with clean towelette.

Bake board to drive out remaining moisture.

After cleaning, only handle the board by the edges and do not touch anything inside the guard area. Avoid breathing on the board, as saline moisture in the breath can severely degrade performance. If any changes are made to the components within the guarded area, the cleaning procedure should be repeated.

The board should be stored in a sealed container or bag, preferably with a desiccant pack.

A full cleaning procedure and demonstration video[6] of the LMP7721 evaluation board is available at www.ti.com.

Verifying the board’s performance

After assembling and cleaning the board, the performance of the board has to be measured. A simple test was devised to check the performance.

For the inverting or transimpedance amplifier, the leakage is measured simply by disconnecting the source and observing the baseline “zero” level. Any levels above the theoretical baseline level are most likely due to leakage. However, because these circuits contain large resistors, resolving femtoamps can be difficult due to the noise.

The non-inverting configuration has the highest input impedance and is the most sensitive to leakages. For this reason, the non-inverting buffer configuration was chosen to test the board performance.

To test the non-inverting input, an open-circuit “float” test was used. The leakage current is integrated across the input capacitance. From the resulting drift rate and the known input capacitance value, the leakage current can be calculated.

The non-inverting input “float” test is fairly simple. The input is temporarily grounded with a wire, and then opened by quickly removing the grounding wire from the input. The input is then allowed to “float” unconnected as the output voltage is measured at regular time intervals to calculate the current.

The equipment required for the test is fairly simple, only requiring a DMM and a stopwatch or similar interval logging setup. A digital scope can also be used for this function if one is available.

The Setup

The setup was enclosed in a steel coffee can, covered with a metal lid or aluminum foil (not the plastic lid).

Figure 8: Test Circuit inside Coffee Can. (Test wire can be seen going to the input)

A long, thin piece of grounded, un-insulated bus wire is run through a small hole in the top and inserted into the input. This wire can be seen in left side Figure 8. The end of the wire has been bent into a narrow “V” and friction-fit into the input pad so it will come out quickly and easily.

To start the test, the wire is pulled all the way out of the enclosure to open the input and begin the test. The output voltage is recorded at 10 second intervals for 500 seconds.

Figure 9: Measured Open-Input Results

Figure 9 shows the results. The wire was pulled out after the first two samples (20 seconds). Visible is the initial jump in the output after the wire was pulled out (due to mechanical disturbances). After about 40 seconds, the output settles to a constant drift rate of less than 1mV per second.

Using the known input capacitance (previously measured at about 12pF for this board), and the measured change in voltage and time, the input leakage currents can be calculated by integrating the output voltage over time using the simple formula:

i = (Δv / Δt) * C

Looking at Figure 9, we can make a rough calculation of the average input current. The output went from -10mV at 200 seconds, to -20mV at 500 seconds. The ΔV is -10mV, and the ΔT is 300 seconds. Inserting these values into the formula gives us about a femtoamp of leakage.

( -10mV / 300sec ) * 12.2pF = -1.2fA

This is very good performance for an FR4 board!

Measuring the Input Capacitance

The input capacitance is affected by several factors. Most prominent is the input capacitance of the amplifier and the trace capacitance.

Most op amps have input capacitances in the range of 2pF to 15pF, and as high as 40pF for “low noise” CMOS devices. Sockets, PCB traces, protection components, feedback elements, connectors and cables can add significantly to this value. The actual total capacitance value will dependant on your individual circuit and the layout.

Knowing the input capacitance of your circuit is critical to both the circuit design and the current measurement. There are various ways to measure the capacitance, such as using a capacitance meter, but there are problems with that approach.

Most capacitance meters are based on a “bridge” or AC source-measure configuration and cannot have one of their terminals grounded. Some handheld DMM’s have capacitance functions, and you can take advantage of the “floating” aspect of the handheld device, but these meters are generally inaccurate in the picofarad range and/or are susceptible to noise pickup or proximity effects while “floating.”

A simple technique involves using a large series value resistor (100K to >10M) added in series with the input and a sinewave signal generator (10Hz to ~100KHz).

Figure 10: Input Capacitance Test Circuit

An RC pole is created by the large series test resistor (Rsense) and the input capacitance (Cin).

To find this pole, an AC signal is fed through the series resistor while the generator frequency is swept until the monitored output amplitude drops to 70.7% of the reference frequency amplitude (-3dB). By knowing the pole frequency and resistor value, the input capacitance can then be calculated.

To perform the test, a temporary jumper is placed across the sense resistor to short it out. The scope or AC voltmeter is connected to the amplifier output (Vout) and the generator is then set to a low reference frequency; say 10Hz, and the amplitude set to some convenient value, like 100mV (Vgen).

The jumper across the test resistor is removed and the generator frequency is swept up until the output voltage drops to 70.7% of the initial Vin (70.7mV), and the generator frequency is noted.

The frequency and the resistance are now known, so the capacitance can now be calculated from the RC formula:

Cin = 1 / (6.28 * R * F)

For example, using a 10Mohm series resistor, we find that the 100mV output drops to 70.7mV at 1.305kHz. So:

Cin = 1 / (6.28 * 10M * 1305)

Cin = 12.2pF

There are a few points to be aware of with this measurement. The first is the stray capacitance across the sense resistor, generally around 0.15pF to 0.3pF for 1/4-watt resistors, can affect the results. The way to avoid this problem is to use several lower value resistors in series to create one large sense resistor with low capacitance. Each resistor’s stray capacitance appears as a series capacitance, so the more resistors used in series, the less the total series capacitance.

To do this, the resistors are soldered end-to-end and allowed to bow up into the air, keeping away from nearby objects to minimize stray capacitance. For this measurement, five 2MΩ resistors were soldered end-to-end. See Figure 3 in Part 2 for a photo of the actual resistor string used.

The second point is to be aware of is the overall bandwidth of your circuit and to watch out for output slew rate limiting. It is a good idea that when you find the pole frequency, that you short the sense resistor again and make sure the amplitude is the same as the original reference frequency (~100mV) to verify you have not run out of bandwidth or hit slew rate limiting.

If the amplitude is not the same, increase the value of the sense resistor or add a known capacitance across the input to lower the pole frequency (add 20pF, then subtract 20pF from the result). Any capacitor type can be used for this test, as leakage is not important. To prevent slew limiting, use the lowest amplitude possible to achieve good results.

Summary

We hope this tutorial give you a better understanding of the challenges involved with sub-picoamp measurements. Creativity is the best tool at these levels. As with any time you are pushing up against the limits of nature, be prepared for minor setbacks and circuit or layout revisions.

Recommended Resources and Reading

Keithley Instruments, Inc. Low Level Measurements Handbook, 6th Edition. Cleveland, OH., 2004. Section 2 is of most general interest.

References

[6] “Op Amp Eval Board Cleaning for Femptoamp Bias Currents,” Texas Instruments Corporation website, online video now available at: http://www.ti.com/general/docs/video/Gallery.tsp?bkg=dark&entryid=0_65zy5r36&lang=en

Author’s biography

Paul Grohe is an applications engineer for Texas Instruments’ Precision Systems group. He attended the College of San Mateo (San Mateo, CA).

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