Intel will begin adding 2.5D and 3D packaging into its processors, following the lead set by IBM and AMD in recognizing that new packaging approaches are essential for improving performance and lowering power.

This shift won’t derail the semiconductor industry’s efforts to the reach future process nodes or continually shrink features, but it does add context for other factors that increasingly will help define technology progress in the future. Those factors include:

• Shortening distances that signals must travel between the processor, memories and I/Os;

• Reducing the resistance to driving those signals by using faster interconnects with improved bandwidth—thereby reducing both power and heat;

• The ability to optimize performance, power and cost more easily through different packaging options, and

• Improved time to market by using customized configurations from parts developed at a variety of process geometries.

For Intel, this is more than just a statement of direction. It’s a modification of a 2D approach to chip design that has defined the company since its inception. And if the past is any indication, it will be used as a stamp of approval by other chipmakers as they migrate to smaller geometries.

“We will start this year,” said Babek Sabi, Intel corporate vice president and director of assembly and test technology development. “That will be for servers. Adding this for the mass market involves us and memory suppliers and some others. There are a lot of people talking about it now. We expect it will move down in the market in the latter part of this decade.”

In a speech this week at SEMI‘s Integrated Strategy Symposium, Sabi said Intel has been studying how to best improve performance per watt for some time. “We have been looking at what are the options we have,” he said, adding that achieving “really high-speed I/O” is not possible without multi-chip packaging.



Source: Intel/SEMI ISS

That allows much more flexibility as to how various components in an SoC are assembled, with less focus on putting everything on the same die using the same manufacturing process. This is particularly problematic at advanced nodes, where RC delay is a growing problem due to extremely thin wires, resulting in thermal issues, electromigration, electromagnetic interference, power and signal noise issues in analog components, and an overall shortened lifespan for chips.

Intel has talked at a high level about its plans for 2.5D and 3D multi-chip packaging in the past, but the company has never offered a timetable or provided insight as to how it plans to use its Embedded Multi-Die Interconnect Bridge, which is a low-cost alternative to an interposer. Sabi said the EMIB, which also has lower resistance than a silicon interposer, will be used to connect the CPU with other chips, including Altera FPGAs. That will allow software to control which processing is done where, and to switch back and forth when performance is required or when power is more of a concern.

“You can have specialized FPGAs or general computing,” Sabi said. “You also can have tiny FPGAs scattered around.”



Source: Intel/SEMI ISS

Intel is by no means alone in developing these advanced packaging chips. AMD last year rolled out a 2.5D graphics card for gaming, which is one of the burgeoning markets for these higher-performance advanced packaging chips. AMD claims the package is 40% shorter, twice as fast, and runs 20° C cooler.

IBM has been making 2.5D and 3D server chips, as well, emphasizing performance and lower power. In an interview last October, Gary Patton, now CTO at GlobalFoundries, pointed to a 2.5D chip that IBM had developed that combined analog/mixed signal chips with ASIC chips.

What’s ironic here is that while advanced packaging approaches have been characterized as “More than Moore,” they might more accurately be labeled “the lesser-known side of Moore’s Law.” In his famous 1965 paper, Gordon Moore wrote, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.”

“Gordon Moore anticipated it and, ‘by definition,’ 3D-IC/system-in-package could be considered to be encompassed in the original concept of Moore’s Law,” said Greg Yeric, an ARM fellow. “We are already seeing multiple early adopters pushing the new technology.”



Source: ARM/IEDM

New possibilities

In fact, there have been numerous companies developing chips using new packaging approaches, including fan-outs and a new version of fan-out technology termed (at least for now) advanced fan-outs.

The earliest adopters of these new packaging approaches have been the networking equipment vendors, for whom performance is critical and prices are relatively flexible, and more recently the gaming market, where pricing is a bit more of an issue. Ron Huemoeller, corporate vice president of worldwide R&D at Amkor, said the big sticking point for many companies moving into this packaging approach remains cost. But he also said the cost equation is changing rapidly, in part because of economies of scale and in part because of the focus on new interposer technology.

“So far, the market for 2.5D has been interposer price-dependent, and that price curve remained static for years,” Huemoeller said. “But between 2013 and 2015, it dropped 40%.”

He said the gaming market has been able to justify that because of a system-level benefit in performance, a decrease in the number of layers on the motherboard and a decrease in the number of layers in graphics.

Amkor has been developing silicon-less integrated modules to cut the cost of TSVs as a way of gaining traction with 2.5D in the mobile market, which is extremely price sensitive. “If you take the TSV out, you do not have to sacrifice performance,”Huenmoller said. “You reduce the cost, lower the inductance, and you get just as good power benefits as a non-TSV interposer.”

He cited another potential market opportunity, which is shifting from a die-first to a die-last approach. With die-first, which is what TSMC offers, the die is glued face up on the package. With die last, the die is metallurgically attached to the die face down, which allows it to be thinned out more easily. He expects that approach to begin gaining traction this year and continuing through 2018, when there will be a combination of 3D-ICs, 2.5D TSVs for logic plus high-bandwidth memory, and 3D package-on-package with wafer-level multi-chip modules.

Both Intel and Amkor also cited panel-level rather than laser-level chip development, as well—large rectangles instead of round wafers. How that fares in the market remains to be seen. Yole Développement drew attention to this approach in a report two months ago, as well, saying that panel-level manufacturing developed by the PCB, flat-panel display and photovoltaic industries potentially can be adapted for a variety of chips ranging from high-end CPUs to power management modules.

Challenges remain

While Intel may be able to manage all of the pieces itself—manufacturing, packaging, chip development—it’s not so clear how the rest of the industry will fare with an advanced packaging model.

“People feel comfortable that there is enough yield and cost data and the supply chain is good enough,” said Huenmoeller.

Not everyone agrees, though, which is why there are so many different approaches being developed. Marvell‘s MoChi system-in-package relies on a menu of Marvell’s own technologies for the design (along with embedded ARM cores). HiSilicon has done the same at Huawei, which was one of the first commercial users of 2.5D chips.

The big foundries are a bit more hands-off when it comes to these choices, leaving it up to the chipmakers to shoulder the risk. While TSMC’s fan-out technology has gained traction, its 2.5D packaging approach is still being assessed. The same is true for GlobalFoundries’ packaging technology.

“With 2.5D, you can take out the MEMS and the sensors and put them on a separate chip, but you still have to deal with basic reliability issues, integration challenges, inventory management—getting all the different pieces together—as well as testability, yield fallout and accountability,” said Subramani Kengeri, vice president of global design solutions at GlobalFoundries. “If something goes wrong, who’s to blame?”

But at the most advanced nodes, and particularly where performance is either a differentiator or a prerequisite, not looking at new approaches may be a liability, as well. Just shrinking features has stopped paying dividends in terms of power and performance, and while increased density can help drive that performance, if the distances that signals have to travel are too long or there is too much resistance and capacitance, that can negate the benefits of shrinking features.

It’s also clear that not everyone will benefit from these changes, though it’s too early to tell who will be on which side. A new market study on packaging by Dan Tracy, senior director of industry research at SEMI, notes that fan-outs and other packaging options potentially will be disruptive to the supply chain because thin-film metallization will eliminate some substrate materials, while advanced packaging will reduce the need for underfill.

At the very least, advanced packaging adds another dimension to semiconductor design. That, in turn, opens up many more options about what pieces can be put together, by whom, for what price, and how quickly. But it also increases the level of uncertainty in an industry that prides itself on proven processes and very low risk.