ESD (electrostatic discharge)—the sudden andmomentary electric current that flows betweentwo objects at different electrical potentials—causes equipment failure and network downtime,thus causing production losses of multiple billionsof dollars annually. From portable consumer electronicsto industrial-automation, process-control systems, andmilitary and aerospace applications, every electronics manufacturermust consider ESD during equipment design. Myriadtesting standards exist for addressing the range of technicalrequirements of the various industrial segments.

To help you select the correct testing standard for a design,you need to understand the main ESD standards and thedifferences between device- and system-level testing. ESDprotection includes a range of protection schemes, the mostcommon of which are steering-diode arrays, TVS (transient-voltage-suppressor) diodes, and zener diodes. No matterwhich protection scheme you select, you must perform afinal EMI (electromagnetic-interference) test and a test ofthe protection circuit itself.

HBM testing



The HBM (human-body-model) device-level test is the mostcommon model for ESD testing. It is used to characterize thesusceptibility of an electronic component to ESD damage.The test simulates an electrical discharge of a human ontoan electronic component, which could occur if a human hasbuilt up residual charge—for example, by dragging his feet, insocks, across a carpet and then touching an electronic device.The failure modes for the HBM testing of ICs typically comprisejunction damage, metal penetration, melting of metallayers, contact spiking, and damage to the gate oxides.

You set up the test procedure by applying a high-voltagesupply in series with a 1-MΩ resistor and a 100-pF capacitor.After the capacitor is fully charged, a switch is used to removeit from the high-voltage supply and series resistor and to applyit in series with a 1.5-kΩ resistor and the DUT (device undertest). The voltage thus fully dissipates through the resistorand the DUT (Figure 1 ). Values for the high-voltage supplyrange, according to the test level, from 0.5 to 15 kV. You set up the test procedure by applying a high-voltagesupply in series with a 1-MΩ resistor and a 100-pF capacitor.After the capacitor is fully charged, a switch is used to removeit from the high-voltage supply and series resistor and to applyit in series with a 1.5-kΩ resistor and the DUT (device undertest). The voltage thus fully dissipates through the resistorand the DUT (). Values for the high-voltage supplyrange, according to the test level, from 0.5 to 15 kV.

Figure 2 shows a typical oscilloscope readout with an initialcurrent spike as large as 1.4 to 1.5A when the capacitorstarts discharging and the ramp-down until it asymptotically approaches 0A at approximately 500 nsec. The DUT canexperience a maximum power of 22.5 kW at a single dischargeevent on a traditional HBM. Keep in mind that power equalsthe current times the voltage. shows a typical oscilloscope readout with an initialcurrent spike as large as 1.4 to 1.5A when the capacitorstarts discharging and the ramp-down until it asymptotically approaches 0A at approximately 500 nsec. The DUT canexperience a maximum power of 22.5 kW at a single dischargeevent on a traditional HBM. Keep in mind that power equalsthe current times the voltage.

MM testing

The MM (machine-model) device-level test, which emergedin the 1990s, is now less common than the HBM test.Industrial-automation-manufacturing sites became increasinglypopular in the ’90s to increase output. These machines become electrically charged after turn-on and discharge intoan electronic component after making contact. Thus, MMtests became a model for testing this type of ESD event.Failure modes in MM testing are similar to those in HBMtesting. These failure modes include junction damage, meltingmetal layers, and gate-oxide damage.

You set up the test procedure for MM testing with a high-voltagesupply in series with a resistor and a 200-pF capacitor.After the capacitor fully charges, a switch is used to removeit from the high-voltage supply and series resistor and thenapply it in series to a 0.5-μH inductor and the DUT. Theinductor with the capacitor voltage dissipates through theDUT (Figure 3 ). Traditional values for the high-voltagesupply can vary, but the most common range is 50 to 400V. You set up the test procedure for MM testing with a high-voltagesupply in series with a resistor and a 200-pF capacitor.After the capacitor fully charges, a switch is used to removeit from the high-voltage supply and series resistor and thenapply it in series to a 0.5-μH inductor and the DUT. Theinductor with the capacitor voltage dissipates through theDUT (). Traditional values for the high-voltagesupply can vary, but the most common range is 50 to 400V.

When looking at an oscilloscope measurement of currentover time, you can see that the RLC (resistance/inductance/capacitance) circuit creates an alternating current (Figure 4 ).The current reaches approximately ±3A, which is about four times higher than the HBM’s peak-to-peak current amplitude.Furthermore, the dissipation is much longer for the MM testbecause it is still asymptotically approaching 0A at 900 nsec(Figure 4 ). The DUT experiences a maximum power dissipationof approximately 1.2 kW during an MM discharge event. When looking at an oscilloscope measurement of currentover time, you can see that the RLC (resistance/inductance/capacitance) circuit creates an alternating current ().The current reaches approximately ±3A, which is about four times higher than the HBM’s peak-to-peak current amplitude.Furthermore, the dissipation is much longer for the MM testbecause it is still asymptotically approaching 0A at 900 nsec(). The DUT experiences a maximum power dissipationof approximately 1.2 kW during an MM discharge event.

MM testing requires that you test each pin on the DUTto its standard. The electronic chip is mounted on a speciallydesigned load board that interfaces with an automated ESDtester. You ground the other pins on the board and thenindividually test each pin. You continue this procedure untilall pins have been tested.

CDM testing



The CDM (charged-device-model) device-level testing procedureis a simulation for situations that often happen inautomated-manufacturing environments in which machinesoften remain on indefinitely, causing the electronic ICs toelectrically charge over time. When the part comes intocontact with a grounded conductor, the built-up residualcapacitance discharges. For the CDM test, the DUT is placedon its back facing upward on a testing board.

A probe then approaches the pin under testwhere an ESD event occurs. Monitoring the ground connectionof the pin under test verifies this action. Repeat this teston each pin of the DUT for three positive and three negativepulses. The result is six total discharges per pin (Figure 5 ). Separate the metal field plate and the DUT with aninsulating material, which acts as a capacitor between thetwo objects. You then connect the metal field plate to a high-voltagesupply and increase its voltage to the required CDM-test-voltage level.A probe then approaches the pin under testwhere an ESD event occurs. Monitoring the ground connectionof the pin under test verifies this action. Repeat this teston each pin of the DUT for three positive and three negativepulses. The result is six total discharges per pin ().

Figure 6 indicates that the CDM discharge takes placeover 2 nsec at most, which makes it difficult to test and tomodel. This test results in a current of 5 to 6A discharging inless than 1 nsec. The current dissipates within 5 nsec, makingthis part of the test succinct but volatile. Due to this fasttransient, the failure modes typically seen in CDM tests aregate-oxide damage, charge trapping, and junction damage.Figure 6 shows the current waveform during a CDM test.

The HBM, MM, and CDM are the most common ESDdevice-level testing procedures for electronic components.Table 1 summarizes their similarities and differences.

ESD immunity



The system-level ESD-immunity test simulates the ESDof a human onto an electronic component (Figure 7a ).Electrostatic charge on a human can develop in low relativehumidity, on low-conductivity carpets, and on vinyl garments.To simulate a discharge event, an ESD generator applies ESD pulses to the EUT (equipment under test) in two ways. The firstis through contact discharge, or direct contact with the EUT,in which something makes physical contact with the EUT. Thesecond is through air-gap discharge, or indirect contact withthe EUT, in which the discharge occurs through the air. TheIEC (International Electrotechnical Commission) defines thistest in the IEC61000-4-2 ESD-immunity-test specification.

Characteristics for this test are a rise time of less than 10nsec and a pulse width of approximately 100 nsec, indicatinga low-energy, static pulse. The ESD-immunity test requiresthat you administer at least 10 discharges of both positiveand negative polarity at 1-sec intervals. Thus, you test theEUT at least 20 times for the ESD-immunity system-levelspecification (Figure 7b ).

Figure 8 shows the differences between device- and system-level testing standards. The IEC ESD test, which manyconsider the gold standard for component testing, typicallyhas an eight-times-higher testing voltage than CDM and20-times-higher peak-current testing than HBM.

EFT immunity



The system-level-testing standard of IEC61000-4-4 is the EFT(electrical-fast-transient) immunity-testing model (Figure 9a ).The EFT-, or burst-, immunity test simulates transients thatcan happen in everyday environments due to switching offinductive loads, relay-contact bounce, and the operation of dcor universal motors. This test is performed on all power, signal,and earth wires. A burst is the sequence of pulses with a finiteduration. In the EFT-immunity test, a burst generator producesa sequence of test pulses that attenuate to 50% of their peakvalues in less than 100 nsec. The next adjacent pulse typicallyoccurs 1 μsec later. A burst typically lasts for 15 msec, and theburst period, the time from one burst’s start to the next burst’sstart, is 300 msec. This cycle repeats for 10 sec, after whichthere is no testing for 10 seconds. This scenario represents onetest cycle. The test cycle must repeat six times, taking 110 sec.The significance of the EFT-immunity test is its short pulse risetimes, high repetition rates, and low energy content.

Although the fast rise time and the low energy contentof an EFT are somewhat similar to those of an ESD pulse,the number of pulses per test cycle is not. Assuming a 1-μsecinterval between one pulse front and the next, a 15-msec EFTburst contains at least 15,000 pulses. Multiplying the numberof bursts within a 10-sec window yields 10 sec/300 msec=33.3bursts and 500,000 pulses per 10-sec window. Thus, theapplication of six 10-sec windows with a 10-sec pause intervalresults in 3 million pulses within 110 sec.

Because EFT testing involves no direct contact of conductorsbut instead the indirect application through a capacitiveclamp, proper, industrial-grade cabling with internal shieldingcan produce great results to the DUT by drastically attenuatingthe coupling of EFT energy into the conductors (Figure 9b ).

Surge immunity



The surge-immunity, or lightning, test, IEC61000-4-5, representsthe most severe transient-immunity test in current andduration (Figure 10a ). However, testers often employ it on signaland power lines longer than 30m. The surge-immunity testsimulates switching transients due to direct lightning strikes;induced voltages and currents due to indirect strikes; or switchingthe power systems, including load changes and short circuits.

The test specifies the surge generator’s output waveformsfor open- and short-circuit conditions. The ratio of the opencircuit’s peak voltage to the short circuit’s peak current isthe generator’s output impedance. High current due to lowgenerator impedance and pulse duration approximately 1000times longer than the ESD- and EFT-immunity tests characterizethis test, indicating a high-energy pulse.

This test requires five positive- and five negative-surgepulses with a time interval between successive pulses of oneminute or less. A common procedure is to shorten the pauseintervals to 12 sec, thus reducing total test time to less thantwo minutes. Although this approach intensifies the surgeimpact due to the protection circuits’ reduced recovery timebetween pulses, it contributes to a significant reduction intest cost (Figure 10b ).

System-level testing



The IEC compiles the system-level-testing standards accordingto IEC61000-4. This family of standards includes approximately25 system-level-testing specificationsfor transient-immunity testing:IEC61000-4-2 for ESD, IEC61000-4-4for EFT, and IEC61000-4-5 for lightning.Table 2 compares these tests.

Today’s rising demands for system-leveltesting renders inadequate device-leveltesting at the low voltage/currentlevels of HBM, MM, and CDM. Astrong distinction exists between systemESD and burst/surge-level testingbetween consumer products and industrialequipment and systems, however. Inconsumer designs, ESD testing assumes ahigh priority due to the increased probabilityof human contact with electroniccomponents through cable connectors.

In strong contrast, industrial designersrate the burst- and surge-immunitytests higher than ESD testing. In thiscase, the daily bombardment of electricaltransients due to electric motorsand other inductive switching loadsposes far greater risks to the systemthan ESD, whereas human contactoccurs only during system installationand maintenance and even thenonly when the operator is wearingESD-protection gear. For more informationabout ESD and testing, visitwww.ti.com/esd-ca.

Acknowledgment

This article originally appeared on EDN ’ssister site, Planet Analog.

Authors' biographies

Dwight Byrd is a product-marketing engineer in the precision-analog group at Texas Instruments, where he is responsible for ADCs. Byrd was previously part of TI’s interface group, where he was responsible for ESD/EMI products, I2 C peripheral devices, signal switches, and voltage-level translators. He received a bachelor’s degree in electrical engineering from Texas A&M University (College Station, TX). Dwight Byrd is a product-marketing engineer in the precision-analog group at Texas Instruments, where he is responsible for ADCs. Byrd was previously part of TI’s interface group, where he was responsible for ESD/EMI products, IC peripheral devices, signal switches, and voltage-level translators. He received a bachelor’s degree in electrical engineering from Texas A&M University (College Station, TX).