ANTWERP, Belgium — A startup led by one of the pioneers of flash memory worked with the Imec research institute to design the smallest SRAM cells to date. The 0.0205-mm2 and 0.0184-mm2 6T-SRAM cells use a vertical gate-all-around transistor being developed by Unisantis as a building block for tomorrow’s leading-edge chips.

The work was one of a handful of announcements at the opening day of the Imec Technology Forum. Other news here includes work on more accurate indoor location over Bluetooth, a dense lab-on-a-chip, and a camera-free approach to eye tracking, all developed solely by Imec.

A team from Unisantis and Imec is using the startup’s so-called Surrounding Gate Transistor with a 50-nm-minimum pillar pitch. The design is suited to a 5-nm SRAM but is less optimal for logic because it would require three of the transistors to provide the performance of a single FinFET.

The Unisantis design is similar to what’s generally known as a vertical nanowire, a candidate for years as a future transistor. They have the potential to reduce chip area significantly, one of the last remaining areas of progress in CMOS scaling.

To date, most researchers see vertical transistors as having challenges that prevent their practical use in commercial chips for many years. The Unisantis design, in particular, would need two to three times more performance to compete in logic with FinFETs.

FinFETs are expected to scale down to use through the 5-nm node expected to hit volume production in 2020. A horizontal gate-all-around transistor, sometimes called a nanosheet, nanowire, or nano-slab, is widely expected to be its successor at the 3-nm node.

The CTO of Unisantis, Fujio Masuoka, was a pioneer of NAND at Toshiba in the 1980s. His startup clearly aims to pioneer a next-generation transistor that could someday be even more fundamental to tomorrow’s semiconductors.

In February, Samsung reported on a 6T 256-Mbit SRAM with a 0.026-mm2 bit cell that it made using FinFETs and extreme ultraviolet lithography (EUV), the smallest device at that time. The Korean giant said that it had test silicon of the design that gave it confidence in its plans to be the first to use EUV commercially.

The Unisantis design represents a significant shrink over the Samsung work, which, at the time, leapfrogged the work of chip giant Intel. Using EUV, the Unisantis transistor could be made in a 5-nm process at a cost comparable to a FinFET SRAM, according to a press release from Imec.

“The big three are working on gate-all-around (GAA) technology,” said G. Dan Hutcheson, president of VLSI Research. “IBM has been working on vertical nanowire GAA for years. … With Unisantis in the game, it could be the biggest legal catfight since Rambus took on the industry in the ’90s.”

However, the market watcher noted that “this is not a simple research project that can be executed in small research facilities like Imec. You need manufacturing scale to scale up from the transistor to finished designs that can be made economically enough to be salable at anything but a loss.”