When Intel launched Ivy Bridge last week, it didn’t just release a new CPU — it set a new record. By launching 22nm parts at a time when its competitors (TSMC and GlobalFoundries) are still ramping their own 32/28nm designs, Intel gave notice that it’s now running a full process node ahead of the rest of the semiconductor industry. That’s an unprecedented gap and a fairly recent development; the company only began pulling away from the rest of the industry in 2006, when it launched 65nm.

We recently had an opportunity to talk with Mark Bohr, Senior Intel Fellow and the Director of Process Architecture and Integration at the company’s engineering fabs in Hillsboro, Oregon. We asked him to explain how Intel had managed to keep its two-year tick-tock cadence and why Santa Clara’s manufacturing is regarded as the best in the world.

Bohr attributes Intel’s success to several factors. First, Intel is virtually the only IDM (Integrated Device Manufacturer) left in the microprocessor business. Even companies like Samsung and IBM, which still handle a significant amount of their own product manufacturing, have teamed up with GlobalFoundries to jointly focus on R&D. The rest, like Qualcomm, Nvidia, Toshiba, and Texas Instruments, outsource their manufacturing to companies like TSMC, UMC, and GlobalFoundries.

Because it manufacturers all its own hardware, Intel avoids the conflict of interest that inherently exists in any foundry/customer relationship. The increasing difficulty and cost of transitioning to new nodes has amplified tensions between the two groups that were previously kept to a minimum thanks to the combined effect of Moore’s law and Dennard scaling. Moore’s law states that transistor density doubles every 18-24 months; Dennard scaling predicted a proportional, linear relationship between the size of a transistor and its voltage/current draw. Smaller transistors, in other words, draw less power.

Node transitions were still difficult and occasionally rocky, but the end results were fundamentally predictable. Higher short-term costs and greater defect densities would be more than offset as the new node came online and yields improved. That underlying predictability is what made the pure-play foundry model work. In its absence, we’ve seen customers like Nvidia pushing for new agreements in which custom IP design, R&D costs, and risk production expenses are shared more equitably between foundry and customer.

Bohr didn’t specifically distinguish between small, group-level collaboration and the large-scale sharing of information between different sections of the company, but his comments made it clear that design and implementation are treated as a joint effort at every level — including when things go wrong. This reduces the chance of an “us vs. them” mentality developing between groups of engineers and encourages further collaboration to solve the problems that do occur, rather than circling the wagons and going into CYA mode.

Next page: The Copy Exactly method, and tick-tock cadence