With AMD readying quad-core variants of its Ryzen "Summit Ridge" processor, the question on everyone's minds is whether the chip features two quad-core compute complexes (CCX) with two cores enabled, each, or just one CCX, given that the L3 cache amount being advertised by the company is 8 MB (that of one CCX), in comparison to 6-core Ryzen parts receiving the full 16 MB (8 MB per CCX) available on the silicon. While we will be able to definitively answer that question on the 11th of April, a new UEFI firmware by ASUS for its Crosshair VI Hero motherboard lets users not just disable cores, but also the distribution of the disabled cores.CPU cores on the Ryzen "Summit Ridge" processor are distributed in two groups of four cores, each, called the quad-core compute complex (CCX). Each CCX has an 8 MB L3 cache, and so the ideal way of distributing cores on lower core-count models would be to disable an equal number of cores per CCX. For 6-core chips, one core is disabled per CCX, resulting in a 3+3 configuration. For quad-core chips, however, you can either disable all four cores in a CCX (4+0 configuration), or do a purportedly more optimal 2+2 configuration, with two cores disabled per CCX. Hardware Unboxed took advantage of ASUS' new UEFI firmware to compare the 4+0 configuration to the 2+2 configuration. The results are somewhat surprising.As you can see in the graphs above, there is practically no performance difference between the 4+0 configuration and the 2+2 configuration. In fact, the 4+0 configuration is mildly faster in some scenarios. AMD already advertised quad-core Ryzen parts to feature just 8 MB of L3 cache, and so it could make more sense to keep all 8 MB in one CCX, and disable an entire CCX to run the chip in a 4+0 configuration, than disabling 4 MB per CCX, and running it in a 2+2 configuration. This way, a single core can dump >4 MB of data onto the L3 cache it addresses (as opposed to being limited to 4 MB in a 2+2 configuration with just 4 MB per CCX). Inter-CCX communication may be fast, but not fast enough to make a core from one CCX address the L3 cache of another CCX (which by the way is not possible, according to AMD). This is what makes 4+0 a more desirable configuration for the upcoming quad-core Ryzen parts, than 2+2.