This tutorial will walk through an audio echo that can be implemented on an FPGA development board. This tutorial is quite a bit more involved than the previous MyHDL FPGA tutorial. This project will require an FPGA board with an audio codec and the interface logic to the audio codec.

Review the Previous Tutorial

The previous MyHDL FPGA tutorial I posted a strobing LED on an FPGA board. In that tutorial we introduced the basics of a MyHDL module. To review, we described the hardware to control the LED.

The signal strobe is a periodic signal that strobes at the rate defined by the parameter LED_RATE. And the logic describes how the LEDs blink, in this case the led_bit_mem (a.k.a an enhanced shift register) will shift the 1 (the on bit) right or left depending on the current direction (state). In the LED example, a simple boolean is used to keep track of the state (direction).

After the design is verified with the original verification code. The design is run through the FPGA tools driven by Python scripts. The scripts and vendor tools generate and load the bit-stream onto a development board.

Note, these tutorials assume the reader is familiar with an existing HDL and/or will need to refer to the MyHDL manual. These tutorials implement a design and see it run on the FPGA and not an in depth guide to using MyHDL as a hardware description language.