For years, Extreme Ultraviolet Lithography (EUV) has been broadly painted as the future of the industry, even as its supposed integration into mainstream manufacturing has been shoved further and further into the future. Now, a group of researchers at MIT have demonstrated compelling evidence that Directed Self-Assembly (DSA) might be an easier way to manufacture chips below 10nm, provided certain problems can be overcome.

DSA isn’t a standalone manufacturing process. It’s a complementary method of printing structures using chemical processes. There are materials that self-assemble at the nanoscale when “directed” to do so with one of a variety of techniques. Here’s how MIT News describes the process:

First, a pattern of lines is produced on the chip surface using well-established lithographic techniques… Then, a layer of material known as a block copolymer — a mix of two different polymer materials that naturally segregate themselves into alternating layers or other predictable patterns — is formed by spin coating a solution… Finally, a top, protective polymer layer is deposited on top of the others using initiated chemical vapor deposition (iCVD).

The original lithographic pattern forms the guide for the copolymer line position. But the chemical process results in lines that are much smaller than the original, as shown below:

The fact that research teams at MIT, the University of Chicago, and Argonne National Laboratory have managed to create lines below the 10nm mark is impressive in and of itself. But the same image that proves the achievement also demonstrates a major problem with the technology. Look at the image, and you’ll see that the lines are scarcely straight, with several of them nearly touching at various points. The deviation of a feature edge from its ideal shape is called line-edge roughness (LER). It’s a significant problem in multi-patterning, but it’s an even more significant issue in DSA.

To understand why LER is a major roadblock, imagine being asked to freehand draw two straight lines one foot apart, with no more than a two-inch deviation from a perfectly straight line. Now, imagine being asked to freehand draw two lines 2 millimeters apart, with a 0.33mm deviation from a perfectly straight line. The first task isn’t particularly difficult; the second would be impossible for most of us. As process nodes shrink, the margin of error for line noise shrinks as well.

Over at Semiengineering, Mark Lapedus delved into why DSA hasn’t been as successful as some thought it would be. The silicon industry has, thus far, flung most of its resources towards multi-patterning in the short-term and EUV in the long term. It may be possible to build memory chips, with their extremely regular structures, using DSA, but logic circuits (CPUs, ASICs) face daunting challenges:

“There are particular challenges for logic,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries. “To get the types of shrinks we need, we need to have more than a single pitch. Getting that for line/space patterns with DSA is problematic today. Again, when you try to use it for contact and via layers, it’s getting the non-periodic structures that you get in random logic. There also has to be a lot more work done on the lithography design co-optimization side to make this work. There needs to be more work that takes place in terms of creating a low defect process on the wafer. There are still a lot of substantial issues here.”

This is not to say that the current work on directed self-assembly at the 10nm node isn’t important, or that it’s doomed to fail. But there doesn’t seem to currently be much of a market for DSA products or near-term integration with standard lithography manufacturing techniques.

Now read: The myths of Moore’s Law