At IEDM Intel and Micron presented “A Floating Gate Based 3D NAND Technology With CMOS Under Array” authored by Krishna Parat and Chuck Dennison.

As I previously discussed in my blog on the IEDM memory short course and blog on IMEC’s work on high mobility 3D NAND channels, continuing to scale 2D Flash has become extremely difficult and the major Flash producers are all moving to 3D NAND.

The memory short course blog can be accessed here.

The IMEC high mobility channel for 3D NAND can be accessed here.

Samsung was the first to introduce 3D NAND with their Terabit Cell Array Transistor (TCAT) and Toshiba has been in hot pursuit with their Bit Cost Scalable (BiCS) approach. Both of these approaches plus proposed 3D NAND from SK Hynix and Macronix have all been based on a charge trap devices where a silicon nitride layer is used to trap electrons.

The basic process for these devices can be thought of in three parts:

CMOS – the fabrication of CMOS to control access to the memory array.

Memory array – deposition of the memory layers, channel, slot and stair step formation.

Interconnect – interconnect of the CMOS and memory array.

To-date the 3D NAND devices in production have been charge trap based memory cells and the CMOS has been arranged off to the sides of the memory array.

In the Intel-Micron paper the first floating gate 3D NAND cell is described as well as the first instance of the CMOS being fabricated under the memory array.

The fabrication of CMOS under the memory array follows a flow similar to CMOS off to the side but adds interconnect that will also be under the memory array. We expect a pair of tungsten interconnect layers will be required.

The memory array fabrication begins with deposition of oxide and polysilicon layers pairs. The devices described in the paper has 32 memory layers plus select transistor layers and dummy layers. After the layers are deposited the array formation proceeds as follows:

[LIST=1]

Cell hole formation.

Etch back the gate polysilicon layers to create a recess.

Interpoly dielectric formation – I believe this is ONO.

Floating gate deposition – I believe this is polysilicon.

Floating gate etch back to isolate the floating gates, basically islands of polysilicon are created in the recesses formed in step 2.