Early access programme for PolarFire FPGAs

29 January 2020 Programmable Logic

The trend towards compute-intensive gateways and edge devices is driving the integration of traditional deterministic control applications with additional embedded processing capabilities needed for smart and secure connected systems.

In response, Microchip Technology is opening the Early Access Programme (EAP) for the PolarFire system-on-chip (SoC) field programmable gate array (FPGA). The platform offers the world’s first hardened real-time, Linux capable, RISC-V-based microprocessor subsystem on the award-winning, mid-range PolarFire FPGA family, bringing low power consumption, thermal efficiency and defence-grade security to embedded systems.

Qualified EAP customers can start designing now with Microchip’s Libero SoC 12.3 FPGA design suite and SoftConsole 6.2 integrated development environment (IDE) for the embedded developer. Customers can also debug their embedded applications today using Renode, a virtual model of the microprocessor subsystem.

PolarFire SoC delivers power efficiency that is up to 50% lower power than competitive devices in the industry. This provides numerous customer benefits including reduced bill of materials by eliminating the need for fans and heatsinks. It’s the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux plus real-time applications.

The support of real-time and rich operating systems like Linux is part of Microchip’s growing Mi-V RISC-V ecosystem, a comprehensive suite of tools and design resources developed by Microchip and numerous third parties to fully support RISC-V designs. Ecosystem partners ready to support PolarFire SoC include WindRiver, Mentor Graphics, WolfSSL, ExpressLogic, Veridify, Hex Five, and FreeRTOS as well as development tools from IAR systems and AdaCore.

PolarFire SoC includes extensive debug capabilities including instruction trace and passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors from Mi-V partner UltraSoC, 50 breakpoints, FPGA fabric monitors, and Microchip’s built-in two-channel logic analyser SmartDebug.

The PolarFire SoC architecture includes reliability and security features such as single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a differential power analysis (DPA)-resistant crypto core, defence-grade secure boot and 128 Kb of Flash boot memory.

Credit(s)

ASIC Design Services





