Yesterday it was the “roof tile” method of stacking memory chips, and today IBM and 3M have announced that they are teaming up to develop a silicon glue that can be used to form “towers” out of hundreds of discrete chips. The end result, according to IBM, would be processors that are 1,000 times more powerful than those currently on the market — and a resounding shattering of Moore’s law.

If the video (embedded below) is to be believed, IBM and 3M hope that this adhesive will make chip stacking a simple matter of applying a blob of glue, slapping on a billion-transistor wafer, and then repeating the process 100 times. In reality, it will probably be more complex, but it will ultimately come down to how each of the chips are interconnected. In the video it looks like each chip would have a standard pin grid array on the bottom, and a ball grid array on the top… and everything would be simply connected in series.

Chip stacking, or multi-chip modules (MCM), 3D packaging is already used in some mobile- and server-class processors, but it is generally limited to stacking memory on top of a CPU. IBM and 3M’s completely-generic approach, where every chip can be stacked on top of each other, will certainly require some new chip designs — but you’ll probably be unsurprised to hear that, out of all chip foundries, IBM probably has the most experience with 3D packaging. It’s worth noting that 3D packaging is nothing like Intel’s Tri-gate transistors, which have a height of just a few nanometers. You could glue together multiple Tri-gate chips, though, which will no doubt be branded “4D,” or perhaps 6D…

With regards to heat dissipation, the gooey glue would also have the properties of a thermal paste — though how that helps a chip at the bottom of a 100-storey stack, we’re not entirely sure. Perhaps the heat can be transferred to the edge of the chip? But even then, the surface area on the side of a chip is tiny. Considering we are reaching the limits of air-cooling, stacking chips seems rather counterintuitive — but we’ll just have to assume that IBM and 3M have a plan. The fact that the chips are so close together will certainly allow for lower power consumption — electricity has to travel over less copper wire between each chip — but it’s still 100 silicon dies within the same square inch.

If their adhesive works, though, the pay-off will be huge. Instead of fashioning large, expensive SoCs using the same process, tablets and smartphones could use stacks of small, low-cost, commodity chips. The fact that IBM itself thinks that these “bricks” of silicon could be 1,000 times faster than today’s single-layer CPUs and GPUs means that exciting times lay ahead for PC users and console gamers, too.

Finally, with regards to a release schedule, IBM and 3M hope that their adhesive and related chip fabrication technologies will be ready by 2013 — and, according to the The Register, IBM is already using an adhesive to glue together some of its chips, so 2013 might even be on the conservative side.