It has been a little while since I have posted, however, I have been dedicating some time for research and would love to share my findings with the Publish0x audience...so here goes!

Mining algorithms are very complicated concepts to wrap your head around! With thousands of blockchains and hundreds of mining algorithms, it becomes a very challenging task to remain up-to-date and monitor the progression of every individual algorithm!

If you have been wondering what the X16R or X16Rv2 algorithms are don’t worry, I’ve got you completely covered here!

So, What IS The X16R Algorithm?

The X16R mining algorithm is a descendant of the X11 hashing algorithm, an algorithm that runs 11 hashing functions and was primarily implemented on Dash. The X11 hashing algorithm was great because it ran 11 different hashing functions - making it difficult for any particular mining sector to dominate the market. Similarly, the X16R runs 16 hash functions in its series.

The great thing about X16R is the fact that it becomes very problematic for it to be implemented into ASICs, due to the 16 hash functions and the random order that each hash function is used.

Why Is It Important To Become ASIC Resistant?

ASIC stands for Application-Specific Integrated Circuit. They are specialist mining machines that are solely dedicated to hash on that specific mining function - bringing super high hash rates!

As the devices are “application-specific” this means they are purposely built to mine on that particular hashing algorithm.

As ASICs create a higher hash rate than GPUs, they eventually always take up the majority of the network hashing rate. This tends to reduce the distribution and introduce centralization within a token economy that causes uncertainty and instability as the coin is in danger of ending up in the hands of a small number of holders.

If the development team of a particular coin decides to change algorithms, that particular ASIC mining device becomes obsolete.

In the X11 algorithm, the order of the 11 hashing functions was in a fixed particular order. This made it extremely easy for ASIC manufacturers to configure their machines to mine on X11.

How Does The X16R Algorithm become ASIC Resistant?

The X16R seeks to disrupt ASICs by always changing the ordering of the hashing algorithms. The order is changed depending on the hash of the previous block. The output of 1 block becomes block the input of the next block - leading to a new order in mining algorithms.

Here is a list of all of the hashing algorithms used on X16R;

BLAKE, BMW, Groestl, JH, Keccak, Skein, Luffa, Cubehash, Shavite, Simd, Echo, Hamsi, Fugue, Shabal, Whirlpool, Loselose, Djb2

Each algorithm is assigned a number or a letter according to the following table.

The system works by taking the hash value of the previous block as an input to determine the current block’s sequence of hash functions. The last 8 bytes of the previous hash block determines the order of the next hashing sequence. So, if the previous block hash was;

0000000000000000007e8a29f052ac2870045ae3970270f9​7da00919b8e86287

The final 8 bytes are;

0x7da00919b8e86287

This equates to the next block sequence to becoming;

cubehash (7) -> shabal (D) -> echo (A) -> blake (0) -> blake (0) -> simd (9) -> bmw (1) -> simd (9) -> hamsi (B) -> shavite (8) -> luffa (6) -> groestl (2) 0> shavite (8) -> cubehash (7).

Quite an intuitive solution right?

Which Coins Have Implemented The X16R Algorithm?

Ravencoin, launched in Jan 2019, is one of the most popular cryptocurrencies that implement the X16R algorithm.

The Ravencoin blockchain allows users to transfer ownership of unique assets. They have created a “fully asset aware system” in which unique assets can be created in the form of tokenized securities. The team plans to utilize this feature by tokenizing assets such as precious metals, currency, land deeds, and shares of companies. Find out more about Ravencoin here.

The team at Ravencoin has a very interesting attitude toward the development of their coin. The team is created through a group of voluntary developers that all work together to build the Ravencoin platform. For this reason, the team has often stated that their project is one of the only “true” decentralized open-sourced projects as they can’t even create partnerships as there “isn’t anyone to sign any partnerships or an entity to sign them for”.

The developers work together according to the schedule of the Ravencoin roadmap, which can be found here. Furthermore, the developer all agreed to keep ASICs off the Ravencoin network by utilizing the X16R algorithm.

It is important to highlight the fact that the X16R algorithm is not foolproof at preventing ASICs from entering into the market. In fact, in July 2019, a Ravencoin user posted an article that detailed that ASICs had indeed entered into the Ravecoin mining arena.

As a result of this article, the Ravencoin developers decided to conduct a hard fork in October 2019 that would see the release of a new mining algorithm - X16Rv2.

What Is X16Rv2?

The X16Rv2 is the Ravencoin team’s solution to preventing ASICs on their network. The algorithm upgrade introduced the Tiger function in three different parts of the X16R algorithm which will be executed before the Luffa, Kecca, and SHA-512 algorithms.

This solves the problem as it introduces another hashing function into the network that ASICs have not been programmed to mine upon - preventing their activity on the Ravencoin network.

Is It A Never-Ending Race To Keep ASICs Away?

This only seems like a tempory solution and should only be expected to give a few months of relief for GPU owners as we can only assume that ASICs will be re-programmed to be able to mine this new hashing function - eventually!

This creates a scenario in which any coin that runs the X16R algorithm will have to actively monitor their networks for the re-entrance of ASICs. Once ASICs re-enter the network, the team will have to introduce another hashing function to prevent the ASICs from mining on the network - creating a never-ending race for the developers in the battle to remain ASIC resistant.





