In this tutorial we will see how to design and test a VHDL component. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see:

The tutorial comprises three chapters, and it is divided into three entries of this blog. Make sure that you haven't missed to visit part 2 and part 3 of the tutorial!

For this tutorial it is assumed that you already have basic knowledge of the VHDL language and know how to use simulation tools (We will use the Xilinx's Vivado built in simulator, but you can easily adapt the tutorial to other tools you may be familiar with).

Chapter 1 - Simple implementation

Over the chapters of the tutorial we are going to generate random numbers by HW. One popular way of generating pseudo-random numbers by HW is by using an LFSR. LFSR stands for Linear-Feedback Shift Register.

The input bit to the shift register is a linear function of its previous value. The generation of pseudo-random sequences is based on linear algebra, where the register is interpreted as a polynomial. Each bit in the register is the coefficient or order 'n' of such a polynomial.

n -1. There are 'recipes' for the linear feedback function needed to generate maximum length sequences for any register length. For further reading you can check



Mike Field correctly pointed to me that an LFSR is a random BIT generator. So to generate an 'n' bit random NUMBER, we must advance the LF Shift Register by 'n' positions.

Hence, in this tutorial we will first make and test a random bit generator using an LFSR, and then, in later chapters, we will activate the LFSR 'n' times to generate a random number. A register of length 'n' can generate a pseudo-random sequence of maximum length 2-1. There are 'recipes' for the linear feedback function needed to generate maximum length sequences for any register length. For further reading you can check this application note from Xilinx.Mike Field correctly pointed to me that an LFSR is a random BIT generator. So to generate an 'n' bit random NUMBER, we must advance the LF Shift Register by 'n' positions.Hence, in this tutorial we will first make and test a random bit generator using an LFSR, and then, in later chapters, we will activate the LFSR 'n' times to generate a random number.

Let's see our first version of a pseudo-random bit generator written in VHDL.

For this first example, the polynomial order is very low, i.e. 3, which generates a sequence consisting of only 15 states. The polynomial order is one less than the quantity of bits of the register. Each bit in the register is a coefficient of the polynomial, from a 0 to a n -1 . In our first case, from a 0 to a 3 . For each state the output will be either '0' or '1', since this is a pseudo-random bit generator. If we keep running the simulation, these 15-values pseudo-random bit sequence will repeat indefinitely.

That is the reason why these sequences are called pseudo-random. They have a certain variability, but on the other hand, they are repetitive, and even if they don't generate a trivial sequence, they always will produce the same sequence.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 library ieee ; use ieee.std_logic_1164.all ; entity lfsr_bit is port ( reset : in std_logic ; clk : in std_logic ; rbit_out : out std_logic ); end entity ; architecture rtl of lfsr_bit is signal lfsr : std_logic_vector ( 3 downto 0 ); signal feedback : std_logic ; begin -- option for LFSR size 4 feedback <= not (lfsr( 3 ) xor lfsr( 2 )); sr_pr : process (clk) begin if (rising_edge(clk)) then if (reset = '1' ) then lfsr <= ( others => '0' ); else lfsr <= lfsr( 2 downto 0 ) & feedback; end if ; end if ; end process sr_pr ; rbit_out <= lfsr( 3 ); end architecture ;



The process starting at line 21 implements a shift register. The feedback input to the shift register is a linear combination of some of its own bits. Since the process sensitivity only includes the clk signal, we can know that this process uses a synchronous reset.



Also please notice that the process is labeled (sr_pr). Labeling processes helps us to better understand and maintain our code.



On the next chapter of this tutorial we will add a test bench for the pseudo random bit generator.



The source file for this Chapter is released on Github here



Chapter 2 - Adding a test bench