Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient.

Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is that at the most advanced nodes, it abstracts away the dynamic issues of power delivery that are increasingly important as semiconductor technologies scale.

“With faster switching times, the dynamic component of cell current demand is increasing relative to the static part,” said , CEO of Teklatech. “Current is demanded in a spike within a very narrow time window. The voltage drop in that time window — the dynamic voltage drop (DVD) — is a factor in calculating the delay of the cell. The timing of other switching events in the vicinity is a factor in the dynamic voltage drop in the given location and the given time window. As a result, dynamic analysis is required to get an accurate picture of DVD aware timing.”

Dynamic analysis also becomes increasingly important due to the decreasing effectiveness of decaps. As metal square resistance increases, the range of decaps, as well as the effectiveness of inherent load cap of non-switching cells, is reduced. This means that the dynamic component stands out even more. The result is a perfect storm of multiple effects from physical scaling, Bjerregaard explained.

“Dynamic analysis, and the optimization of the dynamic effects, becomes essential as local effects, both in time and floorplan location, begin to dominate. This also means that dynamic voltage drop must be taken into account at an early stage in the design process, right after placement, in order to be able to understand and mitigate its effects properly. Late stage fixing by ECOs is a costly process in terms of time and risk of non-convergence,” he said.

In other words, with static voltage drop, the workload is consistently making a demand on the power network that the network is unable to meet, so the voltage drops. This could be due to the voltage regulator being too small for the chip, or more typically, an under-designed power grid on the chip, said Peter Greenhalgh, fellow and senior director of technology at ARM.

With dynamic voltage drop, the workload is temporarily making a demand on the power network that is too rapid for the voltage regulator to react to and compensate for, so the voltage drops, Greenhalgh said. “The time frame that is typically considered for dynamic voltage drop is <100ns. This scenario is an ever-present risk in CPU implementation as a workload can rapidly transition from a full pipeline stall due to all cache levels missing, to the entire pipeline being active in a few nanoseconds when data returns from DDR.”

To avoid voltage droop, layers of local decoupling capacitance cells are required to provide sufficient power until the voltage regulator can respond. Essentially, the local decoupling capacitance is smoothing the power being delivered to the chip by the regulator.

However, it is important to remember that managing static and dynamic voltage drop are two very different problems, said Arvind Shanmugavel, senior director of application engineering at Ansys. “For static voltage drop, we have the ability to only fix the magnitude of average current or the resistance of the power grid. Changing either of these two will impact the voltage drop at the instances. Static voltage drop is typically seen as a robustness check and not a sign-off check. Managing dynamic voltage drop is not that simple. You really need to understand the clear bottleneck in the problem. This can come from several different areas. For example, a dynamic voltage drop can be due to simultaneous switching activity, missing decaps on the chip, high package impedance, high resistive paths on the chip, resonance issues due to chip-package interaction, or combinations of several different aspects mentioned.”

Indeed, fixing dynamic voltage drop is a challenge during the sign-off process. Designers need to keep in mind that dynamic voltage drop is a combination of various factors. On one hand designers need to pay attention to the chosen vector, high impedance paths from package and chip, high current regions and missing decaps. On the other hand, EDA tools also need to have the capability to clearly rank the reasons for a dynamic voltage drop to fix the real issue and avoid over design. Modeling power noise for these types of designs is very tricky. You have to understand that process technologies such as 16nm or 7nm have very different requirements. The operating noise margins have drastically decreased due to the supply voltage scaling at the same time the localized switching activity has increased, Shanmugavel explained.

Circular dependency

To further help understand the impact of power on the design and help improve the power network design and integrity, it is critical for designers to perform power analysis as early as possible at the system level or at the RTL level.

“The circular dependency between power, timing, and IR drop needs to be addressed concurrently early in the design cycle,” said Sudhakar Jilla, group director of marketing for the IC Implementation Division at Mentor, a Siemens Business. “Power savings opportunities are much more at the architecture level, and diminish as we go down to the RTL, gate and layout level. It is much easier to make architectural changes if the power is not within budget. That would tremendously help the power grid, rather than trying to make changes in the layout stage if the design is not within the power budget. That would put undue strain on the power grid.”

Fortunately, design tools have evolved to support the advanced power analysis and optimization needs at leading-edge nodes. That includes the ability to support advanced power/IR drop analysis needs, such as rush current and simultaneous switching analysis, and scalable infrastructure to support big designs. It also allows design teams to take advantage of parallelism in the tools, which is becoming necessary as the amount of computing increases, said Jilla.

A number of these improvements were added with the introduction of finFETs in order to speed up the time it takes to bring complex designs to market.

“Three or four years ago, the semiconductor manufacturing side started doing finFET structures,” said Jerry Zhao, product management director in the Digital & Signoff Group at Cadence. “With the feature sizes from 16nm now to 7nm and 5nm becoming very small, coming with that very thin structure is the idea of coloring on the mask or the design layout. Depending on the color of the layout pattern, there will be a different resistance. When the resistance is different, the IR drop is different because voltage drop is directly related to the resistance. It is proportional to that, so it tends to have larger resistance, and this tends to lead to more IR drop. At the same time, the voltage supply to the chip also is dropping, bringing additional challenges.”

PCB voltage drop

Managing both static and dynamic voltage drop is critical at the PCB level, as well.

On the static voltage drop side, Dave Kohlmeier, product line director for high speed tools in the PCB Division at Mentor, said the key is to make sure the right voltage levels are being delivered to the ICs through the package, and through the board. The problem that’s occurring is there are no longer any solid plane layers on a package or on a board—even for multi-layer boards where there are 16 or 24 layers.

This can be traced back to how the PCB is manufactured. “It’s fiberglass with layers of copper attached, and the copper gets etched away,” Kohlmeier said. “A solid plane layer is one where there is an entire layer of the PCB dedicated to supplying power to all of the ICs. Thirty years ago, when everything used to be 5V, that was relatively straightforward. You just had to make sure everything was attached correctly to that plane. Now there are so many different voltages that every system needs, in addition to the [large] pin count on the major chips. There are fewer devices that are bigger on every PCB so those pins — maybe 2,000 — those are all holes that they have to drill through the plane layer. So if you have voltage pins on that chip that are inside of that mesh, you have to make sure you can get the current through those. It has become a multi-path problem, and it has to be meshed and solved in a different way than before.”

All of those things together—multiple voltages, the number of pins and perforations in the plane layers—add up to having to have some way to solve the static voltage drop, Kohlmeier explained.

The dynamic side of voltage drop for PCBs concerns what frequency is needed to deliver the current to the ICs. “Then it’s about storage, so now we are analyzing the capacitor locations and how the capacitors are connected to the plane layers. Every little bit of connectivity of any traces or anything like that, including distance from the IC to the capacitor, limits its high frequency performance to deliver current to the device. So now they’ve got to simulate. We call this DC drop and AC decoupling analysis, because all of those decoupling capacitors are there for localized storage of charge to the ICs,” he said.

Designing to avoid problems

Avoiding problems with voltage drop is a full-flow issue. “You need to consider it from the very beginning of the design, starting from the architecture level,” said Zhao. “That’s how people talk about a low-power design methodology. After the architecture you make sure the functionality is correct and start doing the implementation. That’s where the rubber hits the road. From there, you want to look at the power delivery network—basically, the power meshes. You may have 10 power metal layers you can use for routing of the signals and routing of the power meshes. When you start at the early stage, you have to consider those things. You could have early analysis capabilities, and also some in-design capability of the IR drop analysis feature so that the implementation tool can fix ‘what ifs.’ After the implementation is done, it typically comes down to signoff — and this area is the one where IR drop and EM tools play a major role to make sure that IR drop can be signed off, and that tapeout can be completed. The tools must be very accurate, because two weeks before tapeout day you don’t have much room to wiggle and you have to run these tools. If you find problems, there must be a link to send back to the implementation tool to show where the error is, and the implementation engineers need to know how to fix the problem quickly, as well.”

Bjerregaard views techniques for managing static voltage drop as a subset of managing dynamic voltage drop. “You need to ensure that your power grid is statically strong enough, but dynamic voltage drop cannot be managed by strengthening the power grid alone,” he said. “That would mean too much overhead. Dynamic switching pattern analysis, decap placement, and clock scheduling are methods that can be used to directly address dynamic power integrity issues. In fact, as dynamic effects have started to dominate, using such optimizations will allow smaller power grids, leading to better routability, better area utilization and, in turn, higher product profitability.”

Finally, a good design methodology will result in robustness of the regulator, power grid and local decoupling capacitance, while also considering the challenge of inductance on high-frequency power network design, Greenhalgh said. “To do so requires a lot of analysis with different workloads running through an EDA tool setup that can accurately simulate the behavior of the power network over different time periods and loads.”

Put in perspective, maybe it’s time to turn the tables, focus on managing dynamic voltage drop first to create the best possible starting point, and then build a PDN with the lowest possible implementation overhead, Bjerregaard said.

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