Costs of developing a complex chip could run as high as $1.5B, while power/performance benefits are likely to decrease.

As chipmakers begin to ramp up 10nm/7nm technologies in the market, vendors are also gearing up for the development of a next-generation transistor type at 3nm.

Some have announced specific plans at 3nm, but the transition to this node is expected to be a long and bumpy one, filled with a slew of technical and cost challenges. For example, the design cost for a 3nm chip could exceed an eye-popping $1 billion. In addition, there are also several uncertainties at 3nm that could change everything overnight.

That hasn’t sidelined anyone yet, however. Samsung and GlobalFoundries separately announced plans to develop a new transistor technology called a nanosheet FET, with so-called variable widths at 3nm. Samsung, for one, hopes to deliver a PDK (version .01) by 2019, with plans to move into production by 2021. Meanwhile, TSMC is exploring nanosheet FETs and a related technology, nanowire FETs, at 3nm, but it has not announced its final plans. Intel, meanwhile, isn’t talking about its plans.

The transistor serves as a switch in chips. The finFET, today’s leading-edge transistor, is ramping up at 16nm/14nm and 10nm/7nm. Sometime around 2020, 5nm finFETs are expected to appear, but the finFET could run out of steam at 3nm unless there are some new breakthroughs.



Fig. 1: FinFET vs. planar: Source: Lam Research

That’s why the industry is exploring both nanosheet and nanowire FETs, which are considered evolutionary steps from today’s finFETs. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Both nanosheet and nanowire FETs are classified as gate-all-around technologies. They implement a gate on four sides of the structure, enabling more control of the current. In nanosheet/nanowire, a finFET is placed on its side and is then divided into separate horizontal pieces, which make up the channels. A gate wraps around the channel.

Compared to nanowires, the nanosheet FET has a wider channel, which translates into more performance and drive current in devices. That’s why nanosheets are gaining momentum in the market.

But migrating to nanosheet or nanowire FETs is not a simple matter. For one thing, the performance and scaling benefits of a gate-all-around device is debatable. “The industry needs to get a major increase in functionality as well as a small increase in transistor costs to justify the use of 3nm,” said Handel Jones, chief executive of International Business Strategies (IBS). “The problem is the definition of 3nm and (understanding) the real benefits of gate-all-around.”

Design costs are also a problem. Generally, IC design costs have jumped from $51.3 million for a 28nm planar device to $297.8 million for a 7nm chip and $542.2 million for 5nm, according to IBS. But at 3nm, IC design costs range from a staggering $500 million to $1.5 billion, according to IBS. The $1.5 billion figure involves a complex GPU at Nvidia.



Fig. 2: IC design costs escalate Source: IBS

For that reason, customers likely will stay at certain nodes longer, such as 16nm/14nm and 7nm, before even thinking about switching to 3nm. Some may never move to 3nm. And if or when gate-all-around appears, it may get pushed out beyond its target date of 2021.

Still others could move to nanosheets, but it will be a dauting task. To help the industry get ahead of the curve, Semiconductor Engineering has taken a look at gate-all-around and the manufacturing challenges.

Narrowing the options

The IC market is divided into several segments. At the leading edge, chipmakers are ramping up chips at 16nm/14nm and beyond in 300mm fabs. In those fabs, chipmakers also produce products in several segments above 16nm/14nm.

Then, there is huge demand for chips in older 200mm fabs. Not all customers require chips at leading-edge nodes. “If you were to do the cost equation, the calculation would easily tell you that it’s very challenging to get the payback because the costs of finFETs are still quite high,” said Walter Ng, vice president of business development at UMC. “It’s one thing to go to the first finFET node. It’s another thing to push beyond that. Only a few can afford it.”

Still, there are applications that require the latest processes, such as machine learning, servers and smartphones. “Certainly, those of us in software for semiconductor manufacturing definitely need more computing power. If we had 10 times as much for the same cost today, we would love that. It’s fair to say that all other scientific and engineering computing communities are in a similar situation,” said Aki Fujimura, chief executive of D2S.

At the leading edge, the industry has kept up with the demands over the years. At each node, chipmakers have scaled the transistor specs by 0.7X, enabling the industry to deliver a 15% performance boost at each turn, plus a 35% cost reduction, a 50% area gain and a 40% power reduction.

The big leap took place in 2011, when Intel moved from planar transistors to finFETs at 22nm. Foundries followed with finFETs at 16nm/14nm. FinFETs provide more performance with lower power.

But at each node, process cost and complexity are skyrocketing for finFETs, so now the cadence for a fully scaled node has extended from 18 months to 2.5 years or longer. In addition, fewer foundry customers can afford to move to advanced nodes.

Going forward, customers will likely stay at certain nodes longer due to cost. For example, 7nm finFETs provide enough power, performance and area scaling benefits for most apps. “7nm is going to be a long-lived node,” said Gary Patton, CTO of GlobalFoundries.

Still, some chipmakers plan to extend the finFET to 5nm. But at 5nm, the design costs escalate. Moreover, the scaling benefits are questionable for a 5nm finFET. “5nm is going to be one of these half nodes. It’s very similar to 10nm and 20nm in terms of performance improvement and scaling,” Patton said.

From there, the industry is working on ways to extend the finFET to 3nm. So far, it is running into roadblocks, meaning the finFET could run out of steam at 3nm. “We are spending a lot of time, and the industry is spending a lot of time, still trying to come up with the performance boosters that can get us where we need to be with the finFET on 3nm. For instance, if we would find a breakthrough in low-k spacers, that would be a big help to treat the performance of the finFET. But today, it’s not at the values where it needs to be to make the 3nm targets,” said An Steegen, executive vice president of semiconductor technology and systems at Imec. “At 3nm for us today, the finFET is starting to struggle. So at 3nm, we need to find a serious performance booster for the finFET or we would have to make a change, let’s say to a nanosheet.”

The industry recognized this some time ago. Over the years, the industry has been evaluating several next-generation transistor options, such as gate-all-around, TFETs, vertical nanowires and finFETs with III-V materials. At one time, the nanowire FET was the favorite. Nanowires are still viable, but the nanosheet is gaining steam. TFETs and vertical FETs are too difficult to make with today’s technologies.

Nanowires and nanosheets have some tradeoffs, though. “Just to put nanowires and nanosheets in perspective, a nanosheet is typically going to score higher on performance than a nanowire. It’s got a fatter channel and you’re able to drive more current there, and it will be more stable from an inversion perspective. It’s going to suffer from a density scaling perspective versus a nanowire. It’s a tradeoff,” said David Fried, vice president of computational products at Coventor, a Lam Research Company.

Of the two technologies, nanosheet FETs have some advantages. “That is the most realistic structure of gate-all-around. It will include a nanosheet with a variable nanosheet width, and more than a 90% compatible process with finFETs,” said S.D. Kwon, senior vice president of logic at Samsung.

Last year, Samsung introduced what it called a Multi Bridge Channel FET (MBCFET) at 4nm. MBCFET is basically a nanosheet FET. Recently, Samsung said it would ship the device at 3nm, not 4nm.

In addition, GlobalFoundries is developing a similar technology, with others exploring it as well. “The next node for us is something that will probably involve nanosheets,” GlobalFoundries’ Patton said. “It’s definitely more of an evolutionary step (from a finFET).”

TSMC, meanwhile, disclosed it is extending the finFET to 5nm. At 3nm, the company is exploring both nanowire and nanosheet FETs. “We are looking at both,” said Y.J. Mii, senior vice president of R&D, design and technology platform at TSMC. TSMC hasn’t publicly announced its final decision.

Clearly, the competition among foundries is heating up at 3nm. “Gate-all-around represents an opportunity for a foundry to demonstrate not just manufacturing leadership, but also technology leadership by introducing a new device architecture first,” said Klaus Schuegraf, vice president of new products & solutions at PDF Solutions. “But all of these architectural changes cost you something. They will cost you new characterization technologies. They will certainly cost you new process equipment. And that’s a lot of work.”

Plus, the manufacturing costs are enormous. “3nm will cost $4 billion to $5 billion in process development, and the fab cost for 40,000 wafers per month will be $15 billion to $20 billion,” IBS’ Jones said.

Then, even with new transistor structures, the benefits of scaling are shrinking while costs are rising. “Before 14nm, there was a 30% improvement in price/performance at each node,” said E.S. Jung, executive vice president and general manager of the foundry business in Samsung‘s Device Solutions division. “From 14nm to 10nm, there is more than 20% improvement, and at less than 10nm there is more than 20%. At 3nm, there is about 20% improvement.”

With that in mind, the question is whether the nanowire/nanosheet will provide any scaling or performance benefits over finFETs. In a recent paper, Imec described a nanosheet FET with three stacked sheets. Each sheet has a width of 20nm. The vertical pitch of the device is 12nm.

Imec’s nanosheet FET has a gate pitch of 42nm and a metal pitch of 21nm. In comparison, a 5nm finFET will likely incorporate a 48nm gate pitch with a 28nm metal pitch, according to Imec.

Based on those metrics, the nanosheet FET provides a modest scaling boost over a 5nm finFET. But the newfangled technology has some intriguing features, namely the ability to vary the width of the channels or sheets in devices. For example, a nanosheet FET with a wider sheet provides more drive current and performance. A narrow nanosheet has less drive current, but it takes up a smaller area.

“The key element is variable widths. You can control it better than the variable height of a fin,” said Dan Mocuta, director of logic integration and devices at Imec.

“In a finFET technology, the width of the device is quantized. You can have one fin, two fins, three fins or whatever. In nanosheets, you have a fixed number of nanosheets on top of each other. But you can play with the width. Now, you have access to a continuum of device widths, which you didn’t have for the finFET,” Mocuta said. “For example, you want to have an area that drives a lot of current. That could be a buffer. Then, you want to have an SRAM with a very small footprint. There are different needs on the chip that can be met.”

Nanosheets are promising, but that isn’t the only option. With a breakthrough, finFETs could extend beyond 5nm. Another option is to wait until the industry develops a better transistor. Still another way is to get the benefits of scaling by putting multiple devices in an advanced package.

Patterning nanosheets

Meanwhile, the process steps are similar between gate-all-around devices (nanosheet and nanowire FETs) and finFETs, with some exceptions. Making a gate-all-around device is challenging, however. Patterning and defect control are just some of the issues.



Fig. 4: Stacked nanosheet process sequence and TEM. Source: IBM, Samsung, GlobalFoundries.

In nanosheets and related devices, the first step differs from a finFET. The goal is to make a super-lattice structure on a substrate using an epitaxial reactor. The super-lattice consists of alternating layers of silicon-germanium (SiGe) and silicon. At a minimum, a stack would consist of three layers of SiGe and three layers of silicon.

Then, you pattern tiny sheet-like structures on the stack. For this, the industry wants extreme ultraviolet (EUV) lithography. “The question is how do you accomplish that on your wafer in patterning. In finFETs, the fins are straight and regular. And you could use self-align spacer techniques to print those,” Imec’s Steegen said. “(For nanosheets), I can print pretty much every different linewidth spacing in single-exposure EUV.”

With EUV, though, chipmakers face some reoccurring challenges. “What’s interesting about that from a patterning point of view is that we go back to having devices with variable widths,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries.

“If we go back to variable widths, as what we did in the days of planar transistors, it’s highly desirable to print those directly with EUV lithography,” Levinson said. “But now, if we go back to devices with similar patterning requirements as the old planar transistors, we are back on very aggressive line-edge roughness. There will be a need for much less LER.”

LER is defined as a deviation of a feature edge from an ideal shape. Any deviation of a feature edge can impact the performance of a transistor.

Transistor challenges

Meanwhile, after the patterning flow, the next step involves the formation of the shallow trench isolation structures, followed by the development of inner spacers.

Then, using a replacement process, the SiGe layers are removed in the super-lattice structure. This, in turn, leaves the silicon layers with a space between them. Each silicon layer forms the basis of a sheet, which are the channels in the device.

“The way you access the sacrificial materials is you look down the gate. You must have a chemistry that is able to go under and remove the sacrificial material,” Imec’s Mocuta said. “The wider the nanosheet, the harder it is to remove this material. It has to be an isotropic etch. It also has to go laterally. It has to be very selective.”

The challenge is performing an isotropic etch laterally in the source/drain region at the bottom. “That’s a problem that needs to be solved. But there are solutions,” he said.

Finally, high-k/metal-gate materials are deposited, thereby forming a gate. The gate surrounds each of the nanosheets.

For this and other steps, the industry requires new or more advanced tools. “We believe selective deposition and selective etch will be fundamental for those nodes coming in,” said Kandabara Tapily, a researcher at TEL, in a presentation at the recent IEEE International Interconnect Technology Conference (IITC). “We are looking at selective processes, not just selective deposition. Deposition is not the only way to achieve selectivity. You have to look at selective etches or combining some treatments that can be selective.”

Selective etch involves atomic layer etch (ALE). Offered by several vendors, ALE selectively removes targeted materials without damaging other parts of the structure.

The big gap is a technology called area selective deposition. With this, the goal is to deposit metal on dielectrics or dielectrics on metals. It is still in R&D.

Interconnect issues

There are other challenges, namely the interconnects. The interconnects—the tiny copper wiring schemes in chips—are becoming more compact at each node, causing an unwanted resistance-capacitance (RC) delay in chips.

To help solve these issues, Intel moved from traditional copper to cobalt materials for two of the interconnect layers at 10nm. Others are sticking with copper at 7nm.

But it’s unclear if copper can extend to 3nm. So, the industry is exploring other metals, such as cobalt and ruthenium, for the interconnects.

For this, it’s too early to say what will happen at 3nm. “Down the road, there will be additional challenges with the metallization,” said Jonathan Bakke, global product manager at Applied Materials. “The industry, as a whole, has a pretty clear roadmap to 5nm. Beyond that, there are a lot of question marks. We see sometime in the next few years that gate-all-around may happen. We don’t have that exact visibility when, but there is a lot of work out in that space.”

Process control problems

Inspection and metrology are also critical. Wafer inspection is used to find defects in chips, while metrology is the art of measuring structures.

Gate-all-around presents some challenges. “In many cases, given that the channels are buried, we will no longer be able to rely on CD-SEM measurements, even for engineering-level measurements,” said John McCormack, technical director of process control solutions at KLA-Tencor.

“Instead, enhanced optical-based CD (OCD) metrology systems and models will be required. For example, in these advanced device structures, the inner spacer is the most critical parameter in determining the gate length. As this is recessed in the sacrificial SiGe, it is not visible to top-down CD-SEMs, and thus requires advanced OCD measurements,” McCormack said. “In addition, there will be a continued increase in critical dimensions defined by multiple integrated unit-process steps, as we saw in the transition from planar to finFET devices. This seems likely to continue the trend of utilizing multiple measurement steps and types for SPC and APC control.”

For gate-all-around, chipmakers will not only require OCD, but also transmission electron microscopy, X-ray and other techniques.

To be sure, the industry can make nanosheets. It’s up for the task. But it requires huge funding. The question is whether or not it’s worth it in the long run.

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