Today we have the second generation Intel Xeon Scalable processor launch. This second generation has been codenamed “Cascade Lake” which is a nomenclature set to expire today. At STH, this is now the fifth major dual socket Intel Xeon Launch we have covered, although we were reviewing systems before then. Over the past month, we have had systems in the lab running new chips at various parts of the new Xeon SKU stack in single, dual, and quad socket configurations from multiple vendors. We are going to break out parts of our specific analysis, however, we wanted to provide our readers with an overview of what this new generation offers.

Key Points of the Second Generation Intel Xeon Scalable Family

Since this is a longer piece, we are going to summarize the launch into several key points:

More cores in the mainstream part of the SKU stack at the same price points Almost all SKUs in the stack have minor clock speed bumps and thus performance improvements accompanying the core count increases Similar clock-for-clock IPC performance as the first generation Memory speeds and capacities have increased, now to a maximum of DDR4-2933 speeds and 256GB LRDIMM support Intel Optane DC Persistent Memory Module support (DCPMM) for persistent, high-capacity, high-performance modules in DDR4 sockets New hardware security mitigations and fixes for the side channel/ speculative execution families of vulnerabilities, e.g. Spectre/ Meltdown and L1TF Intel DL Boost using the new VNNI instruction to allow faster AI inferencing without GPUs New quad CPU packaging into a half-width dual-socket Intel Xeon Platinum 9200 series to increase density for the HPC space

These key points underpin the entire launch. In this article, we are going to discuss all eight. On some of the performance aspects, Intel Optane DCPMM, and the Intel Xeon Platinum 9200 series, we already have more detailed pieces in the publishing queue, but we are going to provide some sense of what to expect in this article to discuss the impact.

Intel’s slide on their new processors looks fairly similar to what we outlined above as our key points.

In this generation, the vast majority of architecture will seem familiar to those who used the first generation parts. We are going to direct our readers to our AMD EPYC and Intel Xeon Scalable Architecture Ultimate Deep Dive for all of the basics of how Intel Xeon Scalable CPUs work, and how they compare to previous generation Xeon E5 systems and AMD EPYC.

Here is the headline slide for the new series that highlights Intel’s main points on the launch.

One can see that our outline translates into the key changes in this cycle, albeit with a bit more nuance.

Next, we are going to discuss some of the SKU stack changes. We will then move onto our CPU performance testing. That will be followed by a discussion on Intel Optane DC Persistent Memory and an example of how that can help performance. We will then discuss security hardening and Intel DL Boost. We will end with a discussion of the new Intel Xeon Platinum 9200 series followed by our final thoughts.