a, Standard cell layouts (derived using the ‘asap7sc7p5t’ standard cell library37), illustrating the importance of CNT correlation: because the length of CNTs (which can be of the order of hundreds of micrometres) is typically much longer compared with the CNFET contacted gate pitch (CGP, for example about 42–54 nm for a 7-nm node37), the number of s-CNTs and m-CNTs in CNFETs can be uncorrelated or highly correlated depending on the relative physical placement of CNFET active regions38. For many CMOS standard cell libraries at sub-10-nm nodes (for example refs 37,39), the active regions of FETs are highly aligned, resulting in highly correlated number of m-CNTs among CNFETs in library cells, further degrading VTCs (because one m-CNT can affect multiple CNFETs simultaneously). b–f, Generating a variation-aware CNFET SNM model, shown for a D-flip-flop (dff) derived from the asap7sc7p5t standard cell library37. b, Layout used to extract netlists for each logic stage. c, Schematic: CNFETs are grouped by logic stage (with nodes arbitrarily labelled ‘D’, ‘MH’, ‘MS’, ‘SH’, ‘SS’, ‘CLK’, ‘clkn’, ‘clkb’ and ‘QN’ for ease of reference). d, For each extracted netlist, there can be multiple VTCs: for each logic stage output, a logic stage input is sensitized if the output state (0 or 1) depends on the state of that input (given the states of all the other inputs). For example, for a logic stage with Boolean function: Y = !(A*B+C), C is sensitized when (A, B) = (0, 0), (0, 1) or (1, 0). We simulate all possible VTCs (over all logic stage outputs and sensitized inputs), and also in the presence of m-CNTs. For example, panel d shows a subset of the VTCs for the logic stage in panel b with output node ‘MH’ (labelled in panel c), and sensitized input ‘D’ (with labelled nodes (‘clkb’, ‘clkn’, ‘MS’) = (0, 1, 0)). The dashed line indicates VTC with no m-CNTs, and the solid lines are example VTCs in the presence of m-CNTs (including the effect of CNT correlation). In each case, we model V OH , V IH , V IL and V OL as affine functions of the number of m-CNTs (M i ) in each of r regions (M 1 , ..., M r ), with calibration parameters in the static noise margin (SNM) model matrix T (shown in panel f). e, Example calibration of the SNM model matrix T for the VTC parameters extracted in panel d; the symbols are VTC parameters extracted from circuit simulations (using Cadence Spectre), and solid lines are the calibrated model. f, Affine model form. g–j, VLSI design and analysis methodology. g, Industry-practice physical design flow to optimize energy and delay of CNFET digital VLSI circuits, including: (1) library power/timing characterization (using Cadence Liberate) across multiple V DD and using parasitics extracted from standard cell layouts (derived from the asap7sc7p5t standard cell library), in conjunction with a CNFET compact model8. (2) Synthesis (using Cadence Genus), place-and-route (using Cadence Innovus) with back-end-of-line (BEOL) wire parasitics from the ASAP7 process design kit (PDK). (3) Circuit EDP optimization: we sweep both V DD and target clock frequency (during synthesis/place-and-route) to create multiple physical designs. The one with best EDP is used to compare design options (for example, DREAM versus baseline). h, Subset of logic gates in an example circuit module, showing the effect of CNT correlation at the circuit level (for example, the m-CNT counts of CNFETs P3,1 and P5,1 are both equal to M 1 + M 2 + M 3 )40. i, Distribution of SNM over all connected logic stage pairs, for a single sample of the circuit m-CNT counts. The minimum SNM for each trial limits the probability that all noise margin constraints in the circuit are satisfied (p NMS ). j, Cumulative distribution of minimum SNM over 10,000 Monte Carlo trials, shown for multiple target p S values, where p S is the probability that a given CNT is a semiconducting CNT. These results are used to find p NMS versus p S for a target SNM requirement (SNM R ), where p NMS is the fraction of trials that meet the SNM requirement for all logic stage pairs. We note that p NMS can then be exponentiated to adjust for various circuit sizes based on the number of logic gates. k, CNFET compact model parameters (for example, 7-nm node).