Ferroelectric FETs and memories are beginning to show promise as researchers begin developing and testing next-generation transistors.

One measure of the efficiency of a transistor is the subthreshold swing, which is the change in gate voltage needed to increase the drain current by one order of magnitude. Measured in units of millivolts per decade, in conventional MOSFETs it is limited to kT/q by the Boltzmann electron energy distribution. That’s about 60 mV/decade at room temperature.

As devices have scaled down, this limit has become more onerous. If supply voltage is constant, a higher and higher charge density is needed to produce the same amount of current.

Device designers have two options to reduce subthreshold swing (SS). They can use a different switching mechanism with different physics, such as a tunnel FET, or they can find a way to increase the gate capacitance without increasing the gate voltage. This latter option is motivating interest in ferroelectric transistors (FeFETs), which place a ferroelectric capacitor in series with a conventional dielectric gate capacitor.

Ferroelectric materials first came to the industry’s attention as potential non-volatile memory elements. A ferroelectric material has a built-in electronic dipole moment. (They are named by analogy with ferromagnetic materials, as ferroelectrics generally do not contain iron.) Applying a sufficiently strong electric field reverses the polarization of the material, and the polarization persists even after the electric field is removed. The decay rate of the polarization — the hysteresis of the material — creates a “memory window” that allows the ferroelectric capacitor to store a previous charge state. FeRAM devices are based on this behavior.



Fig. 1: Ferroelectric polarization as a function of electric field. Source: Wikimedia

Explaining negative capacitance

In both the positive and negative polarization states, a ferroelectric capacitor behaves as a conventional capacitor, with positive capacitance εA/d. (A is the area of the plates, d is the separation between them, and ε is the permittivity of the dielectric.)

As Anne Verhulst, principal scientist at Imec, explained in work presented at the recent IEEE Electron Device Meeting (IEDM), switching the polarization causes a transient decrease in charge at the ferroelectric (MFM) capacitor. If the MFM capacitor is connected in series with a transistor’s gate (MIS) capacitor, this transient produces an increase in charge at the gate. The so-called “negative capacitance” effect can produce a sub-60 mV/decade subthreshold swing over at least part of the transistor’s voltage-current curve. The discovery of ferroelectric behavior in HfO 2 in 2011 made FeFETs a CMOS-compatible potential solution to one of the industry’s most challenging scaling issues.

Well, maybe. The hysteresis that is so helpful in FeRAM devices contributes to switching delay in FeFETs. It is not yet clear whether hysteresis-free devices will still demonstrate a negative capacitance effect, particularly at the high switching speeds required for leading edge circuits. There is ongoing debate about the extent to which the negative capacitance effect is a fundamental feature of the FeFET structure, an unreliable artifact of charge trapping, or both. At IEDM, a few points of agreement began to emerge.

Optimizing FeFETs

The consensus FeFET (or NCFET) structure appears to be a hafnium-zirconium oxide (HZO) capacitor with TaN electrodes, placed on top of an HfO 2 gate oxide. (SiO 2 oxides are used in some experimental studies.) Chengji Jin and colleagues at the University of Tokyo found that increasing the zirconium content increases capacitance and ultimately can result in anti-ferroelectric behavior, with the hysteresis loop moving clockwise rather than counterclockwise. Most proposed devices have roughly equal amounts of hafnium and zirconium.

Shinji Migita (AIST, Ibaraki, Japan) pointed out that substantially more charge can be stored in the MFM capacitor than in the MIS capacitor. His group’s devices used 10 nm thick Hf 0.5 Zr 0.5 O 2 , with a maximum charge density of 30 μC/cm2, combined with 3.8 nm thick SiO 2 , which has a maximum charge density of 2.7 μC/cm2. Injecting too much charge into the gate capacitor is unhelpful at best, and at worst can lead to dielectric breakdown.

Best results are thus achieved by matching the capacitances of the two devices. While most studies do this by adjusting the area of the top (MFM) capacitor, an optimized production process could treat the thicknesses and areas of both capacitors as tunable parameters. Several groups demonstrated hysteresis-free steep SS performance in area-matched FeFET devices.

The next important challenge is posed by the kinetics of ferroelectric polarization. Switching the polarization of the ferroelectric capacitor requires finite time.

Individual grains in the ferroelectric layer are binary — they are polarized either positively or negatively at any particular moment. Yen-Kai Lin and colleagues at UC Berkeley ran a simulation in which the ferroelectric was polycrystalline, with some distribution of grain sizes and switching fields. Reducing the switching field and increasing the pulse rate — both of which are desirable in commercial devices — can result in non-uniform ferroelectric behavior and inconsistent current flow.

Poor interface and crystalline quality can introduce charge traps, offsetting the ferroelectric behavior to some degree.

Beyond the roadmap: negative capacitance and emerging devices

Though much of the interest in negative capacitance transistors has been directed toward relatively near-term planar MOSFET and finFET structures, some researchers have also applied the concept to emerging devices. At Imec, single crystalline PZT capacitors, placed in series with the gate of an InGaAs TFET, produced an SS value as low as 40 mV/decade. Researchers at National Taiwan Normal University achieved an even lower SS, averaging 22 mV/decade in highly scaled gate-all-around nanosheet FETs with an HZO gate. Finally, a group at Hong Kong Polytechnic University used an HZO/Al 2 O 3 stack as the gate for two-dimensional WSe 2 transistors, achieving a minimum 18.2 mV/decade SS.

Taken as a group, these results suggest that ferroelectric capacitors may offer a universal performance boost for any of the proposed post-MOSFET structures.