Overview

The DNK7_F5PCIe is a Xilinx Kintex-7 based FPGA board optimized for algorithmic acceleration applications requiring FPGAs with high-performance local memory. Data movement to/from the FPGA grid is accomplished via a fixed 4-lane, GEN1/GEN2 PCIe bridge. Each Kintex-7 FPGA (FPGAs 1-4 in the block diagram) has five separate 256M x 16 DDR3 (4 Gb) memories. The Dataflow Manager FPGA (FPGA 0 in the block diagram) has six 256M x 16 DDR3 memories.

Dedicated PCIe, 4-lane controller (GEN1 or GEN2)

We ship the DNK7_F5PCIe with a fixed, full function, 4-lane master/target PCIe controller. The PCI controller has two mastering DMA engines, 2 for transmit (board -> host) and 2 for receive (host -> board). Drivers with 'C' source for several operating systems are included at no cost.

Kintex-7 FPGAs from Xilinx - Performance and Low Power

The Xilinx Kintex-7, 28 nm FPGAs are utilized. We use the second largest member of this cost effective (read: CHEAP) family. The Kintex-7 FPGA family has an impressive price/performance ratio for hardware-in-the-loop accelerators with excellent device power consumption properties. Operation frequency is approximately twice that of the previous low cost Xilinx FPGAs - Spartan-6.

Features of Kintex-7 include efficient, dual-register 6-input look-up table (LUT) logic, 36 Kb block RAMs, and second generation DSP slices which contain 25 x 18 multipliers along with a 48-bit accumulator.

We use the second largest device from this family, the 7K325T, in the FFG900 and FFG676 packages. 100% of the FPGA resources are dedicated to your application. All FPGAs, excluding the PCIe controller, are configured via PCIe. The PCIe FPGA can be updated in the field.

Memory - DDR3

The availability of large amounts of local high speed memory is pivotal to FPGA-based algorithmic acceleration applications. The DNK7_F5PCIe is optimized accordingly. Each of the four field FPGAs (FPGAs 1 thru 4) has a total of five, 4 Gb DDR3 memories. Each memory is 256M x16 with separate data, address and control. Three of these DDR3 memories are connected to FPGA pins capable of 800 MHz (1600 Mb/s per data pin) and remaining two are connected to FPGA pins capable of 400 MHz (800 Mb/s per data pin). The Xilinx Memory Interface Generator (MIG) works fine. The five memories can be used independently or grouped in any manner that best fits your application. The Dataflow Manager FPGA (FPGA 0) has a total of six, 4 Gb DDR3 memories. Three of these memories are connected to FPGA pins capable of 800 MHz (1600 Mb/s per data pin) and three are connected to FPGA pins capable of 400 MHz (800 Mb/s per data pin).

As always, we provide examples and reference designs to help you with all of your memory interface issues. Please check with us to make sure that what we ship for no charge meets your requirements.

Power Consumption

The PCI Express specification limits slot power to 25 watts. The DNK7_F5PCIe is capable of consuming power significantly beyond that. In addition to the PCIe fingers, a separate connector adds a second path for power. This product is shipped with adequate heat sinks to cool the chips, but airflow is required in the chassis to dissipate the heat. Contact the factory if you require high reliability, no-fan heatsinks.

Although no specific testing was performed, sophisticated statistical finite element models and back of the envelope calculations are showing the number of status LEDs to be bright enough to work as a flashlight. Contact the factory for more information about this sophisticated feature and make sure an adult is present during operation. These LEDs are user controllable from the FPGAs so can be used as visual feedback in addition to emergency lighting. A JTAG connector provides an interface to ChipScope and other third party debug tools.

Specs of FPGAs Available on the DNK7_F5PCIe