Ruthenium interconnects

Imec has developed a process to enable ruthenium (Ru) interconnects in chips at 5nm and beyond.

Ru is one of several candidates to replace traditional copper as the interconnect material in chips. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. The interconnects are becoming more compact at each node, causing an unwanted resistance-capacitance (RC) delay in chips.

As a result, the industry is looking for possible replacements for copper. Cobalt and ruthenium are potential candidates.

At the recent IITC conference in San Jose, Calif., Imec described a process that could enable Ru interconnects. In the lab, the R&D organization fabricated single-level Ru interconnects in a 300mm pilot line. The technology makes use of EUV lithography and a new subtractive etch process.

The process would replace today’s dual-damascene scheme for copper interconnects. “A semi-damascene integration approach is one proposed solution for multilevel Ru interconnect,” said Danny Wan, a researcher at Imec and lead author of the paper. “This method begins with a via formed in low-k first, followed by filling of both the via and the trench layers with a single deposition step. Key advantages are that the process can be barrier-less, grain size can be tuned, and there is no requirement for metal CMP. The trench layer is then patterned using subtractive etch, which eliminates the need for plasma processing of low-k trenches.”

The subtractive etch approach can also be used for other materials. “Not limited to logic, subtractive metal etch has strong downscaling potential and is also considered for advanced memory applications,” Wan said.

With the technology, Ru lines were formed at CDs smaller than 10.5nm. “Using the TCR method, structures with resistivity of 15μΩ.cm and cross-sectional area of 200nm2 were obtained and benchmarked against analogous Ru and Cu (copper) damascene processes,” he said. “Ru lines with aspect ratio up to 3.8 were fabricated and measured having line resistance below 500Ω/μm at 12nm CD.”

How does Ru compare with copper at sub-5nm nodes? “Ru is expected to outperform damascene Cu at this scale, supporting the potential insertion of Ru metal patterning for advanced technology nodes,” he added.

Photonic contacts

In a separate paper at IITC, Leti and STMicroelectronic have developed CMOS-compatible contacts for silicon photonics.

In silicon photonics, the contacts used to pump the III-V lasers are often composed of an Au/Pt/Ti (gold/platinum/titanium) stack. “As a consequence, these contacts are not compatible with a Si-based environment both in terms of integration and of metal used (Pt, Au),” according to the paper.

Instead of the traditional stack, Leti and STMicroelectronics developed CMOS-compatible contacts on n-InP (indium phosphide) and p-InGaAs (indium gallium arsenide) for silicon photonics.

Using the technology, the ﬁrst lasers fabricated with this new platform are operating at 1310nm with a threshold current around 60mA, a Side Mode Suppression Ratio (SMSR) larger than 45dB and more than 1.5mW optical power in the output silicon waveguide.

Ti and nickel (Ni) are promising metals. “In this paper, various Ti- and Ni-based alloyed metallizations and related elaboration using an innovative integration scheme developed for the III-V/Si heterogeneous devices are investigated for the purpose of forming low-resistivity and Si CMOS-compatible contacts to n-InP and p-InGaAs,” according to the paper. “Recently, Ni and Ni2P (nickel phosphide) metallizations have been successfully integrated on a 200 mm CMOS-compatible hybrid III-V/Si laser.”

GaN wires

Meanwhile, also at IITC, Panasonic described a new interconnect process for gallium nitride (GaN) devices.

The process enables aluminum (Al) interconnects, which replaces the traditional gold material for GaN FETs. By using Al, resistance is decreased, while electromigration lifetime is improved.

Based on gallium and nitride, GaN is a III-V, wide-bandgap technology, meaning that it is faster and provides higher breakdown voltages than traditional silicon-based devices. GaN is widely used in the production of LEDs. In addition, it is gaining steam in the radio-frequency (RF) market. And the GaN-based power semiconductor market is taking off.

The problem is that, in general, silicon-based power semis provide enough performance for many applications and are still cheaper than GaN. In addition, GaN-based power semis are produced using a GaN-on-silicon process, which is a relativity expensive and complex technology.

“Conventionally, Au-based metal stacks have been used for interconnects of power devices. But, Au is very expensive material, unfortunately. In addition, Au cannot be patterned by dry etching, which prevents cost down by chip shrinkage,” said Takeshi Harada, a researcher from Panasonic and lead author of the paper.

In response, Panasonic devised an Al-based metal stack as a gate metal for GaN FETs. Researchers discovered that Al grows epitaxially on p-GaN, forming a single crystal. This in turn helps enable to form the interconnect structure.

To make a GaN FET, an AlGaN/GaN heterojunction is grown using MOCVD on a silicon substrate. “Then recesses penetrating the AlGaN were formed by dry etching to control Vt. Next, AlGaN and p-GaN were grown epitaxially by MOCVD and the p-GaN was patterned by dry etching. After that, SiN was deposited as an ILD and trench openings were formed in the SiN to expose the surface of the p-GaN. This step was carefully designed to avoid physical/chemical damages to the p-GaN,” Harada said.

In the interconnect, the Al is sandwiched between two Ti layers. The interconnect is contacted to the p-GaN. “Finally, a metal stack was deposited by PVD and patterned by dry etching so that the gate metal which contacted to the p-GaN was formed. Two types of metal stacks were tried in this work. One was a Ti/Al/Ti stack and the other was a Ti/Al stack. The thickness of Al was 200nm to 450nm,” Harada said.