



Samsung today said it has developed the industry's first 12-layer 3D-TSV (Through Silicon Via) chip packaging technology, calling it "one of the most challenging packaging technologies for mass production of high performance chips." And that is precisely what it will be used for—it will enable Samsung to mass produce 24GB high bandwidth memory (HBM) sooner than later.





What makes this chip packaging technology so challenging is the pinpoint accuracy it requires in order to vertically attach a dozen DRAM chips in a tiny three-dimensional configuration. These configurations consist of 60,000 TSV holes, each of which is just one-twentieth the width of a single strand of human hair.













"The thickness of the package (720㎛) remains the same as current 8-layer high bandwidth memory-2 (HBM2) products, which is a substantial advancement in component design. This will help customers release next-generation, high-capacity products with higher performance capacity without having to change their system configuration designs," Samsung says.





Samsung also touts its 3D-TSV packaging technology as being crucial is continuing to push the limits as Moore's Law scaling "reaches its limits."





It remains to be seen where this will ultimately come into play. High bandwidth memory has seen a sort of lukewarm reception in the consumer space— AMD has used it with some of its GPUs (such as the Radeon VII ), but the bang-for-buck factor has not been attractive, for the most part. Meanwhile, AMD's latest generation Navi GPUs use less expensive GDDR6 memory.





Still, this development will lead to higher capacities, which could be intriguing in the data center and among professional graphics card offerings.