In my various experiments with the Raspberry Pi, I’ve hit a limitation: the number of unused general-purpose I/O ports available. Quite a few pins are usable on the 40-pin header, but sometimes it just isn’t enough.

One solution to this problem is implementing a shift register. Only two GPIO outputs are needed, one for clock and one for data — the data is shifted in serially, and any number of outputs can be read in parallel, depending on the size of the shift register.

In this article I’ll build a 4-bit shift register from first principles. Ideally we could use a shift register on a chip such as the 7400 series 74HC595:

with 8-bits in this reasonably small package. However I didn’t have any of these shift register ICs on hand, all I had was logic gate ICs. Fortunately, this is all we really need to build a functional shift register.

Latches from NANDs

It all starts with NAND gates, cross-coupled into an /S/R NAND latch:

This is the building block for a gated D latch:

There are four NAND gates in 74HC00 (Quad 2-input NAND gate), so the gated D latch can be constructed with only one 74HC00 chip:

I soldered up four D latches:

Tested each individually using a multimeter, read the output signal (Q) voltage, latched in with the data input (D) when the enable input (E) was high.

But four latches isn’t enough. Added two more, for eight total:

This is a good start, but latches by themselves are insufficient to build a shift register. Clocking is needed:

Flip-flops from latches

Latches can be upgraded to flip-flops, a clocked circuit, by combining two together with an inverted enable. Two D latches plus an inverter create the master-slave falling-edge-triggered flip-flop:

For the inverter, we can use another 74HC00 chip (quad NAND gates), tying together the two inputs of the NANDs to create four NOT gates. Here’s the first master-slave falling-edge-triggered flip-flop I soldered up, with the inverter on the bottom:

Wiring up all of the remaining gates takes a while and gets messy, but when completed, we can store 4 bits in the total of four master-slave flip-flops, each with their own data input (D), clock (C), and data output (Q) lines: