Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?

After introducing new 22nm processes over the last year or two, foundries are gearing up the technology for production—and preparing for a showdown.

GlobalFoundries, Intel, TSMC and UMC are developing and/or expanding their efforts at 22nm amid signs this node could generate substantial business for applications like automotive, IoT and wireless. But foundry customers face some tough choices because not all 22nm processes are alike. In addition, not all of them have a full complement of EDA tools or IP.

Nonetheless, foundry vendors are pushing 22nm for a number of reasons. First, the foundry business faces a slowdown and overcapacity at 28nm after years of growth at this node. So vendors see 22nm as a way to generate new revenue.

In addition, 22nm fills a gap for foundry customers. Many customers at 28nm and above are mulling the idea of moving to 16nm/14nm and beyond. But at those nodes, the options are limited to finFET transistors, which are more expensive than traditional planar transistors.



Fig. 1: FinFET vs. planar: Source: Lam Research

So for foundry customers at 28nm and above, 22nm is a compelling option. It provides better performance than 28nm, but it’s less expensive than finFETs at 16nm/14nm and beyond.

But choosing one 22nm technology from a given foundry may be far different than 22nm at a different foundry. There are three different versions of 22nm being rolled out by different foundries:

TSMC and UMC are developing a 22nm planar bulk CMOS process.

GlobalFoundries is gearing up a 22nm planar FD-SOI technology.

Intel is pushing a low-power 22nm finFET technology.

And if that’s not enough, Samsung is developing an 18nm planar FD-SOI technology. Whether it’s 22nm or 18nm, foundries are targeting the same customers, meaning the competition among foundries is expected to heat up.

“Is 22nm going to be the next popular node? My assessment is yes,” said Kelvin Low, a foundry veteran and vice president of marketing for Arm’s Physical Design Group. “I don’t believe that one camp will win or the other camp will win. Several camps will win, because the design considerations are so different.”

Of course, 22nm and 18nm aren’t suitable for everyone or all apps. As before, chipmakers can may choose stay at 28nm and above, or skip 22nm and 18nm and move to 16nm/14nm and beyond. This decision is based on the application, as well as traditional metrics such as power, performance, area scaling, delivery schedules and cost.

To help the industry get ahead of the curve, Semiconductor Engineering has taken a look at 22nm and the vendor base.

Bulk CMOS

Today, some see 22nm as a standalone market, while others view 22nm as a subset of 28nm.

International Business Strategies (IBS), a research firm, lumps four nodes—28nm, 22nm, 20nm and 18nm—into the same general category. In total, this market, which includes all process types, is projected to reach $11.5 billion in 2018, down 2.8% over 2017, according to IBS, which expects the 22nm market to grow just 0.6% in 2019. The real growth at this node is expected to occur after that.

At this point, 28nm is the largest chunk in this category. In 2017, the 28nm foundry process market alone was a $10 billion business, according to IBS. For 2018, though, 28nm is flat and beset with overcapacity. Some, but not all, 28nm customers are migrating to advanced nodes. And China is building up more 28nm fab capacity, thereby contributing to the market woes.

On top of that, 22nm is beginning to cannibalize 28nm. “22nm is 10% of the 28nm foundry market in 2018,” said Handel Jones, chief executive of IBS. “We think 22nm will be a big node over time.”

Of the three main flavors of 22nm—planar bulk CMOS, FD-SOI, and finFETs—bulk CMOS is the best known because it has been the mainstay of the chip industry for years. CMOS is used in both planar and finFET transistors, while FD-SOI uses a specialized silicon-on-insulator wafer that incorporates a thin insulating layer in the substrate.

Each technology has its own benefits and drawbacks. Bulk CMOS is the least expensive, but 2D CMOS transistors are prone to static leakage, which is one of the key reasons for the introduction of finFETs. Controlling that leakage allows chipmakers to increase the clock frequency, but speed has to be balanced against dynamic power density. FD-SOI, meanwhile, accomplishes the same thing using a planar structure, while adding the option of body biasing to control the power. The downside is it ithat both finFETs and FD-SOI are more costly than CMOS.

All of these 22nm options are aimed at winning new business without the need for multi-patterning, which is time-consuming and expensive. This is why the 28nm node, which was introduced in 2011, has become the sweet spot for many advanced IC designs. It balances performance and cost for applications.

The average design cost for a 28nm planar device is $51.3 million, compared to about $106.3 million for a 16/14nm chip, according to IBS. So while GlobalFoundries, TSMC, UMC and others offer 16/14nm finFETs, the majority of designs are still coming in at older nodes.

“When you go to finFETs, you have a big jump in mask and design costs,” IBS’ Jones said. “FinFETs are good for digital, but you can’t really do RF. And mixed-signal is a challenge.”

FinFETs are ideal for high-performance applications, but the technology is limited in other ways. It is difficult to integrate RF and scale analog. So to fill the gap, several foundry vendors some time ago began to develop 22nm. 22nm provides an option for customers who want more performance than 28nm, but don’t require or can’t afford 16nm/14nm and beyond.

22nm is ideal for IoT, mixed-signal and RF. It is less expensive than 16nm/14nm as the average IC design cost for a 22nm device is $70.3 million, according to IBS.

“We anticipate 22nm will have a long life-cycle with reasonable volume,” said John Chen, director of corporate marketing at UMC. “Instead of migrating straight from 28nm to 14nm finFETs, customers will have an attractive ultra-low leakage process option to migrate from their existing 28nm designs. (22nm) benefits from lower mask and design-in costs than 14nm.”

22nm also offers a relatively painless upgrade path to chipmakers with designs at 65nm, 55nm and 40nm, which is where a lot of cost-sensitive designs are being done. “When that group of products migrates to the next node, it will present a big wave at 22nm,” Arm’s Low said. “It’s going to happen when the cost is right. It’s also IP availability. Once those two align, that’s when the market will take off.”

Of the multiple 22nm options, planar bulk CMOS, which is being developed by TSMC and UMC, is basically a scaled-down version of today’s 28nm bulk planar CMOS technology. Like 28nm, it incorporates high-k/metal-gate, copper interconnects and low-k dielectrics.

This approach has some pros and cons. On the plus side, it’s an extension of 28nm and chipmakers can use the same equipment and process flows. On the negative side, bulk technology suffers from unwanted short-channel effects as it approaches 20nm. This, in turn, degrades the sub-threshold slope, or turn-off characteristics, in a device.

Then, in conventional transistors, the channel region below the gate is depleted of mobile charges, leaving the dopant atoms ionized. “The charge from those atoms, along with the gate work function, sets the threshold voltage. The depth of the depletion region controls the electrostatics. Below the depletion region is neutral silicon with a lot of mobile carriers,” explained Terry Hook, a semiconductor expert and a former technical staff member at IBM.

But as the technology is pushed, bulk CMOS transistors are prone to a phenomenon called random dopant fluctuation. In simple terms, this causes variations of the dopant atoms in the channel. As a result, a bulk CMOS transistor may perform differently from its nominal behavior, and can also produce random differences in terms of threshold voltages.

“Bulk planar technologies are limited by a large random dopant fluctuation, which dominates the mismatch and variation of transistors at advanced nodes,” said Jamie Schaeffer, senior director of product line management at GlobalFoundries, in a recent video.

One way to solve the problem is to move to a fully depleted transistor type like FD-SOI and finFETs. “In finFETs and FD-SOI, the channel dopant is minimized and you get a one-time benefit in matching,” said chip expert Hook.

Still, two foundry vendors—TSMC and UMC— plan to push the limits of bulk CMOS with a 22nm version of the technology. And despite the challenges, 22nm bulk is gaining some traction.

“My understanding is that some customers are taking advantages of the density/speed/power by moving from 28nm to 22nm. TSMC expects about 20% of 28nm/22nm customers will choose 22nm,” said Samuel Wang, an analyst at Gartner. “FD-SOI is for low-power niche applications. 22nm bulk is the shrunk version of the popular 28nm. Most designers are used to this design method and it has more widely available physical IP.”

TSMC, meanwhile, recently revealed more details about its previously-announced 22nm technology, which involves two process platforms. The first technology, 22nm ultra-low power (ULP), is geared for low-power applications that require more performance. The second, 22nm ultra-low leakage (ULL), is targeted for ultra-low power devices.

“For IoT and RF/analog applications, the applications space is wide,” said Cliff Hou, vice president of R&D at TSMC. “It’s difficult for one technology to cover both applications. So that’s why we need to optimize them separately.”

22nm ULP has an operating voltage from 0.8 to 0.9 volts. TSMC revealed a new spec for 22nm ULL, which is 0.6-volt. That version is due out April 2019.

Besides the technical specs, foundry customers also must examine the EDA tool and IP support for a process. This gets tricky because some foundries offer more EDA/IP support than others at 22nm.

Foundries rely on third-party EDA tools. Then, for a given process, foundries develop some of their own IP, but they also rely on third-party IP. There is a long list of EDA vendors and IP technologies. But in one major IP development, 22nm marks TSMC’s entry into the embedded MRAM and resistive RAM space.

Embedded memory is integrated in a microcontroller (MCU). MCUs use NOR flash for embedded memory applications, such as code storage.

NOR, however, is difficult to scale beyond 28nm, prompting the need for a next-generation memory technology like MRAM and RRAM. The new memory types combine the speed of SRAM and the non-volatility of flash with unlimited endurance.

Still, Microchip plans to extend its embedded flash technology, called SuperFlash, down to 22nm. “We plan to support FD-SOI and/or 22 nm technologies in general once 28nm technology is qualified,” said Vipin Tiwari, director of marketing at Silicon Storage Technology (SST), a subsidiary of Microchip. “Because 22nm is a shrunk node of 28nm, it is very likely that SuperFlash technology will be needed on those nodes. The eMRAM and SuperFlash technology can coexist depending on the end application.”

Then, on another third-party IP front, Arm has developed physical IP for TSMC’s 22nm process, such as standard cell libraries, general-purpose I/Os, and memory compilers.

On the EDA side, large EDA vendors support TSMC’s 22nm technology. “Enablement for 22nm varies by foundry with some subtle differences in how they are doing lithography and how much DFM enablement they offer,” said Michael White, director of product marketing at Mentor, a Siemens business. “It is important to note that as this is a new node variant, there are always time lags/quality differences between the golden sign-off and following tools. A fabless customer will want to use the industry golden or run higher risks in issues at tape out.”

UMC also is developing a 22nm bulk CMOS process. “UMC is now finalizing customer specifications for our 22nm process, and we expect to ramp to production in 2020,” UMC’s Chen said. “This technology node features performance and power optimization, approximately 10% area scaling compared to 28nm, ultra-low power and RF/mmWave advantages. UMC’s 22nm platform will be a cost-effective solution to serve a wide range of applications for planar high-k/metal-gate technology, including mobile (5G and other wireless), IoT and automotive sectors.”

FD-SOI

GlobalFoundries was the first player to enter the 22nm race. Three years ago the company introduced a 22nm FD-SOI technology. For some time, Samsung has offered 28nm FD-SOI with an 18nm version in the works.

In addition, GlobalFoundries is developing a 12nm planar version of FD-SOI, which is expected to appear in 2022. Generally, 22nm or 18nm FD-SOI doesn’t compete with 16nm/14nm finFETs, and they serve different markets with little overlap.

FD-SOI uses a specialized SOI wafer, which integrates a thin insulating layer (20 to 25nm thick) in the substrate. This layer isolates the transistor from the substrate, thereby blocking the leakage in the device.

FD-SOI also is based on a planar, fully depleted architecture. “This essentially eliminates the random dopant fluctuation, providing superior mismatch and electrostatics to improve sub-threshold slope,” GlobalFoundries’ Schaeffer said.

GlobalFoundries’ 22nm FD-SOI technology, called 22FDX, incorporates high-k/metal-gate with silicon-germanium in the channel. It provides 30% higher performance and 45% lower power compared to 28nm. It was production-qualified in early 2017.

Recently, GlobalFoundries added more capabilities to the mix. “Sub-6GHz RF, mmWave, ultra-low leakage and ultra-low power extensions have all been qualified,” Schaeffer said.

What makes FD-SOI attractive are two features—low-power and body bias. It enables drive currents of 910μA/μm (856μA/μm) at 0.8 volts, with voltage operations down to 0.4 volts.

“Body bias is the ability to fully control the threshold voltage (V th ) of the transistors dynamically by polarizing the back gate of the transistor. V th —which was a parameter determinable only by process through complex doping techniques—is now programmable dynamically through software,” said Manuel Sellier, product marketing manager at Soitec. “Designers can use this feature to dynamically manage the leakage in their circuit, and also to compensate static (process) and dynamic variations (temperature, voltage, and aging) efficiently. The result is a 4X to 7X energy efficiency gain at ultra-low power.”

FD-SOI also supports forward body biasing. When polarization of the substrate is positive, the transistor can be switched faster, according to STMicroelectronics.

FD-SOI, however, has three drawbacks—cost, ecosystem and adoption. For years, FD-SOI has had limited adoption. Intel, TSMC, UMC and others have never adopted FD-SOI, saying bulk CMOS enables high-performance devices at better costs. For example, an SOI wafer sells from $370 to $400 each, compared to $100 to $120 for a bulk CMOS wafer.

But FD-SOI does have a lower mask count, which compensates for the wafer cost. FD-SOI has 22 to 24 mask steps, while a comparable bulk CMOS process has 27 to 29 mask steps, according to IBS.

FD-SOI is closing the gap, too. “We are now looking at what we view as the limit of bulk CMOS,” IBS’ Jones said. “Transistor costs for 22nm FD-SOI are within 5% of the transistor costs for 22nm HKMG (high-k/metal-gate). 22nm FD SOI gives 30% to 50% lower power consumption compared to 22nm HKMG, which is important for wearable and IoT devices.”

The FD-SOI community, however, lags in terms of the EDA/IP ecosystem. “The IP ecosystem for 22nm FD-SOI is strengthening, but 22nm HKMG bulk CMOS has a broader IP ecosystem,” Jones said.

The tide is turning. Cadence, Mentor and Synopsys have been certified for various EDA tools for GlobalFoundries’ FD-SOI technology.

“There are some unique capabilities for RF, for example, with integrated FD-SOI, which are very hard to equal in other ways,” said Wally Rhines, president and CEO of Mentor.

FD-SOI has other advantages. “While the finFET gives you near zero leakage, you still have dynamic power. One of the advantages of FD-SOI is dynamic power. If you can reduce the voltage from one volt down to 0.6, that’s a 65% reduction in power. FD-SOI has some advantages in being able to dynamically alter the power versus the performance balance,” Rhines said.

Other options

Last year, Intel introduced a low-power version of its 22nm finFET technology. Since then, Intel has been rather quiet about the offering. At the upcoming IEDM event, though, Intel plans to present a paper on embedded MRAM technology for 22nm.

There is a lot of activity around 22nm, but it’s not clear yet how big the market will become or which technology will prevail. It’s too soon to say if 22nm will become a smash hit or a niche. Each technology has its place, but some will likely gain more traction than others.

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