SK Hynix is due to present a paper outlining the technology at the International Electron Devices Meeting (IEDM) that takes place December 1 to 5 in San Francisco, California.

The company will report on a 3D crosspoint memory cell for use in storage-class memory (SCM) that is built from phase-change materials integrated with a chalcogenide selector device.

The abstract of the paper describes the phase-change material as new but it is not clear whether the company will reveal the precise formulation which may be just one of the wide variety of germanium-antimony-tellurium (GeSbTe or GST) ternary alloys that it is possible to make.

SK Hynix has fabricated cells with a two-deck architecture at between 20 and 29nm node density with a read latency of less than 100ns in a 16Mbit test array. The authors claim that the memory suitable for use in a 128Gbit device. This is the device format, component capacity and approximate node at which Intel and Micron introduced 3D XPoint memory in July 2015.

At the time Intel and Micron companies were coy about the materials they were using and described the technology at the time as a form of bulk-switching resistive RAM. However, it is widely thought to be based on chalcogenide phase change material (see Is 3D XPoint based on phase-change memory?), which the two companies have not denied.

It took a couple of years for Intel to bring out solid-state drives based on 3D XPoint (see Intel launches SSD based on 3D XPoint memory) and Intel and Micron have this year announced the end of their collaboration (see Intel, Micron end collaboration on 3D XPoint NVM).

The paper #37.1 is titled 'High-Performance, Cost-Effective 2z nm Two-Deck Crosspoint Memory Integrated by Self-Align Scheme for 128 Gb SCM,' and authored by T. Kim et al., SK Hynix.

Related links and articles:

www.ieee-iedm.org

www.skhynix.com

News articles:

Is 3D XPoint based on phase-change memory?

Intel launches SSD based on 3D XPoint memory

Intel, Micron end collaboration on 3D XPoint NVM

IEDM: Intel embeds MRAM in FinFET process