SiFive unveiled a RISC-V based “U8-Series” Core IP that is roughly equivalent to Arm’s Cortex-A72. The power-efficient, up to 2.6GHz U84 and higher-end U87 both offer a superscalar out-of-order pipeline and support heterogeneous SoC designs.



RISC-V market leader SiFive has announced a U8-Series core IP based on the open source RISC-V architecture that it claims is the “highest performance RISC-V ISA based Core IP available today.” The IP design features a superscalar out-of-order (OoO) pipeline with configurable pipeline depth and issue queue width. The U8-Series targets “performance- and latency-sensitive” applications in automotive, datacenter attach, and edge or end-point deep learning SoCs.

SiFive also announced a SiFive Shield technology for its RISC-V processors, which is similar to Arm’s TrustZone (see farther below).

SiFive is offering “lead access” to IP for an initial U84 core optimized for power efficiency and area efficiency. This will be followed by a SiFive U87 core that adds vector processing support. The U84 standard core offers twice the area efficiency and 1.5x better performance per Watt compared to Arm’s Cortex-A72, claims SiFive.







SiFive benchmarks showing U84 performance compared to U74 and U54

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The initial U84 design provides 3.1x higher performance than SiFive’s single-core U74 standard core, claims SiFive. The “popular” U74 was announced a year ago along with a quad-core U74-MC design, both of which provide Cortex A55 like, 2.5 DMIPS cores.

The U84 is also claimed to offer 5.4x higher performance than the original U54 core in “isolated process” benchmarks. When fabricated using 7nm technology, the U84 is 7.2x faster than the U54 standard core fabricated in 28nm.The somewhat Cortex-A35 like U54 core is part of the quad-core, 1.5GHz Freedom U540 SoC found on the HiFive Unleashed development board. SiFive makes no mention of OS support, but this is presumably a Linux-oriented processor like the U54 and U74 cores.



HiFive Unleashed

It’s unclear if SiFive’s claims for being the fastest RISC-V IP now available takes into consideration Alibaba’s RISC-V-based, 16-core, XuanTie 910 (XT 910) processor, which has a claimed CoreMark score of 7.1/MHz, compared to 5.1/MHz for the U74. But if the 3.1x performance boost over the U74 is accurate, then the claim would appear to hold up.

The U8-Series performance increases are enabled by a 2.3x increase in IPC (instructions per cycle) combined with a 1.4x increase in maximum frequency capability over the U74, says SiFive.

The U8-Series supports a variety of different fabrication processes, led by a 7nm process that results in a tiny footprint. A hypothetical quad-core SiFive U84 CPU with 2MB of L2 cache would require only 2.63mm2 (square millimeters) to deliver an up to 2.6GHz clock rate, claims SiFive. A single SiFive U8-Series CPU core without L2 cache can be laid out in as little as 0.28mm2.

The U84 standard core is configured with a 12-stage pipeline and triple-issue capability. However, customers can configure options inside the entire Out-Of-Order design space hyperplane. For example, the pipeline depth, issue queue count, and other options can be modified by the customer. Both the U84 and the currently undocumented U87 cores are “fully parameterized to enable the generation of a vast array of configurations, allowing customers to explore the design space and fine-tune performance and features to the desired workload,” says SiFive.

Other customization options include the ability to “cross-issue from the integer unit to the floating point (FP) unit, when the FP queue is empty.” Combined with the “design scalability of number of issue queues” and the FP units in the design, this capability can result in significant performance increases,” says SiFive. The U8-Series Core IP also features composable caches, enabling the processor to be configured for real-time operation support to enable low-latency, deterministic behavior.

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SiFive Mix+Match

The U8-Series supports heterogeneous core complexes for designing SoCs composed of different class cores. This SiFive Mix+Match capability could, for example, support the possibly hypothetical octa-core SoC shown in the block diagram below with a combination of U8-Series and lower power U7-Series cores, as well as an S2-Series MCU.







Block diagram for a hypothetical U84-based SoC that incorporates U74 and S2 cores using SiFive Mix+Match

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SiFive Mix+Match is similar to Arm’s Big.Little multi-core configuration scheme, including the DynamIQ extensions. Intel recently showed off its first heterogeneous design with a 10nm Lakefield SoC that uses a 3D stacking technique called Foveros to combine a Core-like Sunny Cove core with 4x Atom-class Tremont cores.

SiFive also provides a Custom Instruction Extensions feature that enables any core to be loaded with new instructions for easier workload acceleration. Arm recently announced a somewhat similar Custom Instructions extension for its Cortex-M micro-controllers. SiFive, however, appears to go further, enabling the inclusion of Custom Accelerator IP from third parties to be “coherently included” with SiFive’s TileLink coherent fabric for core-to-core communication or SiFive ChipLink coherent fabric for chip-to-chip communications.

Finally, the U8-Series provides a high-bandwidth memory interface IP that supports SiFive TileLink and industry standard protocols for SoC or chiplet style designs. The interface supports memory intensive workloads that require Samsung’s latest HBM2E+ memory technology. “With validation in 7nm and 12nm process technology currently in progress, SiFive is extending high-performance DRAM capabilities from existing 16nm processes to leading-edge technologies,” says the company.



SiFive Shield

SiFive separately announced a SiFive Shield security technology for its RISC-V processors that is somewhat like Arm’s TrustZone. The key component is SiFive WorldGuard, which is described as a “fine-grain security model for isolated code execution and data protection.”







SiFive Worldguard at work on single-core (left) and multi-core processors

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SiFive Worldguard offers “SoC level information control with advanced isolation control, based on multiple levels of privilege per world, and an unlimited amount of worlds,” says SiFive. It also provides core-and process-id driven modes for multi-domain security to protect core, cache, interconnect, peripheral, and memory.

SiFive Shield is further composed of root of trust, threat prevention, and verified crypto-engines. The latter include a NIST SP 800-90A/B/C compliant true random number generator (TRNG) to enable cryptographic or entropy-based security. OS support includes Linux and FreeRTOS, which suggests that it spans both its U5/U7/U8 applications processors and its MCUs such as the E3- and S5-Series.



Further information

The SiFive U84 Core IP is now available for “lead access,” with the U87 to follow. More information may be found in SiFive’s U8-Series announcement. More on the SiFive Shield technology may be found in the SiFive Shield announcement.

