I was intrigued by the coverage of IBM's press release yesterday, which revealed an alliance that produced the first 7nm test chips with functioning transistors.

It's a good step to prove that shrinks in transistor density can continue to that node, but it is also important to note that the IBM group is far from the only group attempting to reach this new node, and that there are many steps between now and actual production.

The announcement stated that the chips were produced at SUNY Polytechnic Institute's Colleges of Nanoscale Science and Engineering (SUNY Poly CNSE) by an alliance that includes IBM Research, GlobalFoundries, and Samsung. Those groups have been working together for some time—IBM at one point had a "common platform" that created chips along with Samsung and GlobalFoundries. While this platform no longer exists, the groups still work together: IBM recently sold its chip-making facilities and many of its chip patents to GlobalFoundries (which has a large chip factory north of Albany), and GlobalFoundries has licensed Samsung's 14nm process technology to make chips at that node.

Smaller transistors are important—the smaller the transistor, the more transistors can fit on a chip, and more transistors mean more powerful chips. IBM believes the new technology could allow for chips with more than 20 billion transistors, which would be a big step forward from existing technology; today's most advanced chips are manufactured using 14nm technology, which thus far only Intel and Samsung have shipped, though TSMC is slated to begin mass production of 16nm chips later this year. A 7nm advance would be a major step forward.

The actual technology involved transistors created with Silicon Germanium (SiGe) channels manufactured using Extreme Ultraviolet (EUV) lithography at multiple levels. IBM said both of these were industry firsts, and this is the first formal announcement I've seen of working chips using both of these technologies.

Note, though, that other groups are working with these same technologies. Every chip maker is evaluating EUV technology, mostly using chip-making equipment from ASML. Intel, Samsung, and TSMC have all invested in ASML to help develop EUV technology, and recently, ASML said one U.S. customer—likely Intel—agreed to buy 15 such tools.

It may be that the use of SiGe channels is the more significant development. Numerous companies have considered types of materials other than silicon, materials which could allow for faster transistor switching and lower power requirements. Applied Materials, for instance, has talked about using SiGe at 10nm or 7nm.

Indeed, many companies—including IBM and Intel—talk about moving beyond SiGe to materials known as III-V compounds, like indium gallium arsenide (InGaAs), which exhibit higher electron mobility. IBM recently demonstrated a technique for using InGaAS on silicon wafers.

Yesterday's announcement is interesting from a lab perspective because of the technologies involved, but there is always a significant gap between lab innovation and cost-effective mass production. Mass production of 10nm chips, which will come before 7nm ones, has yet to be a success.

One big concern has been the high cost of moving to new technologies. While Intel, Samsung, and TSMC have been able to move to smaller nodes, the cost of creating chip designs at such nodes is more expensive, partly because of the complexity of the design and partly because more steps are required when using techniques such as double-patterningsomething EUV could alleviate, but probably will not eliminate. There has also been concern that actual chip density scaling has slowed: IBM's announcement said its 7nm process "achieved close to 50 percent area scaling improvements over today's most advanced technology." That's good, but traditional Moore's Law scaling gives you a 50 percent improvement every generation, and 7nm is two generations away.

On a typical Moore's Law pace, you would expect to see 10nm manufacturing begin toward the end of next year (since the first 14nm chips started manufacturing at the end of 2014), but the transition to 14nm logic took longer than expected for all of the chip makers. DRAM makers are creating new generations that exhibit far less than 50 percent scaling, as DRAM approaches molecular limits, and NAND makers are mostly backing off from planar scaling and instead focusing on 3D NAND at larger geometries. So it won't be all that surprising to see the time between generations lengthen, or the scaling less dramatic. On the other hand, Intel executives have said that while the cost of making each wafer continues to rise for new technologies, they expect to continue to obtain traditional scaling advances in the next generations, so that the cost per transistor will continue to decline at a rate sufficient to make it worthwhile to continue scaling. (Intel also said it believed it could make 7nm without EUV if necessary, though it would prefer to have EUV.)

The work of IBM, SUNY Poly, and their partners on 7nm chips seems to be an important step on the road to readying such chips for mass production toward the end of the decade. Though we are still a long way from cost-effective mass production, this announcement is a clear sign that even if Moore's Law may be slowing, it will continue for at least another couple of generations.