Chiplicity supports community-developed intellectual property cores (IP cores) and ICs and allows community members to create, share, make derivatives of and commercialize their mixed-signal ICs. Chiplicity includes all the tools needed for a full design cycle from idea to completed manufacturable GDSII files. Community members can manufacture their designs as prototypes through Efabless on shuttles at German foundry X-Fab.

It offers IC designers a set of related library components — an open source chip called Hydra, analog IP ready to wire, a standardized pad frame and an SPI serial interface. A soft variant of the PicoRV32 RISC-V CPU core, developed by open source active contributor Clifford Wolf, is part of the Efabless digital library located in the beta version of CloudV.

To date, the Chiplicity platform has been used internally to tapeout two ICs.

Efabless said that in the future Chiplicity will offer a flexible pad frame generator and additional analog and digital IP, including a variety of microprocessor cores, additional open source IP and community-developed analog IP blocks. Efabless also will offer open source test boards as library components to validate custom analog circuit designs.

Efabless currently supports X-Fabs 0.35-micron mixed-signal process. Its technology roadmap includes support for additional foundry processes, such as 180nm and 130nm nodes.

Related links and articles:

www.efabless.com

www.chiplicity.com

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