DARPA Plans a Major Remake of U.S. Electronics

The defense department’s research wing is pouring $1.5 billion into projects that could radically alter how electronics are made

Image: DARPA

The U.S. Defense Advanced Research Projects Agency is launching a huge expansion of its Electronics Resurgence Initiative, boosting the program to US $1.5 billion over five years. And while some of the research efforts will be just what you’ve come to expect from the agency that brought you disposable drones, self-driving cars, and cameras that can see around corners, a lot of this new money is going toward ideas that could fundamentally change how chips are designed.

If it all works out, the effect could be to make small groups of engineers capable of feats that would take 100 engineers to achieve today. “We envision a much more specialized, secure, and heavily automated electronics community, which will change how everything is done in electronics, top to bottom,” says DARPA’s ERI director Bill Chappell. And that means your job is probably going to feel the effects.

The agency will kick off the initiative and reveal some of the winning proposals at a summit in San Francisco from 23 to 25 July, headlined by bigwigs like Nvidia’s Bill Dally and Intel’s Mike Mayberry. Chappell spoke to IEEE Spectrum ahead of the conference about the initiative’s aims and potential impacts.

Bill Chappell on:

IEEE Spectrum: What are the problems with the U.S. electronics industry that prompted this massive effort?

Bill Chappell: I think it’s a unique point in time. We’ve got underlying trends where the physics is already hard and getting harder. And that’s expressing itself in the cost across the board, whether that’s design, manufacturing, or even writing the software on top of a system-on-chip. Most aspects of electronics are getting more expensive, and larger design teams are needed to manage the underlying complexity. That has consequences across commercial industry and across the defense industry.

IEEE Spectrum: What is it about the problem that prevents industry from solving it on its own?

Chappell: Industry is very good at solving immediate problems. Where the government has stepped in in the past, and is trying to step in now, is at moments where there’s a larger leap ahead required. We’re aiming for 2025 to 2030 timelines. And oftentimes, industry isn’t looking out across those timelines as they have more immediate pressures and concerns.

They also don’t always do what’s best for the collective industry. One thing the government has done well in the past is build communities to tackle big problems as an aligned group, as opposed to just having individual entities tackle smaller problems.

IEEE Spectrum: Has this community building become more important as the original version of the semiconductor road map ended?

Chappell: That’s true. When it was quite clear what the road map was, everybody in the electronics industry could pull in the same direction and know that it would be best for the collective if they kept the road map going. That was true for DARPA as well. We were sponsors of the Sematech consortium, and when it was clear what the goals were, it was an easier time in terms of building the collective.

IEEE Spectrum: Why make this big push now, and why organize it as a high-level summit?

Chappell: Typically, we run individual projects. DARPA’s been doing projects in the electronics space since its inception. In this case, we felt that an initiative was important, first because we’re concentrating on the electronic sector more than ever, and second because it’s the connectivity of many different projects. The teaming that can happen between projects, we think, is where a lot of innovation can happen.

We kicked six programs off simultaneously last summer. So it was a good opportunity to pull the entire electronics community together, to be able to see what we’ve invested in, and then to help brainstorm what the next round of investments should look like.

IEEE Spectrum: What’s the best possible outcome from the summit?

Chappell: There are two aspects that we’re hoping for. First, that we realize the synergy between the individual projects, so that new teams form from universities, companies, and federal labs that might otherwise not partner. And second, that we get a basis for new and exciting ideas for a next round of funding that we hope to announce in the fall.

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IEEE Spectrum: One of the three major efforts DARPA is backing centers around chip architecture. Why is that, and what do you hope it will accomplish?

Chappell: In architectures, we believe that aggressive specialization is a part of the answer to what happens next. That’s mapping applications to the specific architectural choices. And you already see that in machine learning, where there’s a really hot field in terms of deep neural nets and other implementations. [See “IBM’s Do-It-All Deep Learning Chip” for an example of this.]

But a lot of our applications are much broader than that. We’re looking to collect the different applications where it makes sense to commit specific specialized resources.

IEEE Spectrum: Can you give an example?

Chappell: We started a year ago in a program called Hive, where we took a look at sparse graph parsing; that’s making associations across data sets which aren’t densely connected. An example application would just be logistics, where you’ve got lots of connections that didn’t map to the way computing architectures were laid out. In that program, Intel and Qualcomm are doing base-level designs; doing things like updating memory access patterns, updating the type of cores that would be doing the processing, and working across the software stack to do a hardware/software codesign for a variety of applications.

That was step one. Step two, to be kicked off at the summit, is something we call “software-defined hardware.” That’s where the hardware is smart enough to reconfigure itself to be the type of hardware you want, based on an analysis of the data type that you’re working on.

In that case, the very hard thing is to figure out how to do that data introspection, how to reconfigure the chip on a microsecond or millisecond timescale to be what you need it to be. And more importantly, it has to monitor whether you’re right or not, so that you can iterate and be constantly evolving toward the ideal solution.

IEEE Spectrum: Is any of that possible now?

Chappell: It ultimately is a coarse-grained reconfigurable architecture; those have existed. What hasn’t existed is how aggressively we’re asking the timescales to do the reconfiguration.

It’s very hard. That’s why we step in to ask a question like that. It’s too early to be starting companies in that space. It’s a very basic question we’re asking.

IEEE Spectrum: What’s the third part of the architecture push?

Chappell: The third wing of the architecture piece is the “domain specific system-on-chip.” We were able to hire the former lead of GNU Radio Foundation, who is an expert in software-defined radio. He had continual frustration trying to lead a community that had difficulty in utilizing specialized hardware. If an SoC was designed, say, for 4G, it was fairly difficult to repurpose that for the more general needs that the software-defined radio community wanted.

So what we’re asking is: If you built a new radio from the ground up, what would it need to include to be able to have specialized resources like accelerators and yet also have the ability for a broad community to build on top of it?

We’re starting with the software-defined radio domain but then extending that to machine vision and machine learning and other domains to see if you can still have simplified programming models running on top of hyperspecialized hardware. That’s an architecture play, but it’s just as much a software play.

IEEE Spectrum: So in a sense, you’re starting with software and then asking what kind of hardware you’d need to execute it?

Chappell: It’s a bit broader than that. We’re starting with all the algorithms that exist in the software-defined radio community, and then collecting the ones where it would be appropriate to do specialization of the architecture. Right now, it’s pretty easy to make an ASIC if you know what your application is. If you have a broader domain, it can be more difficult to get that specialization right, and then it can be even more difficult to write code with an entire community doing very different things on top of that specialization.

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IEEE Spectrum: What do you have planned in the design space?

Chappell: The first program we did is called Craft. Craft is looking at mechanisms to empower small design teams to do much larger designs. For example, we’ve been working with University of California, Berkeley, on the Chisel design flow. It allows you to write high-level programs to create a system-on-chip. But equally as important to us is to create variants of that chip very quickly. Chisel can port to a new technology node with about 20 percent of the effort of the initial design. That would give us flexibility in manufacturing.

IEEE Spectrum: How’s that compare to what can be done now?

Chappell: It’s not atypical for a large SoC design team to be 100 people or more. What we’ve challenged the university community to do is to come up with design methodologies that empower two or three graduate students to automate a lot of that design flow. The Chisel team showed that two to three student designers can do full system-on-chip designs by abstraction and automation.

IEEE Spectrum: That sounds like the kind of thing big design automation companies would want to do.

Chappell: Synopsys, Cadence, and Mentor are involved in that program. So yes, they’re interested, but it’s not something that’s critical on their road map initially.

One of the things we’re trading off is the ultimate efficiency of the design. If 1 percent of area matters because you’re making millions of parts, then this level of abstraction may not be the right one for you. In our case, we’re not as cost-driven. So, if we give away 10 percent of the area but maximize the capabilities of the smaller design team, that’s the kind of tradeoff that would work for the Defense Department, but it also might work for startups and other smaller players like universities.

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IEEE Spectrum: What are the semiconductor design programs you’re kicking off this month?

Chappell: Those are Idea and Posh. Idea is really the intersection of machine learning and electronic design automation (EDA). What we’re trying to do is to be able to capture the capabilities of the designer inside the EDA itself. So that every time you use an EDA package, it gets smarter and your next design is that much easier.

IEEE Spectrum: Does this intelligence get shared so that everyone’s EDA tools get smarter?

Chappell: Eventually. First, we need to demonstrate that the concept is possible. Right now, it’s a vision, and it’s very hard. We have some inklings that show that it should be possible, but it needs a pretty big push from the research community to show what is and isn’t possible in that space.

Once it works, you can envision a cloud resource where multiple people are sharing and can all get better simultaneously. We’d definitely envision that for the university community. How that breaks down for corporate and proprietary lines is yet to be determined.

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IEEE Spectrum: So, tell us about Posh.

Chappell: Posh stands for posh open source hardware. It is an effort to create a foundation of building blocks where we have full understanding and analysis capability as deep as we want to go to understand how these blocks are going to work.

IEEE Spectrum: How’s that different from today?

Chappell: It’s pretty rare to go to GitHub, find high-quality hardware blocks that are available, and have the verification tools and everything you would need to trust that, even though that block has been altered by many different designers, it is in a state that is useable for your design.

Posh is as much about the verification tools as it is about the IP blocks that will be freely available.

IEEE Spectrum: How will this change hardware design?

Chappell: Our vision is that if you’re starting a new design, you have a foundation to build off of. Because so many people have had eyes on a block that you’re not guessing as to what its functionality is and what its origin was. A lot of time when we use third party [intellectual property], you don’t have full custody of it from the beginning to when it actually gets utilized.

This alternative approach looks at how you, hopefully, enhance security of chip design because an open source community has the opportunity to inspect the blocks before you use them.

The emerging example is the RISC-V community, which we sponsored over the last decade. That’s maturing into something that’s interesting, but that’s just one example of what could be contributed to an open source pool of capabilities.

Ultimately, the parallel is to the software community. The hardware community really hasn’t figured out that ethos of sharing. We’re trying to pull some of that excitement and methodology into hardware design.

IEEE Spectrum: What’s held back sharing in hardware?

Chappell: Some of it is culture, in that it’s historically been a proprietary business, because you’ve had to make really large bets. That risk has been rewarded specifically through these proprietary capabilities. As the abstraction of the hardware design gets higher and higher, it gets closer to the software community’s mentality. So that’s why I think you see an emergence of this concept.

Ultimately the reason I don’t think it has taken root in the hardware community is verification. You’re not going to bet $100 [million] to $200 million on a block that was maybe built by a university or, even if it was from another industrial location, you don’t really know the quality of it. So you have to have a methodology to understand how good something is at a deep level before it’s used.

IEEE Spectrum: What are you planning in the third part of the ERI effort—materials and integration?

Chappell: The existing program is called Chips, which looks at really dense integration methodologies to take the monolithic design and split it into many smaller pieces called chiplets. That way we could create, in essence, a “pseudolithic” design—something that would function as though it was monolithic but was in fact composed of smaller parts which can be designed independent of each other. In Chips, we’re working with Intel on some of their integration strategies and on some of their I/O standards and working with the broader community—a mix of startups, universities, and defense contractors—to explore how to stand up the interfaces so that you can do that composable design.

[See “AMD Tackles Coming ‘Chiplet’ Revolution With New Chip Network Scheme” for one take on this.]

With chiplets, if you’re a smaller team, you don’t have to recreate the rest of the chip. If 10 percent of the chip is where you’re going to be innovative and creative, you can focus there and add that into the broader ecosystem. It’s another way of lowering the barrier toward a new hardware capability.

But it depends on really lowering the energy of moving a bit between different chiplets below 1 picojoule per bit or even lower. You’ll never get to monolithic capabilities, but you really want to minimize the barrier between different chips. What we’ve shown is that, if you’re subpicojoule per bit, at least in many cases, then you can do the composable design.

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IEEE Spectrum: What are the two new programs you’ll be revealing at the ERI Summit?

Chappell: One is called 3D SoC. It’s looking at a system-on-chip and asking: What can you do with older manufacturing nodes (like 90 nanometers) to make them competitive with 5-nm or 7-nm design?

We did a series of seedling projects at different universities to show that if you can truly mix dense memory and logic in a monolithic 3D stack, for many applications it would be better in absolute terms than a 7-nm processor design sitting next to a memory block. [Monolithic 3D chips have two or more layers of transistors built on the same piece of silicon.] But it’s ultimately very hard because if you’re going to do the monolithic 3D, then your processing needs to be fully compatible, including low-temperature deposition of materials on top of the silicon base. [For an extreme example, see “3D Electronic Nose Demonstrates Advantages of Carbon Nanotubes”.]

IEEE Spectrum: Would reviving older, trusted fabs or keeping them going longer by using this 3D stacking provide the Defense Department some security against potential foreign hardware trojans and hidden back doors?

Chappell: It does. There are many smaller facilities across our country that if you could do 3D monolithic stacking, they could contribute high-quality electronics.

IEEE Spectrum: What’s the last program you’ll be introducing?

Chappell: The last one is Franc [Framework for Novel Computing], and it looks at new materials for processing-in-memory. We look at where memory is stored and ask: Can those same materials be used for processing information?

What you’d like to do is to be able to explore a variety of different materials and use some of their eccentricities to map to the problems that you’re trying to solve. In the past, we’ve been able to show deep neural nets that use nonvolatile memory as part of the computation in both storing weights and doing the summing of, for example, a dot product. That can be more efficient than just using the memory to store information and then having to transfer it all the way back to the processor.

IEEE Spectrum: That sounds similar to what deep-learning-chip startups Mythic and Syntiant are doing using flash memory.

Chappell: Most of those cases are looking to use today’s existing technology. Franc would be new devices that would amplify that type of capability. Next-generation nonvolatile memory, for example, that switches very fast and with a low write energy.

IEEE Spectrum: Can you give us an example or three?

Chappell: That should be announced at the Summit, so I think I’m going to hold off on that one. There’s one big bet we’re making that will be announced once it’s on contract. And we’ll make lots of smaller bets at universities.

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IEEE Spectrum: Taken together, this stuff sounds like it could lead to a huge change not just in the electronics industry, but in the engineering profession. Was that a goal?

Chappell: A goal is to alter the electronics industry and shape it in a way that works best for our country including the Department of Defense, and you do that by working hand in hand with industry, not around industry.

We’ve had a really long collaboration working with our mainstream industry partners. Way back with the FCRP program, 25 years or more, we’ve done foundational investments in universities across the country. We’ve just announced the Jump program, which is our next round of collaborative funding with industry. It sponsors more than 380 students across the country today, and we plan to host more than 500 students throughout the program’s lifetime. It’s a $200 million program basically on human resource development and idea generation in the basics of electronics.

So, we have a history of collaboration in the electronics space that is actually quite unique in my opinion. It’s not a given that government and industry partners collaborate at that level. This takes it one step further. It will hopefully impact everybody in the electronics field, specifically by making it a much more vibrant and dynamic industry.