While I was at IEDM I had an opportunity to sit down with Subramani (Subi) Kengeri, the Vice President, General Management, CMOS Platforms Business Unit and Jason Gorss from corporate marketing at Global Foundries (GF) for a briefing on GF’s new 22FDX process technology.

Subi told me his background was in design but that he is now the business unit head for Fab 1 in Dresden. The 22FDX platform is being developed to run in Dresden and will be the next generation process for that fab (Dresden most advanced process is currently a 28nm bulk planar process).

22FDX is targeted at mobile computing and the mobile requirements for cost, performance and power. Applications like the internet of things (IOT) will need ~$1 ASPs. Some of the key requirements include:

Cost.

Ultra-low power.

Security and privacy.

Always on sensors and modules.

Dynamic performance and leakage – low leakage for always-on and performance for short bursts.

Multi-patterning is driving up wafer costs. A design for a leading edge FinFET process costs $50-$80 million dollars for the design. To get a reasonable return at a 20% market share you are looking at ~$400 million dollars out of a market with a TAM of $2 to $3 billion dollars. Not many opportunities are that large.

FinFETs are used for the highest performance applications but they consume slightly higher power due to 3D capacitance. For everything else planar FDSOI is the best.

The goal with 22FDX was to maximize the shrink from 28nm, while minimizing double patterning. 22FDX can provide “FinFET like performance” while operating down to 0.4 volts. It is the only technology known today that can operate at that low of a voltage. The technology also offers software tuning of the body bias so that post silicon tuning can be used to dial in performance and recover weak SRAM bits.

My background is in process technology and I was very interested to dig in to how this process is designed. As previously stated GF wanted to minimize multipatterning.

The front-end-of-line (FEOL) transistor is licensed from ST Micro’s 14nm FDSOI process.

Middle-of-line (MOL) includes 2 metal layers (M1 and M2) with double patterning by litho-etch-litho-etch (LE2).

Back-end-of-line (BEOL) is all single patterned to keep down costs.

The process is basically a 14nm FEOL with a 22nm BEOL to minimize costs.

There are four versions of the process:

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22FDX-ulp – ultra-low power – special SRAM and doping optimization.

22FDX-uhp – ultra-high performance – BEOL stack optimization and MIM capacitors.

22FDX-ull – ultra-low leakage – adds dual gate oxide to create a thick oxide ultra-low leakage device.