I've designed with FETs since I was a kid. Several jobs ago, I used lots of depletion mode N-channel JFETs as the heart of a flame detector in some gas ignition and control devices we manufactured. Those took advantage of the slight rectification ability due to the ionization process in a burning flame. In a more recent job, I used enhancement mode N- and P-channel MOSFETs on various power and signal control circuits.

I mention all this as background. I received a press release from Advanced Linear Devices (ALD) that talked about their new precision dual N-channel MOSFET that is “precision matched at the factory” so I don't have to. I'm certainly in favor of that, having designed and built fixtures to match FETs and then tested and binned them.

This would be useful for differential input stages or as part of a current mirror, so being matched is absolutely what I'd want. But the other selling points had me scratching my head. One point said the device features “…high DC current gain (>108 ). A sample calculation of the DC current gain at a drain output current of 30mA and input current of 300pA at 25°C is 30mA/300pA = 100,000,000, which translates into a dynamic operating current range of about eight orders of magnitude.”

High current gain? This is an N-channel FET, not a BJT. It's a transconductance device — voltage input, current output. But wait — the gate threshold voltage “features Zero-Threshold voltage.” Hmm… I suppose that would make it a good part to use for very low-voltage circuits, except that with a zero voltage threshold, how do you know if it's on or off?

The graph from the data sheet confirms that the threshold is right around zero. The likely thing that's done in the FET processing to make this happen is (probably) making the conduction channel (drain to source) very narrow, and making the gate oxide (insulating) layer super thin. Which makes it prone to leakage. Which would mean you'd get gate current flow. Aha! That's why they have that parameter (above) that makes it look like it has a beta of a hundred-million.

And with such a low threshold voltage, they can claim that “…a circuit with multiple cascading stages can be built to operate at extremely low supply/bias voltage levels. For example, a nanopower input amplifier stage operating at <0.2V supply voltage has been successfully built." I suppose so, but how do you turn it off?

My mistake here is assuming the device is simply a conventional enhancement mode FET. It's not quite that. Nor is it exactly a depletion mode. It's right in the middle. You'd need to bias the gate just a little negative to make sure it's off. And you'd only need to bias the gate just tens of millivolts positive to make sure it's on. So this would be dandy for energy harvesting circuits (about which we've written before). Amplifier circuitry for sensors, ultra-low power boost switchers, some logic circuits, or circuits where the FET should be “normally on” would benefit.

We'll do some more research on these parts and let you know what we learn. And please let us know if you have applications that could use a device like this.

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