The IP is available through makeChip, Racyics' hosted design service platform targeted at startups, small companies, research institutes and universities.

Racyics has executed power-performance-area (PPA) studies for both Cortex and RISC-V based microcontrollers (MCUs) operating at supply voltages down to 0.4V on 22FDX and in Decmeber 2017 it taped out a Cortex-based test chip for silicon validation of its adaptive body bias (ABB) design approach and to show the potential for MCU implementations.

"The 22FDX design flow and IP used for this test chip implemented by us is available at makeChip," Holger Eisenreich, co-founder and CEO of Racyics, told eeNews Europe in an email exchange. "We are currently developing SoC template designs, which we plan to provide to makeChip customers as an ultra-low voltage (ULV), ABB reference implementation or as base for their own customized ULV SoC."



Holger Eisenreich, CEO of Racyics



Eisenreich added that the SRAM arrays operate from dual voltage rails based on the Globalfoundries bit-cell kit with the periphery of SRAM operating at 0.4V and the bit cell array using a supply of 0.72V. SRAMs are typically the circuit type that is least able to scale with voltage.

Racyics has developed its own circuits for monitoring of process, voltage and temperature (PVT) that are already silicon-proven in 22FDX. "This is essential for our ABB platform, because the characteristics of the monitors are one input for the ULV library characterisation. Different back bias voltages are used for the different corner characterizations. These voltages are determined by a virtual ABB regulation. This is a new patent pending approach, enabling an ABB aware implementation and sign-off, leading to much better PPA results."

Eisenreich continued: "From our point of view, Implementation of ULP IoT-like designs at less than 0.5V are only possible based on an ABB scheme. Our ABB approach is even beneficial at 0.8V, resulting in 20 percent more performance in the worst delay corner while having at the same time 25 percent less leakage in the best delay corner. This equals almost another halve node shrink."

Next: What non-volatile memory?