In my last article on plain old Verilog Arrays, I discussed their very limited feature set. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable test benches. In this article, we’ll take a look at the synthesizable features of SystemVerilog Arrays we can use when writing design RTL.

Packed vs Unpacked SystemVerilog Arrays

Verilog had only one type of array. SystemVerilog arrays can be either packed or unpacked. Packed array refers to dimensions declared after the type and before the data identifier name. Unpacked array refers to the dimensions declared after the data identifier name.

Packed vs unpacked SystemVerilog arrays bit [7:0] c1; // packed array of scalar bit real u [7:0]; // unpacked array of real int Array[0:7][0:31]; // unpacked array declaration using ranges int Array[8][32]; // unpacked array declaration using sizes 1 2 3 4 5 bit [ 7 : 0 ] c1 ; // packed array of scalar bit real u [ 7 : 0 ] ; // unpacked array of real int Array [ 0 : 7 ] [ 0 : 31 ] ; // unpacked array declaration using ranges int Array [ 8 ] [ 32 ] ; // unpacked array declaration using sizes

Packed Arrays

A one-dimensional packed array is also called a vector. Packed array divides a vector into subfields, which can be accessed as array elements. A packed array is guaranteed to be represented as a contiguous set of bits in simulation and synthesis.

Packed arrays can be made of only the single bit data types (bit, logic, reg), enumerated types, and other packed arrays and packed structures. This also means you cannot have packed arrays of integer types with predefined widths (e.g. a packed array of byte).

Unpacked arrays

Unpacked arrays can be made of any data type. Each fixed-size dimension is represented by an address range, such as [0:1023], or a single positive number to specify the size of a fixed-size unpacked array, such as [1024]. The notation [size] is equivalent to [0:size-1].

Indexing and Slicing SystemVerilog Arrays

Verilog arrays could only be accessed one element at a time. In SystemVerilog arrays, you can also select one or more contiguous elements of an array. This is called a slice. An array slice can only apply to one dimension; other dimensions must have single index values in an expression.

Multidimensional Arrays

Multidimensional arrays can be declared with both packed and unpacked dimensions. Creating a multidimensional packed array is analogous to slicing up a continuous vector into multiple dimensions.

When an array has multiple dimensions that can be logically grouped, it is a good idea to use typedef to define the multidimensional array in stages to enhance readability.

SystemVerilog multidimensional arrays bit [3:0] [7:0] joe [0:9] // 10 elements of 4 8-bit bytes // (each element packed into 32 bits) typedef bit [4:0] bsix; // multiple packed dimensions with typedef bsix [9:0] v5; // equivalent to bit[4:0][9:0] v5 typedef bsix mem_type [0:3]; // array of four unpacked 'bsix' elements mem_type ba [0:7]; // array of eight unpacked 'mem_type' elements // equivalent to bit[4:0] ba [0:3][0:7] - thanks Dennis! 1 2 3 4 5 6 7 8 9 bit [ 3 : 0 ] [ 7 : 0 ] joe [ 0 : 9 ] // 10 elements of 4 8-bit bytes // (each element packed into 32 bits) typedef bit [ 4 : 0 ] bsix ; // multiple packed dimensions with typedef bsix [ 9 : 0 ] v5 ; // equivalent to bit[4:0][9:0] v5 typedef bsix mem _ type [ 0 : 3 ] ; // array of four unpacked 'bsix' elements mem_type ba [ 0 : 7 ] ; // array of eight unpacked 'mem_type' elements // equivalent to bit[4:0] ba [0:3][0:7] - thanks Dennis!

SystemVerilog Array Operations

SystemVerilog arrays support many more operations than their traditional Verilog counterparts.

+: and -: Notation

When accessing a range of indices (a slice) of a SystemVerilog array, you can specify a variable slice by using the [start+:increment width] and [start-:decrement width] notations. They are simpler than needing to calculate the exact start and end indices when selecting a variable slice. The increment/decrement width must be a constant.

SystemVerilog array slices bit signed [31:0] busA [7:0]; // unpacked array of 8 32-bit vectors int busB [1:0]; // unpacked array of 2 integers busB = busA[7:6]; // select a 2-vector slice from busA busB = busA[6+:2]; // equivalent to busA[7:6]; typo fixed, thanks Tomer! 1 2 3 4 bit signed [ 31 : 0 ] busA [ 7 : 0 ] ; // unpacked array of 8 32-bit vectors int busB [ 1 : 0 ] ; // unpacked array of 2 integers busB = busA [ 7 : 6 ] ; // select a 2-vector slice from busA busB = busA [ 6 + : 2 ] ; // equivalent to busA[7:6]; typo fixed, thanks Tomer!

Assignments, Copying, and other Operations

SystemVerilog arrays support many more operations than Verilog arrays. The following operations can be performed on both packed and unpacked arrays.

SystemVerilog arrays operations A = B; // reading and writing the array A[i:j] = B[i:j]; // reading and writing a slice of the array A[x+:c] = B[y+:d]; // reading and writing a variable slice of the array A[i] = B[i]; // accessing an element of the array A == B; // equality operations on the array A[i:j] != B[i:j]; // equality operations on slice of the array 1 2 3 4 5 6 A = B ; // reading and writing the array A [ i : j ] = B [ i : j ] ; // reading and writing a slice of the array A [ x + : c ] = B [ y + : d ] ; // reading and writing a variable slice of the array A [ i ] = B [ i ] ; // accessing an element of the array A == B ; // equality operations on the array A [ i : j ] != B [ i : j ] ; // equality operations on slice of the array

Packed Array Assignment

A SystemVerilog packed array can be assigned at once like a multi-bit vector, or also as an individual element or slice, and more.

SystemVerilog packed array assignment logic [1:0][1:0][7:0] packed_3d_array; always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin packed_3d_array <= '0; // assign 0 to all elements of array end else begin packed_3d_array[0][0][0] <= 1'b0; // assign one bit packed_3d_array[0][0] <= 8'h0a; // assign one element packed_3d_array[0][0][3:0] <= 4'ha; // assign part select packed_3d_array[0] <= 16'habcd; // assign slice packed_3d_array <= 32'h01234567; // assign entire array as vector end 1 2 3 4 5 6 7 8 9 10 11 12 13 logic [ 1 : 0 ] [ 1 : 0 ] [ 7 : 0 ] packed_3d_array ; always _ ff @ ( posedge clk , negedge rst_n ) if ( ! rst_n ) begin packed_3d_array <= '0; // assign 0 to all elements of array end else begin packed_3d_array[0][0][0] <= 1' b0 ; // assign one bit packed_3d_array [ 0 ] [ 0 ] <= 8 'h0a; // assign one element packed_3d_array[0][0][3:0] <= 4' ha ; // assign part select packed_3d_array [ 0 ] <= 16 'habcd; // assign slice packed_3d_array <= 32' h01234567 ; // assign entire array as vector end

Unpacked Array Assignment

All or multiple elements of a SystemVerilog unpacked array can be assigned at once to a list of values. The list can contain values for individual array elements, or a default value for the entire array.

SystemVerilog unpacked array assignment logic [7:0] a, b, c; logic [7:0] d_array[0:3]; logic [7:0] e_array[3:0]; // note index of unpacked dimension is reversed // personally, I prefer this form logic [7:0] mult_array_a[3:0][3:0]; logic [7:0] mult_array_b[3:0][3:0]; always_ff @(posedge clk, negedge rst_n) if (!rst_n) begin d_array <= '{default:0}; // assign 0 to all elements of array end else begin d_array <= '{8'h00, c, b, a}; // d_array[0]=8'h00, d_array[1]=c, d_array[2]=b, d_array[3]=a e_array <= '{8'h00, c, b, a}; // e_array[3]=8'h00, e_array[2]=c, e_array[1]=b, d_array[0]=a mult_array_a <= '{'{8'h00, 8'h01, 8'h02, 8'h03}, '{8'h04, 8'h05, 8'h06, 8'h07}, '{8'h08, 8'h09, 8'h0a, 8'h0b}, '{8'h0c, 8'h0d, 8'h0e, 8'h0f}}; // assign to full array mult_array_b[3] <= '{8'h00, 8'h01, 8'h02, 8'h03}; // assign to slice of array end 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 logic [ 7 : 0 ] a , b , c ; logic [ 7 : 0 ] d_array [ 0 : 3 ] ; logic [ 7 : 0 ] e_array [ 3 : 0 ] ; // note index of unpacked dimension is reversed // personally, I prefer this form logic [ 7 : 0 ] mult_array_a [ 3 : 0 ] [ 3 : 0 ] ; logic [ 7 : 0 ] mult_array_b [ 3 : 0 ] [ 3 : 0 ] ; always _ ff @ ( posedge clk , negedge rst_n ) if ( ! rst_n ) begin d_array <= '{default:0}; // assign 0 to all elements of array end else begin d_array <= ' { 8 'h00, c, b, a}; // d_array[0]=8' h00 , d_array [ 1 ] = c , d_array [ 2 ] = b , d_array [ 3 ] = a e_array <= '{8' h00 , c , b , a } ; // e_array[3]=8'h00, e_array[2]=c, e_array[1]=b, d_array[0]=a mult_array_a <= '{' { 8 'h00, 8' h01 , 8 'h02, 8' h03 } , '{8' h04 , 8 'h05, 8' h06 , 8 'h07}, ' { 8 'h08, 8' h09 , 8 'h0a, 8' h0b } , '{8' h0c , 8 'h0d, 8' h0e , 8 'h0f}}; // assign to full array mult_array_b[3] <= ' { 8 'h00, 8' h01 , 8 'h02, 8' h03 } ; // assign to slice of array end

Conclusion

This article described the two new types of SystemVerilog arrays—packed and unpacked—as well as the many new features that can be used to manipulate SystemVerilog arrays. The features described in this article are all synthesizable, so you can safely use them in SystemVerilog based RTL designs to simplify coding. In the next part of the SystemVerilog arrays article, I will discuss more usages of SystemVerilog arrays that can make your SystemVerilog design code even more efficient. Stay tuned!

Resources

Sample Source Code

The accompany source code for this article is a toy example module and testbench that illustrates SystemVerilog array capabilities, including using an array as a port, assigning multi-dimensional arrays, and assigning slices of arrays. Download and run it to see how it works!

Download Article Companion Source Code Get the FREE, EXECUTABLE test bench and source code for this article, notification of new articles, and more!

