Intel C++ Compiler 18.0 for Linux* Release Notes for Intel Parallel Studio XE 2018

This document provides a summary of new and changed product features and includes notes about features and problems not described in the product documentation.

Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 18.0.

Change History

Changes in Update 5 (Intel® C++ Compiler 18.0.5)

• Intel® Parallel Studio XE 2018 Update 5 has been updated to include more recent versions of 3rd party components, which include functional and security updates. Users should update to the latest version.



NOTE: Although the Intel® Parallel Studio XE 2018 package for this update release is Update 5, the actual compiler version and directories you see will be 2018.6.xxx. This is because of an internal update in our build process. Be assured that the 2018.6.xxx directories and product versions 18.0.6 in packages you see during installation are indeed for the Intel® Parallel Studio 2018 Update 5 release.

Changes in Update 4 (Intel® C++ Compiler 18.0.4)

Corrections to reported problems

Changes in Update3 (Intel® C++ Compiler 18.0.3)

Changes to mitigate speculative executive side channel issue and new -mconditional-branch option. Please see detailed article at Using Intel® Compilers to Mitigate Speculative Execution Side-Channel Issues available at /content/www/us/en/develop/articles/using-intel-compilers-to-mitigate-speculative-execution-side-channel-issues.html

__INTEL_LIBIRC_DEBUG environment variable

-[a]xIcelake-server and -[a]xIcelake-client options added to support Ice Lake microarchitecture

-[a]xCannonlake option added to support Cannon Lake microarchitecture

Corrections to reported problems

Changes in Update 2 (Intel® C++ Compiler 18.0.2)

Support for the new codenames for targeting specific cpu

Changes to mitigate speculative executive side channel issue and new -mindirect-branch option. Please see detailed article at Using Intel® Compilers to Mitigate Speculative Execution Side-Channel Issues available at /content/www/us/en/develop/articles/using-intel-compilers-to-mitigate-speculative-execution-side-channel-issues.html)

Fixes for reported problems

Changes in Update 1 (Intel® C++ Compiler 18.0.1)

Intel’s OpenMP runtime support library is now linked dynamically even when -static-intel is specified. To link the OpenMP library statically, specify -qopenmp-link=static. The default behaviour showen in 18.0.0 was incorrect and has been corrected.

First Update with Japanese localization

Fixes for reported problems

Changes since Intel® C++ Compiler 17.0 (New in Intel® C++ Compiler 18.0)

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System Requirements

A PC based on an Intel® 64 architecture processor supporting the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instructions ( Intel® 2nd Generation or newer Generation of Intel® Core™ i3, i5, or i7 processors and Intel® Xeon® E3 or E5 processor family , or compatible non-Intel processor) Development of 64-bit applications or applications targeting Intel® MIC Architecture is supported on a 64-bit version of the OS only. Development of 32-bit applications is now supported on a 64-bit version of the OS only. The compiler cannot be installed on a 32-bit OS. Development for a 32-bit target on a 64-bit host may require optional library components (ia32-libs, lib32gcc1, lib32stdc++6, libc6-dev-i386, gcc-multilib, g++-multilib) to be installed from your Linux distribution.

, or compatible non-Intel processor) For Intel® MIC Architecture development/testing: Intel® Manycore Platform Software Stack (Intel® MPSS)

For offload to or native support for Intel® Graphics Technology development/testing Offload is supported from 64-bit applications only A 64-bit graphics driver with support for Intel® Graphics Technology (available from the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com). You should have access to the Intel® HD Graphics Drivers for Linux* download area as part of your Intel® Parallel Studio XE registration. If you do not see this area, please contact support. The following driver versions, corresponding operating systems, and processors are supported: Intel® HD Graphics Drivers for Linux* version 16.4.4 for 4th Generation Intel® Core™ Processors and 5th Generation Intel® Core™ Procesors CentOS* 7.1 for 64-bit architecture Red Hat Enterprise Linux* 7.1 for 64 bit architecture The following processors are supported: 5th Generation Intel Core™ Processors with Intel Iris™ Graphics or Intel HD Graphics (5500, 6000, 6100). 4th Generation Intel Core™ Processors with Intel Iris™ Pro Graphics, Intel Iris Graphics or Intel HD Graphics 4200+ Series (chipset compatibility is usually not an issue for Core™ processors.) Intel® Xeon® Processor E3 v3 Family with Intel® HD Graphics P4700 Intel® Xeon® Processor E3 v4 Family with Intel® Iris™ Pro Graphics P6300 Please note: Chipset must have processor graphics enabled, make sure to check the datasheet. Intel® Xeon® Processors require C226 chipset. Intel Core processors earlier than 4th Generation are not supported Intel Celeron®, Intel Pentium® and Intel Atom™ processors are not supported

For the best experience, a multi-core or multi-processor system is recommended

2GB of RAM (4GB recommended)

7.5GB free disk space for all features

One of the following Linux distributions (this is the list of distributions tested by Intel; other distributions may or may not work and are not recommended - please refer to Technical Support if you have questions): Debian* 7.0, 8.0, 9.0 Fedora* 24, 25, 26 Red Hat Enterprise Linux* 6, 7 SUSE LINUX Enterprise Server* 11, 12 Ubuntu* 14.04 LTS, 15.10, 16.10, 16.04, 17.04 LTS Intel® Cluster Ready

Linux Developer tools component installed, including gcc, g++ and related tools gcc versions 4.3 - 6.3 supported binutils versions 2.20-2.26 supported

Library libunwind.so is required in order to use the –traceback option. Some Linux distributions may require that it be obtained and installed separately.

Additional requirements to use the integration into the Eclipse* development environment

Eclipse Platform version 4.6 with: Eclipse C/C++ Development Tools (CDT) 8.8 or 9.0 Java* Runtime Environment (JRE) 8.0 (also called 1.8) or later

Eclipse Platform version 4.5 with: Eclipse C/C++ Development Tools (CDT) 8.7 Java* Runtime Environment (JRE) 7.0 (also called 1.7) or later

Eclipse Platform version 4.4 with: Eclipse C/C++ Development Tools (CDT) 8.4-8.6 Java* Runtime Environment (JRE) 7.0 (also called 1.7) or



Notes

The Intel compilers are tested with a number of different Linux distributions, with different versions of gcc. Some Linux distributions may contain header files different from those we have tested, which may cause problems. The version of glibc you use must be consistent with the version of gcc in use. For best results, use only the gcc versions as supplied with distributions listed above.

Compiling very large source files (several thousands of lines) using advanced optimizations such as -O3, -ipo and -openmp, may require substantially larger amounts of RAM.

The above lists of processor model names are not exhaustive - other processor models correctly supporting the same instruction set as those listed are expected to work. Please refer to Technical Support if you have questions regarding a specific processor model

Some optimization options have restrictions regarding the processor type on which the application is run. Please see the documentation of these options for more information.

Intel continually evaluates the markets for our products in order to provide the best possible solutions to our customer’s challenges. As part of this on-going evaluation process Intel has decided to not offer Intel® Xeon Phi™ 7200 Coprocessor (codenamed Knights Landing Coprocessor) products to the market Given the rapid adoption of Intel® Xeon Phi™ 7200 processors, Intel has decided to not deploy the Knights Landing Coprocessor to the general market. Intel® Xeon Phi™ Processors remain a key element of our solution portfolio for providing customers the most compelling and competitive solutions possible.



Intel® Manycore Platform Software Stack (Intel® MPSS)

The Intel® Manycore Platform Software Stack (Intel® MPSS) may be installed before or after installing the Intel® C++ Compiler.

Using the latest version of Intel® MPSS available is recommended. It is available from the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com as part of your Intel® Parallel Studio XE for Linux* registration.

Refer to the Intel® MPSS documentation for the necessary steps to install the user space and kernel drivers.

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How to use the Intel® C++ Compiler

Intel® Parallel Studio XE 2018: Getting Started with the Intel® C++ Compiler 18.0 for Linux* at <install-dir>/documentation_2018/en/compiler_c/ps2018/get_started_lc.htm. contains information on how to use the Intel® C++ Compiler from the command line and from Linux*.

The Intel® C++ Compiler for Linux* does not provide "modulefiles" for usage with the Environmental Modules software utility, but is well suited for such usage. See Using Environment Modules with Intel Development Tools for further information.

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Documentation

Product documentation is linked from <install-dir>/documentation_2018/en/compiler_c/ps2018/get_started_lc.htm. Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.

Offline Core Documentation Removed from the Installed Image

Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.

Japanese Language Support

Intel® compilers optionally provide support for Japanese language users when the combined English-Japanese product is installed. Error messages, visual development environment dialogs and some documentation are provided in Japanese in addition to English. By default, the language of error messages and dialogs matches that of your operating system language selection. Japanese-language documentation can be found in the ja subdirectory for documentation.

Japanese language support is not provided with this update of the product.

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Intel-provided debug solutions

Intel®-provided debug solutions are based GNU* GDB. Please see Intel® Parallel Studio XE 2018 Composer Edition C++ - Debug Solutions Release Notes for further information.

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Samples

Product samples are now available online at Intel® Software Product Samples and Tutorials

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Technical Support

If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.

For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/

Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.

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New and Changed Features

The following features are new or significantly enhanced in this version. For more information on these features, please refer to the documentation.

__INTEL_LIBIRC_DEBUG environment variable

If OS/HW work incorrectly and libirc gets a cache size of 0 from CPUID, it may cause performance degradation. In such case user can define env. variable __INTEL_LIBIRC_DEBUG=1 to identify the root cause and get the information about OS/HW issue, e.g. export __INTEL_LIBIRC_DEBUG=1

Support for the new codenames for targeting specific cpu

Support for the following new cpuid(codenames)

haswell

broadwell

skylake

skylake_avx512

knl

knm

In the following function attributes (meaning manual targeting of those functions to the specified cpu codename): C/C++ __attribute__((cpu_dispatch( )))

C/C++ __attribute__((cpu_specific( )))

C/C++ __attribute__((vector(processor()))

monotonic and overlap keywords for ordered block in simd context

New keywords for existing #pragma omp ordered simd

#pragma omp ordered simd monotonic()

#pragma omp ordered simd overlap(expr)

#pragma omp simd reduction(=: list)

Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details

Support of hardware based PGO

Profile Guided Optimization (PGO) Hardware-based event sampling is a new low overhead model to get (many) benefits of PGO using the Intel® Compiler and the Intel® VTune™ Amplifier. Data collection works on systems where Intel® VTune™ Amplifier is supported.

Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details

Parallel STL for parallel and vector execution of the C++ STL

Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.

For more information about Parallel STL, see Getting Started and Release Notes .

To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl

Change in behavior of extract ( _mm256_extract_epi8 ) instrinics return type

Intel defined 256-bit vector intrinsics _m256_extract_epi8/epi16(__m256i a, const int index) return int instead of __int8/__int16 values.

New option -Qimf-use-svml to enforce SVML

New option forces use of SVML where currently LIBM is used, for scalar math. This guarantees bitwise-same result of computations made with vectorized code vs computations made with scalar code. With this feature the compiler vectorizes math functions in /fp:precise FP model and vectorized code produces results consistent with scalar code results.

New /qopt-zmm-usage option

You can tune the zmm code generation done by the compiler with the new additional option -qopt-zmm-usage:low|high. The argument value of low provides a smooth transition experience from - Intel® Advanced Vector Extensions 2 (Intel® AVX2) ISA to Intel® Advanced Vector Extensions 512 (Intel® AVX-512) ISA on a Intel® Xeon® Platinum processor (formerly code name Skylake), such as for enterprise applications. Tuning for ZMM instruction use via explicit vector syntax such as #pragma omp simd simdlen() is recommended. The argument value of high is recommended for applications, such as HPC codes, that are bounded by vector computation to achieve more compute per instruction through use of the wider vector operations. The default value is low for Skylake server microarchitecture-family compilation targets and high for Intel® Core™ /Intel® Many Integrated Core Architecture (Intel® MIC Architecture) Intel® AVX-512 combined compilation targets.

CET - Control-Flow Enforcement Technology support

Control-flow Enforcement Technology (CET) defends a program from certain attacks that exploit vulnerabilities, e.g. Return-oriented Programming (ROP) and similarly Call/Jmp-oriented Programming (COP/JOP). Please refer to the preview document for more details.

New compiler option /Qcf-potection[:keyword] introduced in the compiler to support CET.

Compile time dispatching for SVML calls

The compiler default behaviour is changed for SVML functions and a call to cpu-specific SVML entry is performed. Specifying new option -Qimf-force-dynamic-target reverts to the previous behavior and dynamic SVML dispatching is used.

Features from OpenMP* TR4 Version 5.0 Preview 1

Language features for task reductions from the OpenMP* Technical Report 4 : Version 5.0 Preview 1 specifications are now supported.

TASKGROUP now has the TASK_REDUCTION clause.

TASK includes now has the IN_REDUCTION clause

TASKLOOP now has the REDUCTION and IN_REDUCTION clauses

For more information, see the compiler documentation or the link to the OpenMP* Specification above.

Support for more new features from OpenMP* 4.0 or later

taskloop construct feature #pragma omp taskloop[clause[[,]clause]..]

Support for #pragma omp for linear (list [ : linear-step ]) where list is either list or modifier(list)

Support for ref, val, and uval modifiers for the linear clause Examples: linear(ref(p)), linear(val(i):1), linear(uval(j):1)

Support for #pragma omp simd simdlen(n)

Support for #pragma omp ordered [simd]

Reductions over whole arrays: int x[n]; #pragma omp simd reduction(+:x)

Intel® processor clause extension added to #pragma omp declare simd (proposed; not officially part of OpenMP* 4.5)

support for clauses SIMD and NONMONOTONIC modifiers for #pragma omp for schedule : The Intel® C++ Compiler 18.0 include SIMD and NONMONOTONIC modifiers extenstion to schedule clause to enhance user control of how interations of the for loop are divided among threads of team. See the Intel® C++ Compiler User’s Guide for more details.

and modifiers for support for array sections as list items in the reduction clause reduction(reduction-identifier:list) If a list item is an array section, it is treated as if reduction clause is applied to each seperate element of the section. The elements of the private array sections will be allocated contiguously



C++17 features supported

The Intel® C++ Compiler 18.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/macOS*) options:

Static assert with no message (N3928)

Relaxed Range based for loops (N3994)

Please see C++17 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

C11 features supported

The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11 (Linux*/macOS*) options:

Support for all C11 features including C11 keyword _Atomic and __attribute((atomic))

Please see C11 Support in Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.

New and Changed Compiler Options

For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.

All –o* options replaced by –qo* options All the –o* options deprecated in the previous release have been replaced with –qo* options in this release with one noted exception, there is no change to the –o option for Linux* and macOS* used to name the output file. On Windows*, this change impacts compiler options passed to the target compilation with the /Qoffload-option Compiler option. A new diagnostic is issued when any now replaced –o option is used. For example: $ icc -openmp example.c

icc: command line error: option '-openmp' is not supported. Please use the replacement option '-qopenmp' Options affected: -[no-]openmp

-openmp-lib=<arg>

-openmp-link=<arg>

-[no-]openmp-offload

-[no-]openmp-simd

-openmp-stubs

-openmp-threadprivate=<arg>

-openmp-report[=<level>]

-openmp-task=<arg>

-opt-args-in-regs=<arg>

-[no-]opt-assume-safe-padding

-opt-block-factor=<arg>

-[no-]opt-calloc

-[no-]opt-class-analysis

-[no-]opt-dynamic-align

-[no-]opt-gather-scatter-unroll

-[no-]opt-jump-tables=<arg>

-opt-malloc-options=<arg>

-[no-]opt-matmul

-[no-]opt-mem-layout-trans=<arg>

-[no-]opt-multi-version-aggressive

-[no-]opt-prefetch[=<val>]

-opt-prefetch-distance=<arg>

-opt-ra-region-strategy[=<arg>]

-[no-]opt-report-embed

-opt-report-file=<arg>

-opt-report-filter=<arg>

-opt-report-format=<arg>

-opt-report-phase=<arg>

-opt-report-routine=<arg>

/opt-report-help

/opt-report[=<arg>]

/opt-report-per-object

/opt-streaming-cache-evict=<arg>

/opt-streaming-stores=<arg>

/[no-]opt-subscript-in-range

/opt-threads-per-core=<arg>

For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.

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Support Deprecated

Intel® Cilk™ Plus deprecated in 18.0

Intel® Cilk™ Plus is a deprecated feature in the Intel® C++ Compiler 18.0. Prefer to use OpenMP-based syntax for offloading to the processor graphics. For more information see Migrate Your Application to use OpenMP* or Intel® Threading Building Blocks (Intel® TBB) Instead instead of Intel® Cilk™ Plus

Support for 32-bit icc wrapper deprecated in 18.0

icc: remark #10421: The IA-32 target wrapper binary 'icc' is deprecated. Please use the compiler startup scripts or the proper Intel(R) 64 compiler binary with the '-Qm32' option to target the intended architecture

Support Removed

Support for the Intel® Xeon Phi™ x100 product family coprocessor (formerly code name Knights Corner) is removed in this release

In Visual Studio, code Generation [Intel C++] >Offload Target Architecture(/Qoffload-Arch): "mic" argument is de-exposed

"mic" value saved in project for Intel C++ Compiler 17.0 platform toolset is updated to "default" value after upgrading to 18.0 platform toolset

Support for installation on IA-32 hosts has been removed

Support for installation on IA-32 hosts has been removed. Support for generating code for 32-bit targets is supported on 64-bit hosts (only) via compiler option /Qm32

Red Hat Enterprise Linux 5* is not supported

Support has been removed for installation and use on these operating system versions. Intel recommends migrating to a newer version of these operating systems.

GFX offload support for 3rd Generation Intel® Core™ Processors is not supported

hwo offload support to processor graphics for 3rd Generation Intel® Core™ Processors has been removed in Intel® C++ Compiler 17.0.

Intel® HD Graphics Drivers for Linux* version 16.3.2 for 3rd and 4th Generation Intel® Core™ Processors are not supported.

Support for the 16.3.2 driver has removed. Intel recommends migrating to the 16.4.2 driver and its supporting operating system (either CentOS* 7.1 or RHEL 7.1) for systems based on 4th Generation Intel® Core™ Processors.

Installation on 32-bit hosts has been removed

Installation on 32-bit hosts has been removed in this release. Support for generating code for 32-bit targets is supported on 64-bit hosts (only) via compiler option -m32.

_GFX_enqueue has been removed

_GFX_enqueue has been removed and should be replaced with _GFX_offload

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Pointer Checker requires a dynamic runtime library

When using the -check-pointers option, the runtime library libchkp.so must be linked in. When using options like -static or -static-intel with -check-pointers, be aware that this dynamic library will be linked in regardless of your settings. See the article at http://intel.ly/1jV0eWD for more information.

Known Issues with Intel® Many Integrated Core Architecture (Intel® MIC Architecture)

Runtime Type Information (RTTI) not supported



Runtime Type Information (RTTI) is not supported under the Virtual-Shared memory programming method; specifically, use of dynamic_cast<> and typeid() is not supported.



Known issues for offload to Intel® Graphics Technology

Host-side execution of offload code is not parallelized



The compiler will generate both a target and host version of the parallel loop under #pragma offload. The host version is executed when the offload cannot be performed (usually when the target system does not have a unit with Intel® Graphics Technology enabled).The parallel loop must be specified using the parallel syntax of cilk_for or an Array Notation statement, which has parallel semantics for offload. The target version of the loop will be parallelized for target execution, but there is a current limitation where the host-side back-up version of the parallel loop will not be parallelized. Please be aware this can affect the performance of the back-up code execution significantly when offload execution does not happen in the case of cilk_for use. Array notation does not currently generate parallel code on the host, so performance should not differ here in that case. This is a known issue that may be resolved in a future product release.



The compiler will generate both a target and host version of the parallel loop under #pragma offload. The host version is executed when the offload cannot be performed (usually when the target system does not have a unit with Intel® Graphics Technology enabled).The parallel loop must be specified using the parallel syntax of cilk_for or an Array Notation statement, which has parallel semantics for offload. The target version of the loop will be parallelized for target execution, but there is a current limitation where the host-side back-up version of the parallel loop will not be parallelized. Please be aware this can affect the performance of the back-up code execution significantly when offload execution does not happen in the case of cilk_for use. Array notation does not currently generate parallel code on the host, so performance should not differ here in that case. This is a known issue that may be resolved in a future product release. If multiple processes running with non-root privilege try to offload there may be sporadic fails.



You may see sporadic fails if multiple processes (with non-root privilege) try to offload. Only the first process that opens /dev/dri/card0 can pass DRM authentication. Only the first process to open /dev/dri/card0 has master privilege. “Root” or “master” privilege is needed to pass the DRM authentication. That is why all processes pass through when running with root privilege, but only one of them passes with non-root privilege. This is a known restriction for Linux*.



Possible workarounds Execute each process serially. Execute as root

You may see sporadic fails if multiple processes (with non-root privilege) try to offload. Only the first process that opens /dev/dri/card0 can pass DRM authentication. Only the first process to open /dev/dri/card0 has master privilege. “Root” or “master” privilege is needed to pass the DRM authentication. That is why all processes pass through when running with root privilege, but only one of them passes with non-root privilege. This is a known restriction for Linux*. Possible workarounds Other known limitations with offload to Intel® Graphics Technology In the offloaded code, the following are not allowed: Exception handling RTTI longjmp/setjmp VLA Variable parameter lists Virtual functions, function pointers, or other indirect calls or jumps Shared virtual memory Data structures containing pointers, such as arrays or structs Globals with pointer or reference type OpenMP* cilk_spawn or cilk_sync Intel® Cilk™ Plus reducers ANSI C runtime library calls (with the exception of SVML, math.h , and mathimf.h calls and a few others) 64-bit float and integer operations are inefficient



Intel® Cilk™ Plus Known Issues

Static linkage of the runtime is not supported



Static versions of the Intel® Cilk™ Plus library are not provided by design. Using -static-intel to link static libraries will generate an expected warning that the dynamic version of the of Intel® Cilk™ Plus library, libcilkrts.so, is linked.



$ icc -static-intel sample.c



icc: warning #10237: -lcilkrts linked in dynamically, static library not available



Alternatively, you can build the open source version of Intel Cilk Plus with a static runtime. See https://www.cilkplus.org/ for information on this implementation of Intel Cilk Plus. Any issues must be reported using the dynamic version of the Intel® Cilk™ Plus library.

SPEC CPUv6 runtime bus error seen on Red Hat Enterprise Linux* 6 with the Intel® IA-32 C++ compiler

If the SPEC CPUv6 benchmark (currently in development) is compiled with the Intel® IA-32 C++ compiler and then run with restricted stack and/or virtual memory limits using the ulimit command e.g., ulimit -s 2067152 -v 15000000, bus errors may be seen. Although this has only been observed on this benchmark, it may apply to other applications. A known workaround is to set these parameters to unlimited.

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Disclaimer and Legal Information

Optimization Notice Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to:

http://www.intel.com/products/processor%5Fnumber/

The Intel® C++ Compiler is provided under Intel’s End User License Agreement (EULA).

Please consult the licenses included in the distribution for details.

Intel, Intel logo, Pentium, Core, Atom, Iris, Intel® Xeon®, Intel® Xeon Phi, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.

* Other names and brands may be claimed as the property of others.

Copyright © 2019 Intel Corporation. All Rights Reserved.

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