Logical qubits operated by a substrate-independent application layer are based on the fault-tolerant QEC circuit implementing classical operations for the manipulation of virtual qubits and virtual gates. In turn, the virtual layer is based on the measurement and manipulation of physical qubits, implemented throughout our review by electron (hole) spin in CMOS silicon QDs. In this section, we discuss how the virtual layer is assessed from the physical layout by keeping the space resources at the maximum compactness.

Several virtual qubits have been proposed for QIP in Si.39 In single spin physical qubits, the two spin states of an electron in a QD are Zeeman-split by an external magnetic field and manipulated by means of microwave pulses.32, 40 A S-T virtual qubit architecture is based on two electron spins in a double QD and it does not require microwave pulses.31, 34 Fast operation is achieved through electrostatic control, provided that a strong magnetic field gradient is built across the double QD. Both architectures were implemented in silicon, demonstrating coherent qubit rotations at GHz frequencies, which is much faster than the coherence time predicted for such QD systems (T 2 *~µs).37 The integration of micron-sized resonant microwave antennas and micromagnets for every single qubit may be a major issue against the large-scale integration of single spin and S-T qubits, respectively, as state-of-the-art microwave line integration for qubit control ranges around 100 microns length scale of minimum feature size.41 Inhomogeneity in the magnetic field gradient and microwave interaction with nearest qubits may introduce strong variability in the qubit functional properties and consequently high error rates at the virtual layer. On the contrary, an architecture featuring all-electrical manipulation could take the best of the CMOS technology in terms of scalability and natural integration of the classical control circuitry. This requirement is met by using three electron spin qubits, whose dynamics is governed only by their exchange interaction. Originally, an architecture of this kind was proposed in systems of triple QDs, where the complete control of qubit states is obtained by tuning the inter-dot exchange couplings.33, 42 Later, a more compact version of the exchange-only triple electron spin virtual qubits has been proposed37, 43 and implemented36 by using only two QDs, one of which is doubly occupied. Both architecture are extensively reviewed in ref. 39. In contrast to previous architectures, only a small magnetic field is required during the virtual qubit initialization, provided externally.37, 42 Therefore, one may take this qubit as the most compact one with all-electrical control.

The exchange-only double quantum dot (DQD) qubit, sometimes referred to as a hybrid qubit for its intermediate nature between charge and spin qubits, employs three electron spins in a semiconductor DQD. The logical basis is defined in the spin subspace with total spin S = 1/2 and vertical component S z = −1/2. The logical states employed in the computation are:

$$\left| 0 \right\rangle \equiv \left| S \right\rangle \left| \downarrow \right\rangle ,\quad \left| 1 \right\rangle \equiv \sqrt {\frac{1}{3}} \left| {{T_0}} \right\rangle \left| \downarrow \right\rangle - \sqrt {\frac{2}{3}} \left| {{T_ - }} \right\rangle \left| \uparrow \right\rangle ,$$ (1)

Where \(\left| S \right\rangle \) and \(\left| T \right\rangle \) denote the S-T states of the doubly occupied dot, and \(\left| \uparrow \right\rangle \) and \(\left| \downarrow \right\rangle \) indicate the spin orientation of the single electron in the second dot. Such a virtual qubit is set in the \(\left| 0 \right\rangle \) state by operations at the physical layer by first polarizing the uncoupled spin in a magnetic field that is briefly switched on. Although no magnetic field has been used in single qubit experiments,36 this is required when dealing with more qubits in order to set a common reference for the spin orientation in different qubits. At operating temperatures of about 100 mK, a magnetic field intensity of 1.5 T is sufficient to impose the orientation of a single spin by means of spin-dependent tunneling from a reservoir to the QD.44 We also note that, although not necessary for the manipulation, a small magnetic field could even be beneficial in mitigating the effect of the low-frequency magnetic field fluctuations.45 The time load for this operation corresponds to the electron tunneling time, which can be set exceedingly small by lowering the tunnel barrier. This technique leads to an initialization of the singly occupied dot with fidelity currently of 95%, which is limited by thermal noise.35, 46 The doubly occupied dot is then initialized by driving the system in a configuration, where singlet is the ground state. The manipulation of the virtual qubit is performed by tuning the inter-dot effective exchange interaction. The effective Hamiltonian driving the system can be written in term of spin–spin interactions only.47 Such interactions are finely tuned by controlling the QD potential and the inter-dot electrostatic barrier, allowing fast and all-electrical manipulation of the qubit state. The first experimental work demonstrated coherent qubit rotations at GHz frequencies with fidelity of about 90%,36 albeit much better performances are theoretically predicted with optimized fabrication and pulse sequences.43, 45, 48 The final state is read out by means of charge sensing after collapsing the DQD system in either the (2,1) or the (1,2) charge state, corresponding to the \(\left| 0 \right\rangle \) and the \(\left| 1 \right\rangle \) logic state, respectively. Two-qubit gates could be performed similarly as in other qubit architectures by exploiting either the capacitive or the exchange coupling between two adjacent qubits45, 49,50,51 and so providing a universal set of virtual gates.38, 52 The exchange-only qubit has been realized in epitaxial Si–SiGe heterostructures and Rabi oscillations have been observed,36 with a T 2 * = 2 ns at nominal electron temperature of 150 mK and controlled at picosecond timescale. In principle, a complementary system based on holes53, 54 instead of electrons is also possible by using CMOS technology.55, 56 Holes in silicon carry the potential advantages of a considerably smaller hyperfine coupling with nuclei that cause decoherence,57, 58 and lack of the valley degeneracy that both causes interference phenomena59 and interleaved complicated valley sub-orbitals as happens for low-electron filling.60 Therefore, most of the following discussion holds for both electron and hole double QDs. On the contrary, a different reasoning applies to donor impurities in silicon.61, 62 In brief, single electron spin donor qubits exhibit very long coherence time of the order of seconds,44, 63 and the effectiveness of atomic resolution lithography based on scanning tunneling microscope64 is progressively approaching serial implantation.65 The less accurate single ion implantation66,67,68 method could achieve sufficient precision for some architecture such as a surface code implementation based on a two-dimensional array of distant donors,69 which tolerates deviation of up to 11 nm from the ideal lattice position. However, the complexity of the serial design of devices involving either individual donors with single spins for qubits with microwave control or pair of donors with two or three electrons bound to donors controlled by gates that depends on a relatively high number of currently unaddressed assumptions including yield of implantation and activation of all the donor sites, control of inter-donor distance at single lattice precision, global or individual microwave control, S-T and exchange-only three spin qubits, CMOS mask design on top of silicon overgrowth on the donor layer. The surface code implementation proposal based on a spin-probe controlled two-dimensional array of donors69 considers a distance of about 400 nm between neighboring donors, which represents an intermediate scale between QDs and superconductor qubits. Regardless of the chosen physical implementation, besides the desirable improvements concerning the single qubit specifications to achieve fault-tolerant fidelity for one-qubit and two-qubit gates, the practical demonstration of two-qubit devices and more complex circuits involves additional issues39, 45: the need for long range quantum communication, QEC, and the demanding requirements related to the massive integration of classical control electronics at the quantum chip level. In the following, we focus on the double QD design for hybrid qubits, which could also be naturally adapted to charge qubits51 and S-T architectures43 if the issue of adding a local magnetic field gradient can be addressed with no cost in terms of additional space requirements.

As one is interested in the large-scale fabrication of quantum circuits based on a silicon platform, the CMOS implementation of the hybrid qubit architecture is considered, toward the identification of the scaling law of computational power per unit surface area as a function of the technology node. Universal QIP can be addressed by different approaches. First, we consider the universal set of single virtual qubit rotations and virtual controlled NOT (CNOT) logic ports38 for a Steane code [7,1,3], so we adopt the definition of the three physical building blocks,70 namely, a data qubit (D) capable of one-qubit and two-qubit logic gates and two types of communication qubits, i.e., the chain module (C) and the T module (T). A schematic representation of these devices is reported in Fig. 1.

Fig. 1 The three physical building blocks constituting the virtual layer of the qubits based on exchange-only DQD qubits for the implementation of the Steane code. Schematic device mask is provided for each module together with its symbolic representation utilized in Fig. 2. Greek letters denote virtual qubits storable inside the module, whereas arrows indicate the available quantum connections to neighboring virtual qubits. Top left—Data virtual qubit (d) for one-qubit and two-qubit virtual gates, e.g., the Hadamard (h) and the CNOT. Labeled plunger gates (orange) control the chemical potentials of the four QDs defining the two qubits. Barrier gates (gray) control the inter-QD tunnel coupling. Shaded areas indicate the charge sensors (SET) and the electronic reservoirs (RES) of virtual qubits 1 and 2. Black arrows denote the critical feature sizes defined in the main text. Module sizes are calculated along the directions indicated by the red arrows. Top right—Chain module (c) for quantum communication through SWAP gates. c Bottom—T module (t). The module supports quantum communication along the silicon nanowire direction (in this case vertically) analogously to module (c). In addition, a horizontal virtual qubit chain can be connected on the left of such device to build up a T-shaped crossing with a vertical channel. Blue areas denote the space for metal interconnections between the active area over the Si nanowire and vias at the module boundary. Only plunger gates interconnections (orange) are depicted for clarity. Metal interconnections are disposed so that the space for surrounding (c) modules (depicted shaded on the left and top of t module) is taken into account Full size image

The module D incorporates two qubits (i.e., four QDs) and the corresponding individual electronic reservoir and single electron transistor (SET) for independent initialization and readout. To assess the one-qubit and two-qubit gates mechanisms, as well as measurement readout at the physical layer, the system is equipped with a reservoir consisting of high electron density region with a quasi-continuous density of states that is controlled by an accumulation gate to provide electrons required for qubit manipulation during the initialization procedure. The SET is used as a single charge sensor to monitor the qubit charge state during readout. The coherent transfer of quantum information between distant qubits is a very challenging task, which could in principle be assessed through the sequential repetition of SWAP logic gates between adjacent qubits, as proposed in ref. 70. The module C is specifically designed for quantum communication following this procedure, with no need for initialization and readout. To this purpose, the use of different techniques, such as the coherent transfer by adiabatic passage (CTAP) and teleportation, will be also considered later, as well as the impact of electron loss during the qubit transportation. Finally, the module T is a modified version of the latter to connect perpendicular quantum communication lines and create two-dimensional arrays of qubits. Each device is developed within the same design rules for a given technology node and instantiated as a conventional component in the design of large arrays of identical qubits independently accessible by classical electronics (for more extensive review on the interface between the physical qubits and the classical electronic layer, see ref. 71). The physical size of the three building blocks constituting the virtual layer is then calculated as a function of the main critical sizes such as the pitch of metal interconnections and the width of Si islands. For example, module C height is constrained by the silicon wire width and by the four vias on each side. The sizes of the other devices are determined analogously in terms of the critical pitches. The expressions reported in Table 1 are defined only by the device layout, while being totally independent of the technology node. Δ G and Δ IG are the contacted gate pitch and the interconnect pitch, respectively, w Si is the width of the silicon wires hosting the dots, l HDD is the length of the highly doped drain, and l SU is an undoped silicon buffer to avoid unintentional doping of the device active region.

Table 1 Physical size of the three building blocks for QIP, of a logical qubit and of a qubyte as a function of the main critical sizes independent of the technological node Full size table

As an alternative option, we examine the implementation of surface codes based on nearest neighbor qubit lattices, and having marked differences from the device layout envisaged for the Steane code. Surface codes appear to be promising candidates for the implementation of fault-tolerant quantum circuits with error thresholds in the 10−2 range. Notably, a possible layout was proposed for the implementation of both QEC and leakage correction protocols by surface codes based on S-T qubits realized in semiconductor double QDs.72 By exploiting the formal and geometrical analogy between the S-T qubit and the hybrid qubit here discussed (both based on semiconductor double QDs hosting electron spins), it is possible to evaluate the size of the consequent logical qubit for surface codes20 as the two cases may be treated with no fundamental difference (David Di Vincenzo and Hendrik Bluhm, private communication), with the exception of the highest operation speed for the hybrid qubit, which is the case considered in this review.

A layout for the implementation of the surface code on a nearest neighbor lattice of physical qubits is depicted in Fig. 2 (fourth column), in analogy with ref. 72. The asymmetry of the hybrid qubit does not constitute a difficulty as the four hybrid qubits can be arranged in an alternated configuration block (top of fourth column of Fig. 2). The surface code consists of a two-dimensional lattice of data (red) and ancillae (green and yellow) qubits to implement Z-stabilizer and X-stabilizer for QEC by classical operations. The physical qubit area is estimated accordingly as the area of such block divided by 4, i.e., (8 Δ G )2/4. Nearest neighbor connections impose stringent proximity of the physical qubits, which from one side lead to a minimum footprint, but on the other raises potential difficulties in their control to address the physical operations to achieve an operating virtual layer. The SET-based charge sensors proposed for the Steane code may be replaced by rf-reflectometry sensors fully integrated within the control gates.73, 74 It is worth mentioning that such compact layout comes at the expense of considerably higher complexity at the classical control layer, discussed later. The classical circuitry architecture is supposed to be able to deliver rf pulses of arbitrary shapes for qubit manipulation as well as readout, dealing with serious issues of high-density routing and cross-talk behavior.

Fig. 2 Representation of QIP at different scales of integration according to the different layers of implementation. The first column represents the different scales of integration with symbolic diagrams. The second one is a functional representation of the blocks required to execute the corresponding operations. The third column provides the physical layer implementation by the Steane code based on the modules d, c, and t, while the fourth column by the surface code. Each oval indicates a double QD qubit. In panel h, the representation of the 2D nearest neighbor array shows the virtual data qubits in red for the surface code and ancillae for the x (yellow) and z (green) stabilizer measurements. The four rows represent four scales of integration: the virtual qubits by their physical layout, the QEC scale for logical qubits, the logical layer scale, and finally the quantum chip scale enabling quantum algorithms such as Shor’s factoring and quantum simulations. The logical layer scale assesses fault-tolerant computation from few logical qubits and it has been used to calculate the area of a single logical qubit of the Steane code by including interconnections Full size image

While in the first experimental works on single qubit devices this has not been a blocking point, the complexity increases in a large-scale computer. The replication of the same wiring strategy is not a viable solution for two reasons: on the one hand, the extremely dense topology of physical qubit arrays generates serious routing problems for the interconnections on the quantum chip; on the other hand, interfacing billions of control lines with classical electronics on a different substrate or package is not realistic with current and foreseeable back-end technologies.

It is widespread opinion that the classical electronics will be split into several stages between the quantum chip and room temperature electronics (see Fig. 3a) to optimize the system thermal management. A classical integrated circuit directly attached on the quantum chip by conventional flip-chip technology may provide the low-level interface with the quantum layer. An interposer with superconducting through silicon vias could be effective in limiting the thermal load arising from classical electronics. Nonetheless, the partial integration of control electronics within the quantum chip level is an option that should be considered to alleviate routing issues at the quantum chip level, to make the interface with higher-level classical electronics easier, and to improve its performance by reducing the distance from the qubits.71

Fig. 3 Classical circuitry for qubit control and electrical signals typically used to perform operation and read out of three electron spin qubits.36, 75 a Generic fault-tolerant interrogation correction loop, comprising both an analog front-end and a digital back-end. b Energy efficiency of state-of-the-art room-temperature CMOS ADCs and cryogenic CMOS ADCs.76 The energy spent by an ADC for a single conversion, i.e., E C = P/f s, where P is the power consumption and f s the sampling frequency, strongly depends on its resolution, i.e., the number of effective bits N. Consequently, ADC energy efficiency is quantified by the Schreier Figure-of-Merit (FOMs = 10 log10 [2N f s /(2P)]) for high-resolution thermal-noise-limited ADCs and by the Walden FOM (FOMw = P/f s /2N) for low-resolution ADCs. In terms of those FOMs, the energy efficiency of existing cryogenic ADCs is 200× worse than state-of-the-art room temperature ADCs (FOMs = 175 dB, FOMw = 5 fJ/conversion step), due to the use of past node technologies and the unavailability of reliable cryogenic models for CMOS devices. c, d Voltage applied to the qubit gates to perform single-qubit rotations; typical waveform parameters: t p1 ~5–20 ns, t p1 , t p2 , t p3 ~100–500 ps, microwave burst frequency ~10–12 GHz, pulse rise time (10–90%) ~80 ps. e Typical current waveform read out at quantum point contact (QPC) to detect presence of electron in neighboring QD; typical waveform parameters: t QPC ~10 ns to 100 μs, A QPC ~200 pA; QPC resistance ~25 kΩ Full size image

Starting from both the three building blocks D, C, and T for the Steane code [7,1,3], and the double dot qubit for the surface code, respectively, logical qubits and circuits for implementation of quantum algorithms can be designed. Figure 2 shows the symbolic notation, functional and physical representations of QIP at different scales of integration of the two architectures, from the virtual qubit to QEC circuit, to logical gate and application layer fault-tolerant quantum chip scale, respectively.

By following the typical arrangements of virtual qubits proposed for scaling to a logical qubit and as a further step to H-tree structures for concatenated codes,77, 78 the first level of integration (second row in Fig. 2) for the Steane code is achieved by connecting a relatively small number (~20) of virtual qubits (device D) by means of quantum channels (modules C and T) to create the physical background for fault-tolerant quantum computing. The corresponding physical device is sketched at the third column by means of green blocks (communication modules, namely, C and T) and red boxes (data qubit D) following the symbolic representation defined in Fig. 1. This structure defines the smallest system of virtual qubits connected to a line of bidirectional quantum communication with the scope to store quantum information and correct potential errors. A number of seven virtual qubits is needed to define a logical qubit according to the Steane’s code, and about 20 virtual qubits suffice to correct potential X and Z errors on a logical qubit according to most quantum codes, e.g., the Shor’s and the Steane’s ones.9 As long as the error rate is lower than the code error threshold, arbitrary errors occurring at the individual physical qubits can be detected and corrected in the framework of a logical qubit by employing few additional qubits as ancillae. We note that previous theoretical works identified several strategies to obtain gate fidelity approaching 99.999%.43, 70 This may be good enough to enable QEC by means of the Steane code, which could deal with an error threshold in the range 10−6–10−4 depending on the geometry.9, 71 So, if the error rate is a factor of x better than threshold, encoding yields a final error rate approximately a factor of x 2 below threshold. Further improvement can be achieved similarly by concatenation.9 At any rate, we remark that only a deep understanding of the noise model applicable to the hybrid qubit will definitely set the relevant specifications for gate fidelity to be compatible with a specific QEC scheme.9, 70 Such logical qubit therefore enables QEC and it is the functional building block for error-correcting quantum memory and fault-tolerant QIP. Differently, the implementation of surface code in the fourth column of Fig. 2 exploits the physical qubits in a two-dimensional nearest neighbor array so that the data virtual qubits (red ovals) are interleaved with ancillae for the X (yellow) and Z (green) stabilizer measurements.

The next length scale (third row) requires interconnections between multiple logical qubits to perform small-scale algorithms (in the first column, the Quantum Fourier Transform is given as an example) in a fault-tolerant manner. At such level, in order to estimate the effective area occupied by a single logical qubit by including the space needed to connect the qubits in some arrangements, for example by an H-tree structure,77, 78 it is useful for the Steane code to conventionally define the logical qubyte or quantum byte by eight connected logical qubits, as a reminiscence of classical information processing. The qubyte allows calculating the minimum effective area of a single logical qubit by dividing by 8 its area. Such operation is not needed for the surface code architecture, which employs contiguous logical qubits. An example of operation carried at this level is provided by Quantum Fourier Transform, a key block of more complex algorithms like Shor’s factoring. Finally, many logical qubit blocks are connected (fourth row) to allow control at the application layer and to implement quantum algorithms, e.g., Grover’s, Shor’s, and quantum simulation algorithms applied to problems where classical computation is unpractical.79

The physical size function of a logical qubit and of a logical qubyte, conventionally defined above to calculate the maximum density of the logical qubits by including interconnections, are reported in last two rows in Table 1. About the footprint of classical control circuits, the Steane code layout carries some unused area, which reaches about 23% in the logical qubit and 43% in the qubyte mask, that could be employed for classical electronics and low-level interconnections.

The surface code layout is more compact and so much more challenging to this regard, since even elementary circuits cannot fit into the small distance between physical qubits (the physical qubit pitch is of the same size order of the qubit itself as well as of a typical CMOS transistor). While increasing this feature size would be detrimental for the surface code operation and performance, a viable alternative could be to conceive a quantum processor architecture based on separated blocks of physical qubits interleaved by blocks of classical control circuits, as proposed in ref. 71. Each block, corresponding to one or few logical qubits, is connected to the neighbors by long-range quantum communication channels. Part of these blocks could be also reserved as ancillae factories to the high-throughput generation and purification of high-fidelity ancillae and cat states, which accounts for most of the resources involved in Shor’s algorithm.

However, the operation of two-qubit gates within this topology and the effectiveness of such long-range couplers is still to be carefully evaluated in terms of fidelity and of required transfer bandwidth: the coherent transfer of a realistic logical qubit (d≈20–30) means the coherent transfer of d 2≈400–900 physical qubits over few tens of μm on such a single track.

Anyway, the footprint of integrating classical control circuits obviously depends on the complexity of the functionality that is required within the quantum layer and this is a key point that the next-generation quantum engineer will have to deal with. This falls well beyond the scope of this review: we only note that although we did not estimate the footprint of control circuits, we obtain an estimate of the maximum density, i.e., a higher bound of quantum information. We will show how the evaluation of such figure of merit across different technology nodes, together with practical considerations about the hybrid qubit architecture, can give useful indications to the development of quantum computers.