The U.S. Defense Advanced Research Projects Agency (DARPA) announced the first grants for its Electronic Resurgence Initiative (ERI). The initial round, which will expand to $1.5 billion over five years, covers topics ranging from automating EDA to optimizing chips for SDR to improving NVM performance. Of particular interest is a project called POSH, (posh open source hardware), which intends to create a Linux-based platform and ecosystem for designing and verifying open source IP hardware blocks for next-generation system-on-chips.

The first funding recipients were announced at DARPA’s ERI Summit this week in San Francisco. As reported in IEEE Spectrum, the recipients are working out of R&D labs at major U.S. universities and research institutes, as well as companies like Cadence, IBM, Intel, Nvidia, and Qualcomm.

Most of the projects are intended to accelerate the development of complex, highly customized SoCs. ERI is motivated by two trends in chip design. First, as Moore’s Law roadmap slows to a crawl, SoC designers are depending less on CPUs and more on a growing profusion of GPUs, FPGAs, neural chips, and other co-processors, thereby adding to complexity. Second, we’re seeing a greater diversity of applications ranging from cloud-based AI to software defined networking to the Internet of Things. Such divergent applications often require highly divergent mixes of processors, including novel chips like neural net accelerators.

DARPA envisions the tech world moving toward a wider variety of SoCs with different mixes of IP blocks, including highly customized SoCs for specific applications. With today’s semiconductor design tools, however, such a scenario would bog down in spiraling costs and delays. ERI plans to speed things up.

Here are some brief summaries of the projects followed by a closer look at POSH:

IDEA — This EDA project is based primarily on work by David White at Cadence, which received $24.1 million of the total IDEA funding. The immediate goal is to create a layout generator that would enable users with even limited electronic design expertise to complete the physical design of electronic hardware such as a single board computer within 24 hours. A larger goal is to enable the automated EDA system to capture the expertise of designers using it.

— This EDA project is based primarily on work by David White at Cadence, which received $24.1 million of the total IDEA funding. The immediate goal is to create a layout generator that would enable users with even limited electronic design expertise to complete the physical design of electronic hardware such as a single board computer within 24 hours. A larger goal is to enable the automated EDA system to capture the expertise of designers using it. Software Defined Hardware (SDH) — SDH aims to develop hardware and software that can be reconfigured in real time based on the kind of data being processed. The goal is to design chips that can reconfigure their workload in a matter of milliseconds. Stephen Keckler at Nvidia is leading the funding at $22.7 million.

— SDH aims to develop hardware and software that can be reconfigured in real time based on the kind of data being processed. The goal is to design chips that can reconfigure their workload in a matter of milliseconds. Stephen Keckler at Nvidia is leading the funding at $22.7 million. Domain-Specific System on Chip (DSSoC) — Like the closely related SDH project, the DSSoC project is inspired by software defined radio (SDR). The project is working with the GNU Radio Foundation to look at the needs of SDR developers as the starting point for developing an ideal SDR SoC.

— Like the closely related SDH project, the DSSoC project is inspired by software defined radio (SDR). The project is working with the GNU Radio Foundation to look at the needs of SDR developers as the starting point for developing an ideal SDR SoC. 3DSoC — This semiconductor materials and integration project is based largely on MIT research from Max Shulaker, who received $61 million. FRANC is attempting to grow multiple layers of interconnected circuitry atop a CMOS base to prove that a monolithic 3D system using a more affordable 90nm process can compete with CPUs with more advanced processes.

— This semiconductor materials and integration project is based largely on MIT research from Max Shulaker, who received $61 million. FRANC is attempting to grow multiple layers of interconnected circuitry atop a CMOS base to prove that a monolithic 3D system using a more affordable 90nm process can compete with CPUs with more advanced processes. Foundations Required for Novel Compute (FRANC) — FRANC is looking to improve the performance of NVM memories such as embedded MRAM with a goal of enabling “emerging memory-centric computing architectures to overcome the memory bottleneck presented in current von Neumann computing.”

POSH boosts open hardware with verification

The POSH project received over $35 million in funding spread out among a dozen researchers. The biggest grants, ranging from about $6 to $7 million went to Eric Keiter (Sandia National Labs), Alex Rabinovitch (Synopsis), Tony Levi, and Clark Barrett (Stanford and SiFive).

As detailed in a July 18 interview in IEEE Spectrum with DARPA ERI director Bill Chappell, proprietary licensing can slow down development, especially when it comes to building complex, highly customized SoCs. If SoC designers could cherry pick verified, open source hardware blocks with the same ease that software developers can download software from GitHub today, it could significantly reduce development time and cost. In addition, open source can speed and improve hardware testing, which can be time-consuming when limited to engineers working for a single chipmaker.

POSH is not intended as a new open source processor architecture such as RISC-V. DARPA has helped fund RISC-V, and as noted, POSH funding recipient Barrett is part of the leadership team at RISC-V chip leader SiFive.

POSH is defined as “an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs.” In some ways, POSH is the hardware equivalent of projects such as Linaro and Yocto, which verify, package, and update standardized software components for use by open source developers. As Chappell put it in the IEEE interview, POSH intends to “create a foundation of building blocks where we have full understanding and analysis capability as deep as we want to go to understand how these blocks are going to work.”

The ERI funding announcement quotes POSH and IDEA project leader Andreas Olofsson, as saying: “Through POSH, we hope to eliminate the need to start from scratch with every new design, creating a verified foundation to build from while providing deeper assurance to users based on the open source inspection process.”

POSH is focusing primarily on streamlining and unifying the verification process, which along with design, is by far a leading cost of SoC design. Currently, there are very few high-quality, verified hardware IP blocks that are openly available, and it’s difficult to tell those apart from the blocks that aren’t.

“You’re not going to bet $100 [million] to $200 million on a block that was maybe built by a university or, even if it was from another industrial location, [if] you don’t really know the quality of it,” Chappell told IEEE Spectrum. “So you have to have a methodology to understand how good something is at a deep level before it’s used.”

According to Chappell, open source hardware is finally starting to take off because of the increasing abstraction of the hardware design. “It gets closer to the software community’s mentality,” he said.

DARPA ERI’s slidedeck (the POSH section starts at page 49) suggests Linux as the foundation for the POSH IP block development and verification platform. It also details the following goals:

TA-1: Hardware Assurance Technology — Development of hardware assurance technology appropriate for signoff quality validation of deeply hierarchical analog and digital circuits of unknown origin. Hardware assurance technology would provide increasingly high levels assurance for formal analysis, simulation, and emulation and prototypes.

Hardware Assurance Technology — Development of hardware assurance technology appropriate for signoff quality validation of deeply hierarchical analog and digital circuits of unknown origin. Hardware assurance technology would provide increasingly high levels assurance for formal analysis, simulation, and emulation and prototypes. TA-2: Open Source Hardware Technology — Development of design methods, standards, and critical IP components needed to kick-start a viable open source SoC eco-system. IP blocks would include digital blocks such as CPU, GPU, FPGA, media codecs, encryption accelerators, and controllers for memory, Ethernet, PCIe, USB 3.0, MIPI-CSI, HDMI, SATA, CAN, and more. Analog blocks might include PHYs, PLL and DLL, ADCs, DACs, regulators. and monitor circuits.

Open Source Hardware Technology — Development of design methods, standards, and critical IP components needed to kick-start a viable open source SoC eco-system. IP blocks would include digital blocks such as CPU, GPU, FPGA, media codecs, encryption accelerators, and controllers for memory, Ethernet, PCIe, USB 3.0, MIPI-CSI, HDMI, SATA, CAN, and more. Analog blocks might include PHYs, PLL and DLL, ADCs, DACs, regulators. and monitor circuits. TA-3: Open Source System-On-Chip Demonstration — Demonstration of open source hardware viability through the design of a state of the art open source System-On-Chip.

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