Extreme ultraviolet (EUV) lithography is moving closer to realization, but several problems involving scanner uptime, photoresists and pellicles need to be resolved before this long-overdue technology is put into full production.

Intel, Samsung and TSMC are hoping to insert EUV into production at 7nm and/or 5nm. While the remaining issues don’t necessarily pre-empt using EUV, they do affect the rollout schedule. On the bright side, there are some new technologies for EUV, including actinic pattern mask inspection and multi-beam mask writers.

Resists, which are light-sensitive polymers used to create patterns, remain the top challenge in EUV. There are others, as well, including mask defects and pellicles. None of these is new, but progress in solving them has been slow. As a result, decisions about exactly when to insert EUV remain cloudy.

“A lot of people were saying that EUV would happen in manufacturing by the end of this year,” said Harry Levinson, principal at HJL Lithography, a consulting firm. “Now, you are saying maybe in the second quarter of next year, so there is a push-out.”

EUV may get pushed out even further into next year. Among the ongoing challenges:

EUV scanner uptimes remain in the 70% to 80% range. Uptime, a measure of the amount of time that a system is in operation, should be close to 100%.

EUV mask yields are still low, averaging about 72% in 2018, compared to 64.3% in the prior period, according to a survey from the eBeam Initiative.

An EUV pellicle, which could help with yields, is still not ready for production. A pellicle is a thin, transparent membrane that covers a photomask and prevents particles from falling on the mask.

Chipmakers want an EUV pellicle because if a particle lands on an EUV mask, the scanner may print an unwanted defect on a wafer. A single defect can be a disaster for a device.

ASML has been developing an EUV pellicle. “People are using it, but it’s more to just get up the learning curve. It’s just not ready,” Levinson said.

Not all parts of a device require a pellicle, however. So even without it, chipmakers could use EUV for select parts of the device at 7nm, such as contacts and vias. But that requires extra inspection steps, which impact cost and cycle time.

The industry has poured billions of dollars into EUV development so far, and several customers still want it because it’s becoming more difficult to pattern the tiny features using today’s lithographic techniques at 7nm and beyond. But how quickly they will adopt EUV could vary. Intel, for example, has said it will use EUV when it’s ready. In contrast, TSMC and Samsung hope to insert EUV at 7nm, even if certain pieces aren’t ready.

Still, several components must come together before chipmakers can insert it. These include the scanner, power source, resists and masks.

To help the industry get ahead of the curve, Semiconductor Engineering has taken a look at the status of EUV and its various components.

Scanner/resist issues

For some time, ASML has been shipping its first production EUV scanner, the NXE:3400B. The 13.5nm wavelength tool has a 13nm resolution. In EUV, a power source converts plasma into light at 13.5nm wavelengths. Then, the light bounces off a complex scheme of 10 multi-layer mirrors.



Fig. 1: The complexity of EUV. Source: ASML

A big problem in the past involved the EUV power source, which didn’t generate enough power. That, in turn, impacted the throughput of the system. ASML now is shipping a 246-watt EUV power source, enabling a throughput of 125 wafers per hour (wph). This meets the high-volume manufacturing (HVM) target levels.

But that doesn’t necessarily mean EUV systems will maintain those throughput levels. Today’s 193nm scanners can run non-stop at 250 wph. However, EUV uptimes hover around 70% to 80%. An EUV scanner is a complex machine with several moving parts and the system is prone to stoppages for various reasons.

“The key challenge is the availability. We need to go beyond 90% for these systems to meet the high-volume requirements,” said Marcel Mastenbroek, product manager at ASML. ASML hopes to improve the availability to 88% by year’s end.

There are other issues, such as EUV resists and variations, called stochastics. “EUV photoresists have progressed, albeit slowly, toward improving the tradeoffs between resolution, throughput and stochastic defects,” said Rich Wise, managing technical director at Lam Research. “Today’s resists used for the most aggressive pitches require 2x or more of the HVM targeted dose to meet HVM levels of defectivity. The window of opportunity to overcome this challenge is quickly closing. Not only resist suppliers but the entire patterning ecosystem is working on minimizing this tradeoff for customers.

“This problem is too fundamental to rely solely on any single part of the patterning ecosystem, and there is a lot of innovation in this area in developing new holistic solutions between resists, lithography, deposition, and etch,” Wise said. “At less aggressive pitches the lithography resolution requirement is relaxed, and the stochastics performance at HVM doses is much improved with these holistic solutions. In cases where the resolution requirements can be made less stringent, EUV will be required to mitigate issues such as intra-level mask overlay and cycle time from multiple exposures.”

Chipmakers have other issues to worry about. “While it has been widely published that EUV stochastic driven defects are decreased when a higher dose is used, using a lower dose would enable higher scanner throughput. Challenges remain when considering high-volume manufacturing due to the ecosystem, but also process capability that includes local CD variation, edge roughness and mask selectivity,” said Sophie Thibaut, senior etch process development engineer at TEL, in a recent paper.

Despite these and other issues, it’s possible to put EUV in production, even without a pellicle. “If you are doing contact and via layers, they will be fine without a pellicle. But you need to do checks. Doing metal layers will be the painful one if you don’t have a pellicle,” HJL’s Levinson said.

By checks, Levinson is referring to print checks, which are additional and time-consuming mask inspection steps that must be done in the wafer fab. “We can make good EUV masks. They will make yielding, high-complexity parts. Keeping them clean is the challenge without pellicles,” Levinson said.

Of course, some customers may opt to not use EUV at 7nm. Instead, they will continue to ramp up 7nm using traditional 193nm lithography and multiple patterning. “There are maybe some customers who are saying: ‘I don’t want that now,’ ” he said.

Making EUV masks

Besides the scanner and resists, the EUV mask infrastructure is also important. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scanner, which projects light through the mask. That, in turn, is used to pattern images on a wafer.

In mask production, the first step is to create a mask blank. Made by a mask blank vendor, the blank serves as the base structure of a mask. Today’s optical mask blanks consist of an opaque layer of chrome on a glass substrate.

In contrast, an EUV mask blank consists of 40 to 50 alternating layers of silicon and molybdenum on top of a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on a tantalum material.

The multi-layer stack acts like a mirror. In a scanner, the structure reflects EUV light at 13.5nm wavelengths, enabling patterns on the wafer.

The EUV mask blank is where the issues start. “Defectivity challenges begin with the EUV blank, which is significantly more complex to build than an optical blank, given more stringent requirements for flatness, defectivity and absorber film quality,” said James Westphal, director of marketing at KLA-Tencor.

The blank has other issues. “There are certain properties of these materials that we have to worry about,” said Vibhu Jindal, manager of new markets and alliances at Applied Materials. “For the backside, you have to worry about resistivity, hardness and optical density. The same thing is true with the substrate when it comes to defectivity for the roughness, and henceforth, for the mirror cap and the absorber.”

Regardless, it’s important to have defect-free blanks. But at times, the production process creates defects, such as particulates, pits and bumps, in the blank. “Any particles added during any of these steps have the potential to create height deviation in the stack, which can be the source of phase defects. In addition, at the substrate level, any irregularities (bumps or pits) in the substrate can propagate through the film stack to become phase defects,” KLA-Tencor’s Westphal said.

There are two types of defects in EUV blanks—amplitude and phase. Amplitude defects are surface particles and pits, which can cause contrast changes. The bigger problem, though, involves phase defects, which are bumps and pits that are buried in the stack. These can cause a phase change of the reflected wave in the system.

Mask blank vendors have reduced the number of defects in the blank to single-digit figures, but they can still impact image quality in the scanner. Mask blank inspection systems are used to find defects using. Lasertec and KLA-Tencor sell optical-based inspection tools that are used for this. Lasertec offers an actinic system.

Optical uses laser light to find defects. Actinic inspection, meanwhile, uses the same 13.5nm wavelength as EUV and can supposedly find more defects than optical.

“To detect phase defects, a 13.5nm wavelength light source is required,” said Hiroshi Asai, general manager of corporate planning at Lasertec. “For amplitude defect detection, conventional optical mask blank inspection tools can work. EUV mask blank suppliers will use actinic inspection in combination with optical mask blank inspection tools.

Once the blank is made, meanwhile, it is shipped to the photomask vendor, where the mask is made. To make a mask, the blank is patterned, etched, repaired and inspected. Following that, a pellicle is mounted on the mask.



Fig. 2: Fabrication of EUV mask. Source: Sematech

In mask making, the key step is patterning. A system called an e-beam mask writer creates or writes patterns on the mask based on a given IC design.

The most common system is a single-beam e-beam tool, based on variable shape beam (VSB) technology. In operation, the electrons from the VSB tool are fired in shots, which pattern the mask in rectangular-like shapes.

For years, the write times for VSB tools were acceptable for optical masks. Write times determine how fast an e-beam can write a mask layer.

At advanced nodes, though, optical masks are becoming more complex and the write times are increasing. “For dense layers, the write times can go to 30 hours or even higher. At 60 hours, the write times are no longer practical,” said Elmar Platzgummer, chief executive of IMS.

So, VSB-based mask writer tools are barely keeping with the requirements for complex optical masks, prompting the industry to look at a different technology—multi-beam mask writers.

For example, IMS’ multi-beam mask writer utilizes 262,000 tiny beamlets to speed up the write times for both optical and EUV reticles. The write times for multi-beam tools are constant and take 12 hours or less for all masks.

EUV mask writing, meanwhile, is also challenging. For contacts/vias, the feature size is expected to be 70nm on an EUV mask at 7nm and 55nm at 5nm. In comparison, the feature size is 250nm for an optical mask at 7nm.

VSB tools can pattern EUV masks, but the write times could explode. “For R&D, you can invest more in write times or go with simple structures. Then, you can use VSB,” Platzgummer said. “But for a production, full-layer EUV mask, multi-beam is a must.”

Multi-beam is required for other reasons. “EUV masks need to print at much smaller sizes on the mask than 193i masks. And so EUV masks have to be more precise,” said Aki Fujimura, chief executive of D2S. “Both of these translate to EUV masks needing slower, more accurate resists for exposure. This increases the mask write times. The mask write times for slower resists are faster on multi-beam mask writers than on VSB mask writers. Therefore, EUV masks tend to want to be written on multi-beam mask writers. Then, for certain applications that require non axis-parallel orthogonal features or 45 degree features, VSB writing also becomes prohibitive for EUV. Because EUV can see the 90-degree jogs much better than 193i, the VSB shot count increases quickly, particularly with single patterning. This is another reason why multi-beam mask writers are needed for EUV lithography.”

After the mask is patterned, meanwhile, it is inspected for defects and finding them is challenging. “The challenge for defectivity on EUV reticles is the sensitivity requirements have become tighter on smaller, more complex features,” KLA-Tencor’s Westphal said.

“Today, EUV mask inspection challenges focus on reticle quality,” Westphal said. “Reticle quality is directly linked to wafer yield. When we talk about reticle quality, we refer to two aspects: (1) defectivity–a reticle defect will be replicated on every die on a wafer as a pattern defect, thus directly impacting device yield; and (2) parametric uniformity, such as critical-dimension uniformity and pattern placement error.”

For EUV pattern mask inspection, there are three options–actinic, e-beam, and optical. Using a 193nm light source, optical is the dominate technology for both optical and EUV masks.

E-beam inspection, meanwhile, has sensitivities down to 3nm or lower, but it’s slow in terms of throughputs.

Optical also has some limitations. “The smallest pattern pitch is 40nm half-pitch,” said Hiroki Miyai from Lasertec. So, optical inspection has sensitivities down to 20nm or so.

In a major breakthrough, Lasertec recently unveiled an actinic pattern mask inspection tool. Using a 13.5nm wavelength, the system has demonstrated sensitivities from 23nm to 17nm. This system is different than its actinic mask blank inspection tool.

Actinic is important for other reasons. Generally, at the latter stages of the mask production process, a pellicle is mounted on the mask and the reticle is inspected for defects.

Today’s EUV pellicles are based on a polysilicon material. Because it uses a 13.5nm wavelength, Lasertec’s actinic tool can inspect the mask through an EUV pellicle, making the inspection process less complicated.

In contrast, today’s optical and e-beam tools can’t inspect EUV masks with the pellicle on top. The polysilicon-based material is opaque at 193nm or other wavelengths.

So for this, ASML has developed a retractable pellicle. In operation, when it’s time to inspect a mask, the EUV pellicle is automatically raised and a tool inspects the mask. Once that task is completed, the pellicle is automatically lowered and re-attached to the EUV mask.

Pellicle woes

Today, though, this is a moot point, as the current EUV pellicle isn’t ready for production. For some time, ASML, the sole supplier of EUV pellicles, has been developing a polysilicon-based pellicle that’s 50nm thick.

EUV pellicles must meet various requirements in three categories—transmission rates, thermal loads, and productivity.

For production, chipmakers want a pellicle that can transmit light through the membrane at a transmission rate of 90%. At these rates, the EUV scanner meets the desired throughputs in the fab.

Then, when EUV light hits the pellicle, the structure must withstand the heat from a 250-watt source. That source generates about 5 watts per square centimeter of heat on a pellicle, translating to roughly 686°C.

ASML’s goal is to have an EUV pellicle with an 88% transmission rate and above that can withstand a 300-watt source. Each pellicle must process 10,000 wafers before it is replaced.

Today, though, ASML’s pellicle has a transmission rate of 83%. The pellicle can support a 250-watt source, but it must be replaced after processing 3,000 wafers.

“As you can see, we have a gap with respect to the HVM requirements, so we are working toward a solution,” said Guido Salmaso, a product engineer at ASML. “To fill the gaps, we have to use new materials. The only layer that will stay the same is the core, which is polysilicon. We will have to use new materials for the cap layers. We will have to use new materials for the metal.”

Basically, a pellicle is a thin, multi-layer structure. The core structure is a polysilicon material with a metal-oxide capping layer.

ASML is developing a new polysilicon-based pellicle using a different capping layer. The target is a 90% transmission rate. “That’s a target we aim to demonstrate in the year 2019,” Salmaso said.

More steps

Once the mask has been developed, it is shipped to the fab and placed on the scanner for imaging.

As stated, chipmakers will initially insert EUV for contacts and vias at 7nm. For this, they could go with or without a pellicle.

If there is no pellicle, chipmakers must perform print checks in the fab. The idea is to take the mask, insert it into an EUV scanner and then print some wafers. Then, the wafers are inspected for defects. And eventually, the mask must undergo a cleaning process.

All of this is critical for contacts and vias. Unwanted defects can kill a single via or contact. “These particles that you can get are so big. So, you have to go through this extremely complex and painful requalification process,” HJL’s Levinson said.

Chipmakers would prefer to avoid print checks. “It’s inconvenient. It impacts your productivity,” Levinson said. “The real painful part is when you have to clean the mask and rework the wafers. You might get rid of one particle and you add two more.”

Clearly, inserting EUV is a difficult process. Yet, HVM hasn’t even started. When that does happen, EUV will save money or become more painful—or both.

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