For most of the last 20 years, foundries like TSMC and IDMs (integrated device manufacturers) like Intel have operated in parallel tracks with only minimal direct interaction. In recent years, that’s changed. Not only is Intel pushing its hardware into markets typically served by some of TSMC’s largest and most important customers, the two chip makers have begun to spar with each other over key transistor metrics, including transistor counts. Apple’s A8 and Intel’s Core M/Broadwell have kicked off the latest round, with both Intel and TSMC supporters claiming that various data points prove their preferred company is superior.

Unfortunately, out of all the ways to compare the output of two foundries, transistor counts (and associated derivations of relative density) is one of the worst. It doesn’t matter if you think Intel or TSMC has a particular edge on density; relying on transistor counts to argue which product is better is a significant mistake. Here’s why.

Transistors are not created equal

Transistor density is a useful metric when comparing two identical (or nearly identical) chips across process nodes at the same foundry. When Chipworks analyzed the Apple A8 SoC recently, it performed this type of analysis, comparing the size of each major SoC block (CPU, GPU, and cache) at 20nm against the Apple A7 at 28nm. This kind of fine-grained analysis reveals three entirely different scaling ratios between the two nodes — because not all transistors scale equally.

This rule doesn’t just apply to different types of circuits — it impacts the design layouts for the same type of circuit at different clock speeds. The graph below illustrates how projected SRAM density changes as clock speed increases between 16nm and 28nm (the blue line is 28nm, the green line is 16nm).

At 500MHz, the 16nm SRAM is 60% more dense than the 28nm chip. At 1550MHz, 16nm SRAM is only about 10% more dense than 28nm. While this is a projection of expected SRAM density, not a review of any particular process, it illustrates the point — frequency and speed matter.

It’s not always better to have more transistors

Up until the early 2000s, transistor count was a valid indication of how much additional processing power could be packed into an area. Moore’s law and Dennard scaling, when combined, held that more transistors could be packed into the same space and that those transistors would use less power while operating at a higher clock speed. Classic Dennard scaling no longer occurs at each lower node, which means that packing more transistors into a smaller space no longer guarantees lower total power consumption. Hot spot formation is a major limiting factor on performance these days, which means packing more transistors into tinier areas may also limit sustained clock speeds.

Equally important, however, is the fact that packing more transistors into a smaller space no longer correlates directly to higher performance, either. In the old days, doubling a chip’s transistor count translated directly to more cache, additional CPU cores, or an on-die memory controller. Today, those additional transistors might be spent on sophisticated power gating logic, additional functional blocks within the SoC that don’t directly impact traditional performance metrics, or spent on capabilities like big.Little — ARM’s method of improving SoC power efficiency by mixing low-power and high power cores.

In some cases, these new features still improve performance by allowing for higher burst frequencies or longer battery life, but the question of whether more transistors results in a better final product depends entirely on what the criteria for “better” are.

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