Two new tidbits on AMD’s next-generation GPU architectures have surfaced courtesy of LinkedIn — and while that’s not our typical avenue for discovering new data, past information cribbed from profiles has indeed panned out. In this case, it’s a pair of profiles — one from Linglan Zhang, a system architect manager at AMD, and one from Ilana Shternshain, an ASIC physical design engineer.

The two profiles collectively point to two things. First, that the upcoming R9 380X GPU from AMD has already taped out and gone to manufacturing. This is welcome news, given that Nvidia’s Maxwell shipped months ago, but it doesn’t tell us much in and of itself. It was always a given that AMD would build a new GPU architecture, and we don’t have any information (yet) on whether the R9 380X jumped for 20nm technology or stayed on 28nm. Since new nodes aren’t a guaranteed advantage for large, complex chips the way they used to be, it’s harder to predict what AMD might do.

Second, and arguably more interesting, is Zhang’s profile, which includes the following:

So, what is “High Bandwidth Memory,” and how could it change the future of AMD’s graphics?

Understanding HBM

High-Bandwidth Memory is a specialized application of the Wide I/O memory standard we’ve previously discussed as a long-term replacement for DDR4. Hynix, AMD’s co-partner in developing the standard, describes it as “Wide I/O stacked DRAM with TSV” (through-silicon vias). In this configuration, the GPU RAM would be implemented directly around the GPU itself for optimal routing and minimal cost. One difference between 3D Wide I/O and HBM is that Wide I/O can be stacked directly on top of the SoC — you wouldn’t want to do that with HBM, due to the GPU’s phenomenal heat output.

Everyone agrees that HBM is going to be the Next Big Thing, including AMD and Nvidia themselves, and there’s good reason for it. Even initial HBM implementations are going to offer at least equivalent bandwidth to today’s high-end cards, but with significantly improved access latencies and power consumption.

One thing to keep in mind is that this charge is intrinsically designed to make HBM look good. They’re comparing a DDR3 DIMM of just 8 bits (traditional implementations are 64-bits) and an GDDR5 bus of just 32-bits (most modern GPUs gang 8-12 memory controllers together). In other words, the 128-256GB/s worth of bandwidth off HBM isn’t the only benefit — the benefit is in cost, trace complexity, latencies, and power.

Is AMD ready to deploy HBM in next-gen Radeons?

We know HBM can bring substantial performance improvements, and we know that AMD is working on the technology. The question is, is it ready to deploy on next-generation hardware yet? That’s where a macro-economic perspective is more helpful, and the information there, more tenuous. According to multiple sources, TSMC only began ramping up its TSV support quite recently. The next graph comes directly from TSMC’s own projections of wafer start times for various types of standards:

The “HBM” block takes up most of 2015, but tilts towards the back half of the year. Since these are wafer starts as opposed to volume production, it implies that there’s going to be lag time between the launch of these parts and full availability. GlobalFoundries is also building HBM capabilities, but is rumored to be behind TSMC in deploying the technology.

This suggests one of two things: Either the R9 380X will not use HBM and that technology will be reserved for a second, follow-up GPU (possibly an R9 390X coming later this year or early next year), or that the R9 380X will use HBM, but will not deploy until later in the year to give the technology time to mature.

There is a third option, though it would be fairly out-of-band for AMD, given its current financial situation. The company could have opted to aggressively adopt HBM, sacrificing costs for performance and early availability. If AMD managed to steal a year on Nvidia’s Pascal, it could tilt the competitive landscape sharply back towards Team Red and give the company a welcome shot of good news.

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