A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of its own circuitry. This ISA consists of a number of instructions, which essentially define the functionality of that processor, which explains why so many ISAs still exist today. It’s hard to find that one ISA that works for as many distinct use cases as possible, after all.

A fairly new ISA is RISC-V, the first version of which was created back in 2010 at the University of California, Berkeley. Intended to be a fully open ISA, targeting both students (as a learning tool) and industrial users, it is claimed to incorporate a number of design choices that should make it more attractive for a number of applications.

In this article I’ll take a look behind the marketing to take stock of how exactly RISC-V differs from other open ISAs, including Power, SPARC and MIPS.

Welcome to the World of RISC

A Reduced Instruction Set Computer (RISC) is a type of ISA which focuses on creating an instruction set that requires only a limited number of processor cycles to execute a single instruction. Ideally, an instruction would take exactly one cycle. This is in contrast to a Complex Instruction Set Computer (CISC), which focuses on reducing the number of instructions needed for an application, which decreases code storage requirements.

These days CISC is essentially no more, with the Motorola m68k ISA put out to pasture, and any CPU based on Intel’s x86 CISC ISA and successors (like AMD’s 64-bit extensions) being internally a RISC processor with a CISC ISA decoder front-end that breaks CISC instructions into the RISC instructions (micro-opcodes) for its CPU core. At least as far as the CISC versus RISC ISA wars go, here we can say that RISC decidedly won.

Many flavors of RISC

Though RISC ISAs such as Alpha and PA-RISC met their unfortunate demise due to corporate policies rather than any inadequacies in their ISA design itself, we’re fortunately still left with a healthy collection of RISC ISAs today, most notably:

SuperH (with open J-2 implementation).

ARM (fully proprietary)

MIPS (open, royalty-free)

Power (open, royalty-free)

AVR (proprietary)

SPARC (open, royalty-free)

OpenRISC (open, royalty-free)

RISC-V as a newcomer places its 9 years of (academic) development against the 34+ years of MIPS, 33+ years of SPARC, and the Power ISA which has its roots in development IBM did back in the early 1970s. Considering the hype around this new ISA, there must be something different about it.

This also considering that OpenRISC, which was developed with many of the same goals as RISC-V back in 2000, never made much of a splash, even though it is being used commercially.

A Shifting Landscape

It’s important to note that back in 2010 when RISC-V was being developed, SPARC had been an open ISA for a long time, with ESA’s LEON SPARC implementation in VHDL having been available since 1997. Since 2010, MIPS and IBM’s Power ISA have also joined the ranks of open and royalty-free ISAs, with open source designs in Verilog, VHDL and others made available. MIPS has been a standard teaching tool for processor ISAs since the 1990s (usually based on DLX), with many students writing their own minimalistic MIPS core as part of their curriculum.

Because of the existing contenders in these areas, RISC-V cannot simply distinguish itself by being open, royalty-free, having a more mature ISA, or better freely available HDL cores. Instead its ISA must have features that make it attractive from the standpoint of power efficiency or other metrics, allowing it to process data more efficiently or faster than the competition.

Here one defining characteristic is that the RISC-V ISA isn’t a singular ISA, but over 20 individual ISAs, each focusing on a specific set of functionality, such as bit manipulation, user-level interrupts, atomic instructions, single- and double-precision floating point, integer multiplication and division, and so on. Also interesting in the RISC-V ecosystem is that adding custom instruction sets without any kind of approval process is encouraged.

Ignoring the Future

One interesting choice in the RISC-V ISA itself is in the subroutine calls and conditions, with RISC-V having no provision for a condition code register (status register), or a carry bit. This choice makes predication impossible, instead forcing the processor to execute every single branch in the expectation that one of them is correct, discarding the results of the other branches. As branch prediction is optional in RISC-V, this could come with a big performance and energy cost penalty.

Since every other major architecture uses predication to improve performance especially for blocks of shorter jumps, such as that produced by a big if/else block or switch statement, it’s quite daring to omit this feature. The provided design rationale by the RISC-V developers is that fast, out-of-order CPUs can overcome this limitation through brute processing force. Interestingly, they do not see the larger code size produced for code without predication to be an issue, despite being proud of their compact instructions being generally quite compact.

Here the somewhat schizophrenic nature of the RISC-V development process begins to shine through. Though it’s supposed to be a good fit for embedded, presumably low-clocked processors, its lack of predication will likely hurt it here in raw performance compared to equivalent ARM-based microcontrollers, whose Thumb-2 compact instruction set is also more efficient than the RISC-V compact ISA.

Choosing Uncertainty Over Certainty with RISC-V

At this point, the only parts of the RISC-V ISA which are ‘frozen’ – meaning that they can be implemented without any fundamental changes expected – are the Base Integer sets for the 32- and 64-bit version, as well as the extensions for integer multiplication and division, atomics, single- and double-precision floating point, as well as quad-precision floating point and compressed instructions.

Extensions such as the hypervisor, bit manipulation, transactional memory, and user-level interrupts are still in flux and thus unsuitable for anything but experimental use, further fragmenting the whole RISC-V ecosystem. This clearly shows that RISC-V isn’t a ‘finished’ ISA, but still very much in the early stages of development. While its core is usable, the embedded instruction set isn’t finished either, and there’s no readily available performance data to back up claims that it can handily outperform any competition.

Worse is probably the immaturity of the available HDL cores and software tools for RISC-V. With the stabilization of the ISA sets taking time, it’s no surprise that few cores and tools offer or expect anything beyond the basic (RV32I or RV64I) functionality. Without many more ISA sets being finished and incorporated into silicon, to a bystander there’s the interesting thought that maybe the major contribution of RISC-V to this renewed ISA war isn’t that of RISC-V being necessarily superior, or it even having any long-term commercial viability.

Showing How It’s To Be Done

Back in 2000 when the OpenRISC project took off, it appeared that the market didn’t quite have the appetite for open and freely available ISAs and associated processor designs. Today that seems to be quite different, and it was RISC-V, not OpenRISC that kicked off this change in corporate thinking that caused IBM to open up its Power ISA, along with the MIPS ISA and even the ARM ISA to a limited extent. RISC-V having DARPA funding when OpenRISC did not probably played a role here too, but who is counting?

Regardless of such details, it seems that the computer hardware industry has embarked on a new path, one where even a hobbyist has access to a number of well-supported HDL cores and is free to experiment with the ISA. Right now one can pick between fully open MIPS, SPARC, Power, RISC-V, and SuperH cores, with maybe some day a fully open ARM core becoming reality as well.

In some ways it evokes flashbacks to the 1980s, when amidst the rapidly growing home computer market, multiple CPU manufacturers struggled to make their ISA and their chips to be the most popular, with Zilog’s Z80 and of course the 6502 being strong 8-bit contenders before a little upstart called ‘Intel’ began to make inroads, culminating in the seemingly complete disappearance of ISA diversity on the desktop and most recently in video consoles.

Here’s to Diversity

I wouldn’t go so far as to say I have a longing for the days of dissimilar platforms (lest someone call me a daft bastard). Anyone working in the software industry during the formative years of personal computing will find themselves regressing through the traumatic memories of porting software between the Commodore 64 and ZX-Spectrum. Thinking that we have it so much better now is not such an extreme position to take.

That said, everyone with a sense of what competition means can see that a world with only Intel, or only AMD, or only ARM, or only RISC-V processors in everything would be rather dull indeed. It is the bouncing off of ideas, of comparing differences, that keeps people thinking and that keeps innovation going. Modern software practices should mean that cross-platform compatibility isn’t as much of an issue as it was back in the 1980s and 1990s.

Here’s to an open, diverse future in the world of ISAs.