Built on OA from scratch without legacy code, Analog Rails Basic uses the same database as Virtuoso. Never have a DRC nor LVS violation. Crossprobing and backannotation at all times. Infinite supply of multithreaded co-simulation licenses.

Infinite number of simulator licenses

Cosimulation and multithreaded, users can run millions of fets alongside both digital and analog behavioral simulations on a single engine simulator. No need to klunk away with an analog and digital simulator on a backplane, our XMS simulator/environment is way superior to AMS Designer. Included is Harmonic Balance and built-in RF measurements, such as transient noise. Never again pay for a simulator, XMS is the best simulator in the business. Works with BSIM3, BSIM4, BSIM6, etc. Users can also optionally simulate with 3rd party Hspice compatible simulators just in case they want to double verify. The netlister is customizable. Hundreds of behavioral models, both analog and digital are also included.

Measurements and analysis components in the schematic

Place settling time, overshoot, bandwidth, phase margin, risetime, and etc. components into the schematic, along with multiple analysis components (ac, dc, tran, pss, etc). Corner setups are included in the analysis components.

Sensitivity Analysis

All measurements receive the variation and the largest culprits, both the devices and their parameters, causing the variation.

Manual DRC/LVS correct by construction™ layout

Much more powerful than DRC and LVS, the users cannot make a DRC or LVS violation. Primitives (fets, caps, resistors, bipolars, and differential structures) are generated automatically based on the technology file. No CAD scripts required. Structures snap/repel/permute based on schematic connectivity. Collision avoidance on wiring. Once again, it is impossible for users to make violations.

Never lose crossprobing

Even when flattening the layout, Analog Rails continues to crossprobe the schematic and layout. The circuit designer can always follow the signal...even in 3D!

Simulate layout parasitics at all times

Why wait months to get layout parasitics, such as STI Stress Effects, length of diffusion, and well proximity? DC Currents can be off by 20% without knowing these layout generated values. Now setting reltol has more meaning.