The other day we wrote about Getting Started with Embedded Linux on RISC-V in QEMU emulator and noted that Linux capable RISC-V hardware is currently fairly expensive.

We also mentioned there was work on porting uCLinux to Kendryte K210 RISC-V processor on boards such as Sipeed Maix board. The processor only comes with 8MB RAM, and does not feature an MMU (Memory Management Unit) so what you’d be able to do on the board would be limited, and for instance, a desktop environment is clearly impossible on the platform.

NOMMU support also requires some extra work, and in Linux 5.4 we saw only of the changes was “SiFive PLIC IRQ chip modifications, in preparation for M-mode Linux”.

The slide above is extracted from the “RISC-V NOMMU and M-Mode Linux” presentation by Damien Le Moal, Western Digital at the Linux Plumbers Conference 2019 last September. It explains M-mode support is better suited for NOMMU mode since more direct access to the hardware is possible, while S-mode is synonym with “have MMU”. The work on M-Mode also reduces RISC-V SBI (Supervisor Binary Interface) overhead and will benefit regular S-mode.

If we scroll to the end of the presentation we can also see a boot log showing Linux 5.1 booting to a minimal root file system with Busybox on Kendryte K210 powered Sipeed MAIX Go board with 6+2 MB RAM that sells for a little over $40 as part of a kit with camera and display.

The board will eventually be supported un mainline Linux too, as Linux 5.5 will add support for RISC-V NOMMU:

below is a series to support nommu mode on RISC-V. For now this series just works under qemu with the qemu-virt platform, but Damien has also been able to get kernel based on this tree with additional driver hacks to work on the Kendryte KD210, but that will take a while to cleanup and upstream. A git tree is available here:

git://git.infradead.org/users/hch/riscv.git riscv-nommu.5

There are two new configuration options to enable support for RISC-V NOMMU: CONFIG_RISCV_M_MODE to switch between M-mode and S-mode, and CONFIG_RISCV_SBI to completely disable/enable SBI.