Ah, if only Apple would've stuck with PowerPC, maybe it could've skipped the magical 3GHz mark and jumped straight to 4.7GHz. Okay, that's really just a cheap shot, but I couldn't resist, given today's major announcement by IBM that the 65nm POWER6 will not only debut next month at a stratospheric 4.7GHz, but it also shreds most of the relevant benchmarks. But before we get into the details, let's take a look at the basics of what was announced. From IBM's press kit, shorn of some of the marketspeak and with some of the details expanded:

Top frequency of 4.7GHz

>790 million transistors

341mm2 die size

65nm SOI process with ten layers of copper interconnect and a low-k dielectric on the first eight levels

Dual-core

Two-way simultaneous multithreading (SMT) on each core

Two memory controllers

Manufactured at IBM's 300mm semiconductor fab at East Fishkill, NY

With the exception of the actual top frequency number, all of the details above have been reported here previously. In fact, you might recall that at this past year's ISSCC, IBM claimed that POWER6 would debut north of the 5GHz mark, so Big Blue fell a bit short on that score. But such a shortcoming is pretty forgivable when you consider the fact that POWER6 has the same number of pipeline stages as its predecessor (15 integer stages), and it doesn't draw much more power.

My previous coverage of IBM's ISSCC revelations mentioned that serious questions remain about the POWER6 core architecture; questions on which IBM has kept decidedly mum. These questions center on the chip's out-of-order execution capabilities or the potential lack thereof. It's a good bet that one of the tricks that IBM used to get POWER6's clockspeed up so high was that the design team stripped away a ton of complexity from the pipeline by removing the out-of-order execution window. IBM has stated that floating-point instructions can issue out-of-order, but such issuing is certainly very limited in order to cut down on bookkeeping overhead.

Ultimately, there's a lot that can and should be said about what IBM did to bring about such a dramatic boost in clock frequency with POWER6, but that will have to wait for a separate article. In the meantime, let's take a look at the fruits of IBM's success.

Benchmark bombshell

Aside from the fact that IBM appears to have delivered on 90 percent of their clockspeed and power envelope promises with POWER6, the real news in today's announcement comes from the benchmarks that have been unveiled. Not only has IBM nearly doubled the frequency of the POWER5 design, but it has nearly doubled the benchmarks scores as well. Indeed, IBM is so happy with the benchmark results that it has dedicated an entire section of their site to publishing POWER6 benchmarks on a whole slew of different types of workloads.

The TPC-C benchmarks that were announced today put IBM's new POWER6-based p570 at the top of the 16-core pack with a score of 1,616,162 tpmC. This score is more than double that of its POWER5-based predecessor. The situation is similar with the Oracle Applications Standard Online Benchmark, which shows an 8-core POWER6 system doubling the performance of its POWER5 predecessor on this popular suite of transaction processing benches.

And then there are the famous SPEC scores, where POWER6 cleans up as well. On specjbb2005, the new POWER6 p570 (16-core) clocks in at 691,975 business operations per second (bops), a number that's more than double the 326,651 bops score of the machine's POWER5+-based predecessor. In the CPU2006 benchmarks, POWER6 takes the crown in both floating-point and integer with a specint of 21.6 and a specfp of 22.3 (both are single-core, single-threaded numbers). This puts POWER back ahead of the previous integer champ, Intel's Core architecture, and it also gives it a solid lead over Intel's Itanium line. Indeed, POWER6 is looking significantly better than the IPF lineup for a number of tasks, a fact that makes one wonder about the impact that the new launch will have on Itanium's growth.

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