Intel's 10nm was definitely NOT too ambitious

1. Wrong calculation

Analysis. A 6.2T library to me would indicate a 120MTr density, interestingly, which Intel hasn't reported. I mean, gate pitch is same as TSMC, metal gives Intel 0.9x, COAG is 0.9x and SDG is 0.8x. So a 6.2T library means Intel 10nm has a solid 50% higher density than TSMC 7nm. Click to expand...

Note

2. Correct calculation

As I said, like Samsung, the cell height is a function of the quantized diffusion lines (your fin pitches). 14nm had 9.5 of them and that has been reduced to 8 in 10nm. Talking in terms of tracks does not really make sense for neither Intel nor Samsung for this very reason. Click to expand...

3. Intel 22-14-10-7nm scaling

It's interesting to ponder this further, since it does raise a couple of questions. Why does Intel use SAQP for the interconnect, whereas TSMC only uses SAQP for the 30nm fin pitch (not in the interconnect), while having a bigger cell size? Why does Intel use a 36nm pitch at all, given that TSMC can do a smaller cell with 40nm pitch and SADP? My guess is that they went with 36nm to get the most out of the cobalt interconnect to hit their performance targets. ​

Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.



And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.



So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.



As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.



And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers. Click to expand...

4. TSMC 7nm