btarunr You are absolutely correct. I've revised the article.

Mysteoa There are some speculation reagrding the double l3 cash. It's possible that the IO die has a duplication of the L3 and SiSoftSandra doesn't read it correctly. This is maybe to keep latency low when a cores that need something from L3 on different chiplet will only make one hop to the IO, not 2 hops without it.

_Flare Of course Sisoft could be mistaking by staticly dividing every four Cores, yes.

But i think the OS should get correct reports about the segmentation etc., so its unlikely but in deed possible.



So there is little chance that every Chiplet is One big 8-Core CCX with 32MB L3-Cache.



@btarunr "you are very welcome"

I saw this on reddit last week. Other theory is Adored tv might have been on to something. It could be 8core ccx and IO die has copy of L3 cache to improve latency. He mentioned that in his video, that would make sense too. He said it would make too much sense to reduce latency between cores and IO die being massive. Its either what adore was saying in his video or 4 core ccx a massive IO chip. But I am honestly leaning towards 8 core ccx with copy of l3 caceh on IO Die. The die seems massive and there has to be something going on there.Yep! I am leaning on this, Adored guy was mentioning the same thing. He said it made so much sense given IO die is so massive and they can improve latency by copying l3 cache. The guy knows his shit about chips, he said he was speculating but it made too much sense.It doesn't have to be. THe massive IO die could basically have a copy of each l3 cache to reduce latency and sandra might just be reading it wrong.