After initially working to create a modernized replica of a Czechoslovakian 4-digit Metra M1T242 voltmeter, [Jaromir Sukuba] figured that while he was at it, he might as well create a voltmeter that would be slightly more capable. This led to the design and construction of a brand-new, 6.5 digit voltmeter design, which [Jaromir] has documented over at EEVBlog.

Employing an MSP430FR5994 MCU for the digital board, and an Altera/Intel EPM240T100 CPLD plus ADC on the input side, the design has been undergoing validation for a while now. The current revision uses an OPA140 op-amp in an integrating ADC setup in a multi-slope run-up configuration, but [Jaromir] has plans to replace this input board with another op-amp in a more efficient topology in the future.

Validating a voltmeter is the real challenge here, with determining the ADC noise and overall stability of the measurements. Here the ability to validate one’s design is of course limited by the quality of the testing equipment one has available. As there’s no ‘perfect’ level, it means that there will always be room for further improvement, which is both a blessing and curse with a DIY meter like this.

[Jaromir] has made the schematics and sources (firmware and Verilog HDL) available via the EEVBlog page, allowing anyone to start on their own version, or even contribute to the project. That is, assuming that one look at the internals of the prototype system hasn’t already filled you with too much respect for the sheer complexity of such a project.

(Thanks to David Gustafik for sending this one in)