SANTA CLARA, Calif. — Engineers see many options to create 5-, 3- and even 2-nm semiconductor process technologies, but some are not sure that they will be able to squeeze commercial advantages from them even at 5 nm.

The increasing complexity and cost of making ever-smaller chips is leading to diminishing returns. Data rates are peaking at 3 GHz for mobile processors, and power and area gains will narrow at 7 nm, said a Qualcomm engineer in a panel at a Synopsys user group event here.

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Speed gains of 16% at 10 nm may dry up at 7 nm due to resistance in metal lines. Power savings will shrink from 30% at 10 nm to 10–25% at 7 nm, and area shrinks may decline from 37% at 10 nm to 20–30% at 7 nm, said Paul Penzes, a senior director of engineering on Qualcomm’s design technology team.

For decades, the electronics industry followed a roadmap codified by Moore’s law of doubling the number of transistors on a chip roughly every two years. The result was a fast pace of ever-smaller, faster, cheaper products from PCs to smartphones.

“Area still scales in strong double digits, but the hidden cost increases in masks means the actual cost advantages and other improvements are starting to slow down … It’s not clear what will remain at 5 nm,” said Penzes, suggesting that 5-nm nodes may only be extensions of 7 nm.

Versions of today’s FinFET transistors will be used down to the 5-nm node, said technologists from Synopsys and Samsung on the panel. Below a width of about 3.5 nm, FinFETs will hit a hard limit.

Designers will need to transition to a stack of probably three thin horizontal nanowires sometimes called nano-slabs, said Victor Moroz, a fellow and transistor expert at Synopsys. For its part, Samsung has announced plans to use a gate-all-around transistor for a 4-nm process that it aims to have in production by 2020.

At future nodes, pitch scaling will slow to about 0.8x per generation, according to Munoz of Synopsys. That will force designers to shrink cell heights from about 228 nm with two fins and six tracks at 7 nm to 130–100 nm with five tracks and a single fin at 3 and 2 nm, he said.

Using such techniques, “silicon looks to safely take us to 2 nm, and after that, we may look to graphene,” he concluded.

However, in a Q&A session, one attendee expressed shock at the idea of a five-track cell with a single fin.