I found code to add 1 + 1 using QASM (Quantum Assembly Language), so I decided to try 2 + 2. I must admit it was more challenging than I thought it would be.

At first, I tried to add 1 + 1 twice and then use the same algorithm on the outputs. However, the carry was causing me problems.

So, it occured to me to emulate adder circuitry. I decided to use a half adder feeding into a full adder. Instead of just 2 + 2, this should give me the ability to add 0 through 3 plus 0 through 3. It does, sort of.

Image credit: elprocus.com; XOR gates are red, AND gates are orange, and the OR gate is purple.

First, the code:

OPENQASM 2.0;

include "qelib1.inc";

qreg q[11];

creg c[3];

These introductory lines initialize 11 quantum registers and 3 classical registers.

x q[1]; // q[1]q[0] is binary 10 (decimal 2)

x q[3]; // q[3]q[2] is binary 10 (decimal 2)

All qubits start with a value of 0. Above, the values of the 2nd and 4th qubits are changed to 1. I use the 1st 2 qubits for the 1st number and the 2nd 2 qubits for the 2nd number.

barrier q; // half adder

cx q[0], q[4];

cx q[2], q[4]; // sum

ccx q[0], q[2], q[5]; // carry

A half adder accepts 2 inputs, and then outputs the sum and the carry.

barrier q; // full adder

cx q[1], q[6];

cx q[3], q[6]; // XOR1

ccx q[1], q[3], q[7]; // AND1

cx q[6], q[8];

cx q[5], q[8]; // XOR2

ccx q[4], q[5], q[9]; // AND2

barrier q; // OR

x q[7];

x q[9];

ccx q[7], q[9], q[10];

x q[10];

A full adder accepts 3 inputs, including the previous carry. It outputs the sum and a new carry.

measure q[4] -> c[0];

measure q[8] -> c[1];

measure q[10] -> c[2];

This produces the output, in binary. The 1st qubit is the sum from the half adder, the 2nd qubit is the sum from the full adder, and the 3rd qubit is the carry from the full adder.

Creating a full adder using QASM was challenging. While XOR and AND gates are common, there are no OR gates. It’s been a while since I played with boolean gates, so I eventually settled on reversing all the inputs and outputs on an AND gate, which produces OR gate results.

The graphical representation does not screencapture well, but I’m including it just in case anyone finds it helpful.

The resultant histogram shows 100, which is binary for 4. Since 2 + 2 = 4, I’ll call that part of the experiment a success.

Unfortunately, there is one bug that I can’t squish. I tested every permutation of inputs (I think), and every sum from 0 through 6 works… except for 3 + 1 and 1 + 3.

I traced the bug to the first AND gate in the full adder. The inputs, which I measured for confirmation, are 0 and 1. Therefore, the gate should output a 0. Instead, it outputs a 1.

The only troubleshooting that I could think of to do next was to run it on real hardware. Every test up until that point had been run as 1 shot on a simulator, so I ran it one more time on real hardware with the maximum number of shots.

On real hardware, imprecise measurements and residual heat cause every possible outcome to have some probability of being the result. The binary 100 result, which is the decimal 4 that I am looking for, at least has the highest probability.

Does that indicate an issue with the simulator’s AND gate? I don’t know, but I suspect there’s at least some probability of it… pun intended.