- I cleaned up the asm code and fixed several comments, which makes the boot process much easier to understand. - I fixed the alignment for the text segment, so that it can be covered by more large pages [1] - thereby reducing TLB contention. - I fixed a bug in the way the secondary CPUs are launched [2], which caused them to crash if they tried to access an X-less page. - I took rodata out of the text+rodata chunk, and put it in the data+bss+ PRELOADED_MODULES+BOOTSTRAP_TABLES chunk [3]. rodata was no longer large page optimized, and had RWX permissions. - I retook rodata out of the rodata+data+bss+PRELOADED_MODULES+ BOOTSTRAP_TABLES chunk, and made the kernel map it independently without the W permision [4]. - I made the kernel map rodata without the X permission, by using the NOX bit on its pages [5] (now that the secondary CPUs could handle that properly). - I took the data+bss chunk out of the data+bss+PRELOADED_MODULES+ BOOTSTRAP_TABLES chunk, and made the kernel map it independently without X permission [6]. - I made the kernel remap rodata and data+bss with large pages and proper permissions [7] - which reduces once again TLB contention.

- on non-PAE i386, NOX does not exist. Therefore the mappings all have an additional X permission. To benefit from X-less mappings, your CPU must support PAE, and your kernel must be GENERIC_PAE. - the segments are not large-page-aligned, which means that probably some parts of the segments are still mapped with normal pages. It is still more optimized than it used to be, but not as much as amd64 is.