Note: The following somewhat lengthy excerpt is based on the article “Calculating Mathematically Complex Functions” by Adam Taylor, which appears in the hot-off-the press Xcell Journal, issue 87. Adam contributes frequently to Xcell Journal and has published nearly 30 instalments of his “MicroZed Chronicles” series in Xcell Daily. He recently became Head of Engineering for Systems at e2v Technologies.

By Adam Taylor

It is not uncommon to see tight accuracy and calculation latency times in more critical applications. Thanks to their flexibility and performance, FPGAs have found their way into a number of industrial, scientific, military, and other applications that require the calculation of complex mathematical problems or transfer functions. There are many algorithms, such as the CORDIC algorithm, that you can use to calculate transcendental functions.

A CORDIC algorithm is capable of implementing transcendental functions such as sine, cosine, multiplication, division, square root and so on. Therefore, it is possible to implement transfer functions exactly using a combination of CORDIC algorithms and basic mathematical blocks. The technique can result in higher precision. However, for a complicated transfer function, this gain in precision will come at the cost of increased design and verification time. (See Xcell Journal issue 79, “How to Use the CORDIC Algorithm in Your FPGA”. Also, for a very brief history of the CORDIC algorithm’s development back in the 1950s, see “CORDIC and the Hustler,” here.)

When confronting mathematically complex transfer functions, there are more efficient ways of dealing with them than by implementing the exact function within the FPGA. One such example of a complex mathematical transfer function would be an FPGA that monitors a platinum resistance thermometer (PRT) and converts the PRT’s resistance into a temperature. This conversion typically employs a Callendar-Van Dusen equation. In its simplified form, shown below, this equation can determine temperatures between 0oC and 660oC.

R = R 0 * (1+ at + bt2)

where R 0 is the resistance at 0oC, a and b are coefficents associated with the PRT, and t is the temperature. In reality, we want to convert from resistance to a temperature so we need to rearrange the equation to get temperature as a result of resistance. Most systems that use a PRT will design electronics to measure the resistance of the PRT using an electronic circuit, leaving the FPGA to calculate the temperature using the rearranged and far more complex equation below:

Implementing this equation within an FPGA can daunt even a seasoned FPGA engineer. Plotting the obtained resistance against temperature results in the graph shown below:

If you look closely, you’ll see the nonlinearity of this response curve.

Many engineers will look for different methods to implement the function to reduce design and validation effort and to protect project time scales. One possible approach would be using a lookup table to store a number of points on the curve with linear interpolation between the points. This approach may fit the bill, depending upon the accuracy requirement and number of elements stored within the lookup table. However, you will still need to include a linear interpolator function within the design. This function can be mathematically sophisticated and will often include a non-power-of-two divide, which adds to the complexity.

Modern FPGAs including the Xilinx Spartan-6 and devices in the 7 series Artix, Kintex and Virtex All Programmable FPGA families contain much more than just the traditional lookup tables and flip-flops. They also include built-in DSP slices, Block RAM, and distributed RAM, along with many advanced hard IP cores such as PCIe and Ethernet endpoints, high-speed serial links, and so on. You can use the internal RAM structures and DSP slices to implement transfer functions with great ease.

Polynomial approximation is one method that utilizes an FPGA’s DSP- and RAM-rich architecture. To use this technique, you first plot the mathematical function, covering the input value range in a mathematical program such as MATLAB or Excel. You then add a polynomial trend line to the data set in question such that the equation for the trend line can then be implemented within the FPGA in place of the mathematically complex function, provided the trend-line equation meets the accuracy requirements.

Most mathematical programs capable of adding a polynomial trend line allow you to select the order, or number of polynomial terms. The larger the order, the more accurate the fit should be—but the more terms you will need to implement within the FPGA. When performing this process using Microsoft Excel on the PRT curve, we obtained the following 4th-order polynomial:

y = 2E-09x4 - 4E-07x3 + 0.0011x2 + 2.403x - 251.26

Should one polynomial equation not provide sufficient accuracy over the entire transfer function input range, just add more. It is still possible to use this approach so long as you generate a number of polynomial constants for use across the input range. Thus, once the input value goes outside specific bounds, a new set of constants is loaded.

Suppose, for example, that we require an extended operating range and tolerance to 300oC. Our initial approach would not meet the design requirements. Using a segmented approach, we can address this problem by plotting the range between 269oC and 300oC and obtaining a different polynomial equation that will provide more accuracy for this output range. In short, a segmented implementation uses the first set of polynomial constants until the input value goes above a precalculated range corresponding to 268oC. Above 268oC, the second set of constants is used to maintain the accuracy requirements.

Even if the design team employs a system-on-chip with embedded microprocessor cores such as the Xilinx Zynq All Programmable SoC with a dual-core ARM Cortex-A9 MPCore processor, challenges still remain. For starters, the time it takes to calculate the transfer function in software running on the processor core would take much longer than can be achieved in programmable logic, slowing system response time. In fact, calculation of transfer functions such the one used above is a classic example of where the processing should be offloaded to the programmable-logic side of the Zynq SoC.

To see more detailed information on using the Zynq SoC’s interrupts including code samples, read the full version of Adam Taylor’s article by clicking here.

Read more about the using the Zynq in Adam Taylor’s “MicroZed Chronicles”:

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

Bringing up the Avnet MicroZed with Vivado