Microchip’s Microsemi unit unveiled a low power, real-time deterministic “PolarFire SoC” architecture for Linux edge devices that combines its PolarFire FPGA with 4x RISC-V CPU cores supplied by SiFive.



At today’s RISC-V Summit in Santa Clara, Calif., Microchip’s Microsemi subsidiary announced a PolarFire SoC architecture developed in collaboration with SiFive. This “fully customizable, programmable RISC-V platform” will “bring real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core CPU cluster,” says Chandler, Ariz. based Microchip.

The PolarFire SoC design is billed as the world’s first RISC-V based FPGA, a type of programmable processor that has seen increased adoption in fields ranging from edge servers to drones. The system-on-chip combines Microsemi’s low-power PolarFire FPGA with SiFive’s quad-core U54-MC CPU core complex to help developers build real-time systems with predictable behaviors. The same cores power SiFive’s Freedom U540 SoCs on its HiFive Unleashed board, one of the PolarFire SoC’s Linux development platforms (see farther below).







PolarFire SoC architecture

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The PolarFire SoC will compete most directly with Xilinx’s hybrid Arm/FPGA Zynq SoCs, according to Microchip’s Tim Morin during a LinuxGizmos briefing. In terms of performance, this mid-range design falls between the original dual Cortex-A9 Zynq-7000 and the Cortex-A53 based Zynq UltraScale+

The PolarFire SoC’s chief advantages over hybrid Arm/FPGA SoCs, which also include Intel’s more datacenter focused Stratix 10, include the more customizable, open RISC-V design, as well as lower power consumption and much better real-time deterministic capabilities.

“With the PolarFire SoC ISA, Linux and real-time can coexist side by side in a more elegant fashion than we’ve seen before,” said Morin, Microchip’s director of product marketing, Programmable Solutions business unit.







SiFive’s U54-MC Coreplex architecture

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Deterministic real-time embedded applications are enabled via a slightly modified version of SiFive’s U54-MC Coreplex SoC design, which combines 4x 28nm fabricated U54-MC cores with a fifth “E51” management core. The Coreplex features a 2MB L2 “coherent cache” subsystem, which on the PolarFire SoC can be configured as a cache, a scratchpad, or as direct access memory.

After working with SiFive on the PolarFire SoC’s CPU subsystem, Microchip was initially disappointed with the real-time performance. The breakthrough was the decision to turn off the branch predictors for the E51 management core.

“You can turn the branch predictor off in the E51 core, which boots the system and gets it up and running,” said Morin. “This makes the core itself more deterministic, with all the cores coherent to subsystem. We can peel off a portion of L2 cache to provide direct access to memory, and peel off a bit more for a scratchpad coherent buffer for all the cores and that can be used for message passing between Linux.”







PolarFire SoC’s U54-MC Coreplex, showing how turning off branch predictors enable deterministic features

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The removal of the branch predictors demonstrated another advantage of working in the RISC-V community. Not only is the open RISC-V platform designed for such customization, but in these early days for RISC-V, so are the vendors.

“SiFive is a very flexible IP provider,” said Morin. “I find it hard to believe that Arm would do something like turn off branch predictors.”



Low-power, secure PolarFire FPGA

RISC-V’s low power consumption is due in part to its simplicity, which also makes it easier to customize, debug, and secure against threats, says Microchip. Meanwhile, the PolarFire FPGA architecture is already notable for its low power consumption, which Microchip claims to be up to 50 percent lower than SRAM based FPGAs.

The PolarFire SoC also inherits the extensive security and reliability features of the PolarFire FPGAs. These include single and double error correction and double error detection (SEC-DED) on all memories.

Other security features include physical memory protection and a differential power analysis (DPA) safe crypto core. The PolarFire SoC also supplies “defense-grade” secure boot and 128Kb flash boot ROM, and because it uses a five-stage, in-order architecture, it doesn’t suffer from issues such as Sceptre and Meltdown found in out-of-order chips, claims Microchip.

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The PolarFire SoC is also touted for its advanced debug capabilities. These include instruction trace, 50 breakpoints, passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors, and FPGA fabric monitors. Other features include Microchip’s SmartDebug two-channel logic analyzer.



Linux development platform

Microchip is supplying a Linux-driven development platform that consists of the HiFive Unleashed SBC and Microsemi’s HiFive Unleashed Expansion Board. Launched in May on Crowd Supply in collaboration with manufacturing partner Pactron, the Expansion Board provides separate U540 and PolarFire FPGA chips combined with PCIe and USB expansion.







HiFive Unleashed Expansion Board

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HiFive Unleashed

Microchip is also supporting the PolarFire SoC with the open source Renode system modeling platform, which is developed and maintained by its partner Antmicro. Renode is integrated with Microchip’s SoftConsole IDE for embedded designs targeting PolarFire SoCs. Antmicro offers Renode to customers of Microchip and SiFive, enabling simulations of an entire SoC for RISC-V developers, not just the CPU. Renode 1.6 was released on Dec. 4, enabling pre-silicon software development for the PolarFire SoC, and is available on GitHub

Microchip is supporting the SoC design with its PolarFire Mi-V RISC-V ecosystem. It also announced a Mi-V Embedded Experts Program, a “worldwide partner network to assist customers in hardware/software designs for PolarFire SoC.” Services include full product lifecycle support, access to direct technical support, and early access to development platforms and silicon.

Morin noted that just because the PolarFire SoC is based on an open source ISA, it doesn’t mean it’s an open source SoC design. “We bought the IP from RISC-V, and while the instruction set is open source, some parts are owned by SiFive,” he explained. “In the I/O space we bought IP from Synopsis, Cadence, and others.”

Microsemi has led the way in developing soft-core implementations that can run on FPGAs for prototyping, and it was an early adopter of the open source RISC-V architecture. The company offers a soft-core SmartFusion 2 SoC FPGA for use with developing for SiFive’s MCU-like Freedom E300 SoC, which also drives SiFive’s Arduino compatible HiFive1 development board.

In late October, SiFive announced a slate of next-generation cores, including two more powerful Linux-ready models: the Cortex-A55 like U74 and U74-MC.

Stated SiFive CEO Naveed Sherwami: “By leveraging SiFive’s market-leading U54-MC CPU core complex, PolarFire SoC will enable designers to overcome the universal challenge of building real-time systems with predictable behaviors.”



Further information

No availability data was announced for the early-stage PolarFire SoC project. More information may be found in the announcement and product page at the website of Microchip’s Microsemi subsidiary.