New RISC Processor for SoC Developers is Yours for the Taking

by Jim Turley

“There are two major products that came from Berkeley: LSD and Unix. We don’t believe this to be a coincidence.” – Jeremy S. Anderson.

Ready for some radical, left-field (not to say left-wing) thinking? Believe in free love, sharing, and open markets? Step right this way. We’ve got something for you.

Oh, goody. It’s another new microprocessor instruction set.

The great minds at the University of California at Berkeley (that’s “Cal” to insiders) have added a lot to our community over the years. Berkeley was the source of some early RISC processor research and the birthplace of Sun’s famous SPARC processor. And its Big Kahuna, Dr. David A. Patterson, PhD., is professor (and former chair) of Computer Science at Berkeley, as well as being an IEEE and ACM Fellow and recipient of the John von Neumann Medal. You may know him as the Patterson in Hennessy & Patterson, authors of the authoritative computer design bible. A real computer nerd, in other words.

And what does a microprocessor designer and professor do when he’s not grading papers? He designs microprocessors, of course.

More accurately, he teaches his CSEE students how to design processors. And to that end, he and his graduate assistants created a teaching tool, a hypothetical CPU with a simple instruction set, easy-to-implement hardware resources, and a straightforward architecture that budding CPU designers could take hold of and run with. And they called it RISC-V.

As with so many other computer teaching tools (think UCSD Pascal), RISC-V escaped from the classroom and into the wild. So now it’s a real thing. And Dr. Patterson and members of his drum circle are beating the, uh, drum for RISC-V and promoting it as the go-to CPU architecture for everything from SoC to IoT. (If your lips are moving as you read this, be sure to pronounce it “risk-five,” not “risk-vee.”)

As you might expect, RISC-V (no relation to VISC from our November 26 issue) is a reduced instruction set computer, and very reduced it is. Patterson sees minimalism as one of its greatest strengths. After all, RISC-V was originally intended as a teaching tool, not a real processor, so it was deliberately kept simple. Conversely, RISC-V is also extensible, initially so that students could experiment with architectural enhancements, but now so that real designers can add their own features and functions.

Most of all, RISC-V is designed to be un-patentable. No patent or IP licensing is required to implement a RISC-V processor or to use its software tools. There are no “quirks” (Patterson’s word) in either the instruction set or its implementation that would require licensing. Just the opposite, in fact: RISC-V positively encourages designers to get creative with their hardware implementations.

The instruction set is designed to be simple (a RISC hallmark that most adherents have forgotten) and, therefore, straightforward to contrive in hardware. Unlike ARM’s inline shifter or MIPS’s math idiosyncrasies, there’s nothing in the RISC-V definition that requires secret (and legally protected) knowledge.

Patterson’s technical paper reads a bit like a manifesto for the cause of open source and free-market dynamics, advocating for RISC-V because it’s a good thing for the community (this is Berkeley, after all). He cites the restrictive licensing policies of ARM or IBM’s PowerPC, which limit the use of those architectures only to well-heeled commercial entities with $1 million to spend on a CPU license. What’s a poor academic to do?

The paper also name-checks OpenRISC and SPARC, two other examples of open-source CPUs that are similar in concept to RISC-V. So why not just use them? Why create yet another free-to-the-people processor when perfectly good examples already exist?

Because RISC-V is better, that’s why. Patterson identifies four key criteria needed to make an open-source processor popular in the real world, and – surprise! – RISC-V satisfies them all. Evidently single- and double-precision floating point aren’t enough; you need to have quadruple precision, too. And 32- or 64-bit addressing isn’t sufficient. You really need 128-bit addressing. Got code compression? RISC-V does but SPARC and OpenRISC don’t. And finally, a user-extensible instruction set, á la ARC or Tensilica, is necessary.

You can take a hit of RISC-V without losing your mind. It exists in varying levels of realness, from a quick Java simulation you can download from here, to a cycle-accurate C simulator, or a Xilinx FPGA implementation, all the way to the full Verilog implementation of a 64-bit chip of your very own.

So, like, what have you got to lose? It’s totally free. It’s direct from the professor himself, so it’s got to be choice. And it runs Unix, the second-most-important thing to come out of Berkeley in years.