Memristors as events integrators

As originally proposed by Chua, memristors are capable of changing their resistive state as a function of the integral of their input voltage; a phenomenon known as resistive switching25. As a result of this single-device integrator property, solid-state implementations of memristive devices26,27,28 have been at the center of attention, with potential applications in emerging memories and neuro-inspired computing29. In this work, we exploit metal-oxide-based resistive switches as neuronal spike integrators. Solid-state TiO x memristors with a metal-insulator-metal architecture, as shown in Fig. 1a, were fabricated on a Si/SiO 2 substrate; detailed process parameters appear under the Methods section. Subjecting the device-under-test (DUT) to a train of input programming pulses in alternating polarities gives rise to gradual resistive state transitions, provided the pulse amplitude exceeds the device’s inherent bipolar switching thresholds (fundamental properties of the device; denoted as V th− /V th+ ), as illustrated in Fig. 1b,c (see Methods). Here we argue that this capability for gradual switching can be exploited to encode multiple significant spiking events as small changes in a device’s resistive state. This assumption is first explored deterministically, by employing known pulse events. Figure 1d,e show the response of a typical DUT to trains of 200 identical square-wave events of negative and positive polarities30, respectively, as illustrated in the insets. Each writing pulse has a fixed 100 μs duration and suitable amplitude to induce a resistive state change. It is followed by a reading pulse of fixed 0.5 V amplitude and an automatically determined duration, t a (ref. 31). Notably, the pulse amplitude required to elicit a resistive state change of similar strength but in the opposite direction could differ, indicating an inherent asymmetry in the device’s characteristics. This bidirectional, gradual (analogue), saturating switching, could be fitted by second order exponential functions of input voltage integral (Supplementary Table 1), thus defining the input-output relation of an integrating sensor for distinct stimulation protocols. Notably, as our TiO x device prototype acts as a thresholded integrator, it can be described by the generalized definition of memristor as ‘zero phase-shift dynamic system’32. We name hereafter the device as memristive integrating sensor (MIS) and show that this thresholded-integrator attribute can be particularly useful for compressing information and suppressing noise in signals with low SNR, such as data recorded from the activity of neurons/cells. Hence, our approach only allows for significant, supra-threshold events to be registered as measurable changes in the device memory state, whilst sub-threshold events are suppressed.

Figure 1: Device architecture and electrical characterization of solid-state TiO x resistive random access memory devices. (a) Schematic illustration of a solid-state TiOx memristive device and atomic force microscopic (AFM) image of 32 × 32 crossbar array. (b,c) Resistive state changes (bottom trace) accumulate visibly, and in opposite direction depending on polarity, only in response to input pulses with above-threshold amplitudes (top trace; input writing pulses, V W+ and V W− , indicated in red and reading pulses of amplitude V a in light blue). In bipolar devices two inherent thresholds exist, one for each voltage polarity. For this device we obtained V th+ =+1.45 V and V th− =−1.65 V as indicated by the shadowed areas of the plot. (d,e) Show gradual resistive switching under a pulse train stimulation (200 pulses per train). The devices response is fitted with a second-order exponential function (continuous line). Typical biasing scheme parameters (insets): negative write pulse voltage V w− =−1.2 V, positive write pulse voltage V w+ =+0.8 V, read pulse voltage V a =0.5 V, write pulse width t w =100 μs and read pulse width t a automatically determined by the measurement system. Full size image

Neural spiking integration with metal-oxide memristors

The ability of memristors to integrate significant events provides an efficient way of encoding and compressing information on neuronal firing in real-time, as recorded by neuronal probes. The basic concept of the proposed MIS platform is exemplified in Fig. 2a. An external front-end platform (for example a MEA) senses neuronal electrical activity which is fed into the MIS system as a series of voltage-time samples. The MIS begins by pre-amplifying the incoming signal to voltage levels suitable for operating the memristor sitting at the core of the MIS and then proceeding to apply the pre-amplified signals to the memristor in real-time. Periodically, the memristor’s resistive state is assessed periodically and when a significant change in comparison to the previous state is detected, the system registers a spiking event.

Figure 2: MIS concept and operation. (a) Block diagram of the signal processing in the proposed spike-detection system. An external frontend (a CMOS MEA system) located externally to the MIS platform records extracellular neuronal signals and amplifies them. The pre-amplified, acquired neural recordings are then fed into our instrument, suitably gain-boosted (G) and offset (V off ) to render them compatible with the memristors’ voltage operating regimes (i). The conditioned waveform is fed into a memristor and its resistive state is then periodically assessed (ii). Changes in resistive state caused by spiking events are extracted offline (iii). (b) Conceptual read-out scheme for evaluating the time evolution of the resistive state of test devices subjected to input stimulation for one batch. The resistive state (red line) is assessed at the beginning of each neural recording batch (blue trace), then every chosen number of samples termed as bin (B) and finally at the end of each batch (assessment points marked by crosses). Changes in test device resistive state (ΔR) are extracted from consecutive resistive state assessments. Resistive state changes occurring between the last measurement of each batch and the first measurement of the next batch, with no interceding pulse biasing, (N) are considered to result from measurement uncertainty and can be used to determine the noise band. (c,d) Shows an arbitrary input waveform consisting of four concatenated copies of the same retinal cell recording and artificially inverted to produce spike trains with alternating polarities. This waveform was employed to validate the concept of memristive integrating sensors, the response of which is shown in d. The collated recording copies in c have been subjected to appropriate scaling and offsetting in order to accommodate the device’s asymmetric threshold voltages, resulting in balanced resistive state SET and RESET. The extracted threshold voltages are identified here as, V eth+ =1.1 V and V eth− =−1.4 V represented in the green and pink band, respectively; x axis for both (c,d) is given in S.I. units—each data sample lasts 82 μs (sampling frequency: 12.2 kHz). (e) Fractional resistive state modulation (ΔR/R 0 ) extrapolated from (d) showcasing significant resistive state modulation occurring only above V eth+ and below V eth− while intermediate bias values (noise) leads to no significant change. Full size image

We validated experimentally the MIS system implementation on spiking activity of retinal ganglion cells. At first, the activity of dissected retinal cells was pre-recorded by an external MEA front-end system2,33,34,35,36 (see Methods, CMOS MEA). The MEA employed records the raw bio-signals, which lie in the 0.1 mV–1 mV range, and then uses its own in-built amplifiers to boost them to the 10 mV–100 mV range. The resulting, boosted recordings are then stored off-line as voltage-time series. For this work, we have used these stored recordings as inputs to our MIS platform in isolation from the front-end, that is the front-end has not been connected to the MIS platform in real-time (Supplementary Fig. 3). The processing of neural signals through MIS platform begins when the stored voltage-time series are subjected to amplification and offset in software on the PC that runs the platform (Fig. 2a—box (i) and Methods section). This set-up offers the option of adjusting the MIS detection threshold and consequently allowing the integration of significant spiking events with a pre-determined SNR. For example in Fig. 2c, the offset and scaling parameters were chosen such that only the most significant events (largest amplitude extracellular spikes) would exceed the threshold. The resulting, pre-conditioned waveform is then transmitted from the PC to the memristor testing and operation instrument (see Methods, Hardware Infrastructure), which physically implements the MIS system. The instrument, in turn, plays back the waveform to a target memristive device.

In order to assess the distinct resistive state changes during the streaming of recorded neural activity (Fig. 2b—see Methods), the DUT is periodically disconnected from the neural signal feed, for example once every 200 input samples, and connected to a read-out circuit that captures the device’s state, digitizes it and subsequently sends the resistive state reading back to the PC. Importantly, only a limited amount of data is returned to the PC when compared with the full voltage time series in conventional systems (box (ii) in Fig. 2a and see Methods, MEA neural recording signal-processing). A software converts the incoming series of resistive state readings into a series of resistive state changes, subsequently keeping only the largest ones that are marking significant events in the neural signal (Fig. 2a marked (iii), Methods and Supplementary Fig. 6). Noteworthy this filtering process, based on an assessment of resistive state changes in absentia of an input signal (see Methods section) may be engineered in order to fine-tune SNR on neuronal activity.

Our effort to reduce data bandwidth echo current research in on-chip spike-sorting8, with our approach being disruptive in exploiting the inherent data-compression capability of highly scalable, low-power nanodevices that could extend the scaling and processing capacity of neural recording platforms substantially. Our approach reproduces in its essence the strategy adopted by natural synapses for signal compression, where information on spikes number and firing rate is stored into gradual changes of the postsynaptic membrane conductance. In contrast, present state-of-art neural activity monitoring platforms, like the MEA-based system described in ref. 33, rely entirely on front-end circuitry for detecting and transmitting all data offline for processing (Supplementary Fig. 7).

MIS system performance

MIS system performance was investigated in three separate experiments. First, the capability of handling input signals where neuronal spikes span both negative and positive voltages was tested including a repeatability check. Second, the spike detection performance was benchmarked against a state-of-art template-matching system22. Finally, robustness checks were carried-out.

In the case of in vivo recording spikes often span both negative and positive voltage polarities, depending on experimental conditions, for example the position of the recording electrode relative to neuronal compartments and their associated ionic conductances5,37. It is thus relevant to demonstrate the MIS operation for both signal polarities, as explored here at a proof-of-concept level. Figure 2c depicts a waveform consisting of four, concatenated copies of a retinal recording. Each copy was subjected to appropriate scaling and offsetting, and two of the copies were polarity-inverted. The corresponding resistive state transient response throughout this test is shown in Fig. 2d. Significant changes in resistive state correspond to clear, supra-threshold events. We demonstrate that spike detection successfully occurs at both polarities, achieving qualitatively similar modulation over two signals. This is better illustrated in Fig. 2e, where the normalized resistive state changes between consecutive reads is plotted as a function of the maximum voltage magnitude of interceding events. In the same figure, the grey horizontal band denotes resistive state changes that have been discarded (see Methods section). The remaining points are used to define the memristor’s effective operating threshold voltages (V eth+/− ), which partition the plot into three distinct areas: two of them correspond to significant resistive state modulation (larger than V eth− and less than V eth+ ) and the last one ([V eth+ , V eth− ]) containing resistive state changes that are indistinguishable from the estimated background noise. The range of effective threshold voltages for the TiO x prototypes employed throughout this study was −0.8 V to −1.8 V (Supplementary Fig. 2). Importantly, whilst the inherent threshold of the device performs a coarse filtering action, the effective threshold ultimately determines SNR. Moreover, since the MIS system detects normalized changes in the resistive state, this approach is inherently robust against the devices threshold variability as identified in Supplementary Fig. 2b.

The performance of the introduced MIS concept was benchmarked against a state-of-art template-matching-based system22 (Supplementary Fig. 7). The resulting performance comparison between the two approaches is presented in Fig. 3. In this case, we employed an offset (V off =0) and amplification (G=2.8) on the recording shown in Fig. 3a and the device’s resistive state was assessed as per the standard scheme described in the Methods section and in more detail in Supplementary Fig. 5. Figure 3b illustrates the resistive state evolution of the tested MIS in response to the input signal shown in Fig. 3a. One can observe clear changes in the device’s resistance corresponding to spiking events whose magnitude exceeds V eth− , in a similar manner to the first period of events shown in Fig. 2c,d. In this example, the incoming spikes mainly occur in negative polarity hence there is an overall inscrease in resistance, from approximately 2.5 to 5.5 kΩ. However, the presence of a few events in opposite polarity that exceed V eth+ , cause occasional resistive state drops. A clear example indicated by ϕ in Fig. 3g,h can be observed at ∼1.4 s in Fig. 3a,b,e,f where the resistive state reduces from ∼4.5 to 4 kΩ. However, optimizing the value of V off provides additional flexibility for compensating for this effect. Noteworthy, as the MIS is capturing and storing significant events as non-volatile resistive changes, one can afford to use relatively low sampling rates for minimizing the overall requirements in data storage/handling. Along this line, the output of our system is quantified at discrete time bins containing one or more detected events (see for example Fig. 3e, f–h at ∼0.96 s). For this recording, our system identified 74 bins containing significant events denoted in Fig. 3d, while the template-matching-based system overall distinguished 81 significant events shown in Fig. 3c. Comparing the MIS and template-matching approaches within a representative time-window of 1 s duration, indicates a similar performance in spike detection, as noted via asterisk symbol (*) marks in Fig. 3g,h. It is interesting to note that our approach results into registering apparent events (for example at 0.83, 1.05, 1.1 s) that are missed by the template-matching method while it fails recognizing other possible events (for example at 0.59, 1.22, 1.25 s), presumably due to a conservative selection of signal conditioning gain. Overall, benchmarking the efficiency of the MIS approach indicates a rate of true positives of ∼60%, (Supplementary Fig. 6) assuming that the template-matching approach is an ideal spike detector.

Figure 3: Benchmarking memristor-based system against state-of-art template matching system. (a) A pre-conditioned neural recording trace with gain and offset value of 2.8 and 0, respectively, causes the resistive state time evolution shown in b. (c) Eighty-one spikes were detected by the template matching system, with grey lines indicating spike positions. (d) Green shading indicates time intervals within which one or more spikes were detected through the MIS; total of 74. (e,f) are close-ups of the neural recording and resistive state evolution shaded grey in a,b, respectively. Time intervals where the MIS detects spikes are shaded green while the locations of spikes detected by the template matching system are indicated by grey vertical dashed lines. (g,h) Comparison of the detection of spikes by the two systems. The asterisk mark (*) indicates agreement between the two systems and the ϕ symbol indicates the resistive state drop associated to the occurrence of a large-amplitude positive event. Full size image

The robustness of the observed behaviour and its potential for data compression via improvement of SNR is further demonstrated by showcasing: (a) the response of a single MIS to blocks of neural recording data containing significantly different patterns of activity (Fig. 4a–d) and (b) the response of different devices to a common neural recording obtained from MEA as exemplified in Fig. 4e–h. In the former one device—many recordings case we observe how intense activity leads to a larger overall resistive state modulation and how particularly strong events tend to cause distinct non-volatile changes in memory states. Thus, resistive state traces compress information on both the firing rate and spikes amplitude. Instead, in the latter one recording—many devices case we observe that despite the quantitative variability in device behaviour, most of the marked resistive state transitions tend to concur in time with significant events present in the input waveform (see also Supplementary Table 2).

Figure 4: Robustness of memristive devices. (a–d) Response of a single memristor (c,d) to two blocks of neural recording data (a,b) containing significantly different patterns of activity. The pink band indicates the extracted threshold of the device-under-test (V eth− ). The respective figures indicate quantification parameters, that is rate of true positives (TPR) and false positives (FPR), respectively. (e–h) Response of two different devices (g,h) to a common reference block of neural recording data represented in e,f. Initial resistance of device was set to ∼5 kΩ. In all these experiments, signal conditioning parameters, that is software added gain and offset remained fixed at G=2.2, V off =0, respectively. Full size image

Towards array-level MIS operation

The concept introduced in Fig. 2a, when directly interfaced with front-end-circuitry, can be exploited for advancing the present state-of-art in high-density neural recording platforms38. The presented concept is amenable for scaling to a multi-channel array level, as illustrated in Fig. 5a, for capturing the activity of neural networks in real-time. We envisage an overall system architecture very similar to standard active pixel sensor CMOS imagers39. In this hybrid system, data from each of the N pixels in the array arrives as an analogue current from the MEA and is multiplexed onto one of the M on-chip trans-impedance amplifier (TIA) blocks, which are followed by on-chip offset stages. Thus, a small number of both gain and offset stages are time-shared by every pixel in the array. The conditioned recording data points are then de-multiplexed to a memristor bank, that can be integrated into the back-end of the chip, in good proximity to the MEA recording sites. MIS output is then generated by sequentially measuring the resistive states of each memristor in the bank. The low frequency at which memristor read-outs are generated (for example 200 times lower data rate vis-à-vis input stream arriving from the MEA if a standard scheme is used as described in Methods section) allows the MIS system to carry out all measurements through a single or few, time-shared TIA feeding into analogue-to-digital converter. The digitized results are then sent off-chip. We foresee that, a practical implementation of a monolithically integrated system will involve addressing the challenges associated with the integration of a MIS array with CMOS-based front-end circuitry, while the required MIS control can be accommodated as peripheral circuitry with sneak-path issues existing in dense resistive random access memories crossbar configuration mitigated via selector topologies40.

Figure 5: Towards array level integration. (a) Conceptual diagram indicating conditioning of data from N pixels through multiple gain and offset cascade (M). (b–d) Time evolution of normalized resistive state throughout 16 × 14 test sub-array at t 1 =1.63 s, t 2 =3.27 s and t 3 =5.16 s, respectively. The gain and offset values for the neural recordings was fixed at 2.8 and 0, respectively. Three clusters of activity can be discriminated. CMOS MEA, multi-transistor array block, manufactured in standard, commercially available CMOS technology. TIA, trans-impedance amplifier converting current to voltage with appropriate amplification. Full size image

In this work, this concept was validated via a hybrid approach that is capable of processing 224 distinct recording traces stemming from a 16 × 14 pixel subset of the previously employed MEA system2,34, atop which retinal ganglion cells were cultured. The sub-array was found to cover three cells after processing all recordings with a state-of-art array-level template matching system, using an extended principal component analysis method (described in Supplementary Fig. 8). As before, an initial MIS calibration was performed in order to set suitable values for G and V off . This entailed selecting a spatially sparse subset of 23 pixels (see Supplementary Fig. 9, cells marked in orange), and examining their recording waveforms to gauge average maximum/minimum voltage amplitudes as well as the typical levels of background activity. In this experiment, we particularly set G=2.8 and V off =0 for all memristive devices to ensure a suitable SNR. These parameters were kept fixed for all recordings, they were not changed for accommodating individual memristive device behavioural variations, or distinct features of the employed recordings. Every utilized memristive device was initialized to a common low-resistive state (Supplementary Fig. 1) in the range of 2–4 kΩ that for the given parameters yielded a useful MIS operating range up to the set 15 kΩ high-resistive state.