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Today, if you want to build a high-performance computing device, you can almost certainly find all the software you need in a free and open form. The same is not true for the processor chips that run that free software — whatever you choose, a chunk of what you pay will go on proprietary hardware licences to Intel, ARM, or their friends.



RISC-V, pronounced 'Risk-Five', is a new architecture that's available under open, free and non-restrictive licences. It has widespread industry support from chip and device makers, and is designed to be freely extensible and customisable to fit any market niche. To be a success, however, it has to perform technically as well as be economic to design for, verify and program. It has enthusiastic supporters, but it also has enormous competition that has been dug into the very heartland of IT for decades.

RISC in history

One of the foundational truths of computing, first revealed by Alan Turing, is that any computer can theoretically tackle any problem. Another is that if you can do it in hardware you can do it in software, and vice-versa. Real-world systems, however, are constrained by speed, efficiency and resources. Different processor architectures make different trade-offs.

In the 1980s, there was a battle between chips with multiple special-case hardware units to cope with particular situations — CISC, or Complex Instruction Set Computing — and those that kept the hardware simple, fast and general-purpose, and left the complexities to software.

That approach, called Reduced ISC or RISC, seemed to lose out at first, as Intel rose to overlord status with its x86 CISC chips. RISC chips, such as Sun Microsystem's SPARC and IBM's PowerPC, waxed and waned but never overcame Intel — which was symbiotic with Microsoft's heavily Intel-centric Windows. Under the hood, though, Intel's chips were remarkably RISC-like, with the CISC features translated into RISC instructions internally. The mobile market, which evolved independently of Windows, soon settled on ARM chips, which used RISC design to be far more power-efficient. RISC can be said to have won the case across the board.

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For 21st-century hardware designers, though, both x86 and ARM chips have a major drawback: cost. That cost isn't just for the silicon, it's for the intellectual property, primarily patents, that the big companies hold and charge for — ARM through licensing thousands of partners, Intel by existing in an uneasy duopoly with AMD.

RISC-V aims to break up the proprietary hold on processor design in exactly the same way that open-source software liberated huge swathes of the industry.

Image: RISC-V Foundation

RISC-V technical

RISC-V is a classic RISC architecture rebuilt for modern times, and gets its name as the fifth major RISC architecture to come from University of California, Berkeley.

At its heart is an array of 32 registers containing the processor's running state, the data being immediately operated on, and housekeeping information. This array is large enough to minimise the need to access external memory for a lot of basic CPU tasks, which reduces energy use and increases speed. RISC-V comes in 32-bit and 64-bit variants, with register size changing to match. A 128-bit version is underway.

The instruction set — the low-level commands the processor can directly interpret — is very simple and very modular. A RISC-V core can be built with just simple integer instructions, without even multiply or divide. Or it can have those added, floating-point extensions (with another 32 registers), and compressed instructions.

Compression is a key part of RISC-V. The original RISC concept achieved speed by having its instructions coded into a form that was very easy and quick for the hardware to decode and execute — no special cases, everything fitting into a single framework. This, however, can be very inefficient in memory usage as the instruction template has to cater for all possibilities whether a particular operation needs them or not.

Compression breaks that rule, and lets a compiler fit a lot more instructions into a given area of memory. Instructions are variable length, as they are in x86 CISC. Unlike x86, though, which was created piecemeal over many years, the RISC-V variable length schemes are designed from the outset to give the processor hardware as easy a time as possible in knowing how long they are and letting it quickly decode them while managing its internal instruction queues. Queue management is where most modern processor architectures get their speed.

The core RISC-V specification is certified to be free of patent encumbrance, and is licensed under Creative Commons CC BY 4.0. This doesn't require or mean that extensions have to be similarly free and open — designers can include licensed aspects in their additions if they wish. The key point is that the architecture is extensible without losing efficiency.

Image: RISC-V Foundation

RISC-V practicalities

The RISC-V Foundation has more than 200 members, including Samsung, Google, Nvidia, Western Digital, NXP, Micron and Qualcomm, not to mention Raspberry Pi. The full list includes many universities, telcos, chip manufacturers and those who produce design and verification tools — essential if the core spec is to turn into real cores.

Actual hardware and software is thin on the ground. The RISC-V website lists a number of design tools, boot builders, programming languages and operating systems — including Fedora Linux — of mixed stability and functionality. There are a number of chip simulations, designs that can be put into an FPGA programmable logic chip, or even turned into a full custom chip if you have the technology and knowledge, but only six actual chips announced. Availability is definitely ask-first.

However, one company set up explicitly to support RISC-V chip production, SiFive, has an online chip-design tool that builds a custom chip based on a large number of options. The company has already shipped 2,500 development boards, and provided the design for what's claimed to be the first RISC-V chip in a consumer product, the Huami Amazfit fitness band.

Both Western Digital and Nvidia have said they'll be using RISC-V in the very near future; Nvidia is replacing its proprietary Falcon embedded controller used for management in its graphics cards, while Western Digital says it will start using RISC-V controllers in some of its disk drives from 2020.

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NXP has produced VEGAboard, a development board containing two RISC-V cores alongside two ARMs, but at the time of writing has no stock and will only give it to qualified academics or developers — it's not (yet) for sale.

RISC-V is also a Brexit beneficiary. After fighting for years to get major funding for a European High Performance Computing project built on EU technology and thus based on ARM, Mateo Valero, the founder and director of the Barcelona Supercomputing Center, told the RISC-V Workshop in Barcelona, May 2018, that it all went wrong in a couple of months.

"After convincing the European politicians, what happens? Brexit and Softbank [the Japanese company that bought ARM in July 2016]. So ARM is not European any more".

As a result, the European Processor Initiative — announced in 2018 — was set up to create a native European hardware accelerator architecture, based on RISC-V. Initial products are expected in two years, with the aim of giving Europe the third fastest supercomputer in the world.

Image: Western Digital

RISC-V: will it win?

These is no doubt that RISC-V is in a very strong technical position, building on decades of practical architectural experience and attracting support from across industry. But there is a huge leap from being adopted as an embedded core in standalone devices to building the sort of ecosystem where the cost and performance advantages outweigh the risk of not having fully validated, off-the-shelf solutions for bus design, interoperability and long-term support. There is still no certification process, no standardisation for part families or packaging, and no plug-and-play at any point of the hardware or software stacks.

But the same was true for Linux, at the start. Successful models exist to achieve all of the above, through open cooperation across industry players large and small. Attendance at RISC-V events is growing rapidly. There is a lot of work to do, but a lot of resources, motivation and skills are being committed to do it. RISC-V may fail to meet its potential, for many reasons, but no new architecture in decades has had as good a chance of success.

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