New leaks from VIA’s CPU subsidiary, Centaur Technologies, are turning heads as it looks as though the company’s upcoming Isaiah II processor could seriously challenge both Intel and AMD. In a comparison against various SiSoft Sandra tests, the new VIA Isaiah II sample (running at less than 2GHz with reported support for AVX2 and 64-bit computing) was able to surpass the Intel Atom Z3770 (Bay Trail) and compared well against the AMD Jaguar (25W TDP).

We don’t know what the TDP looks like on the Isaiah II and it’s hard to draw firm conclusions from early sample data. The core’s oddly low multi-core efficiency could easily be caused by its engineering sample status. VIA’s history, however, demonstrates that the company is capable of designing competitive processors. When Intel first announced the original Atom, VIA quickly countered with a chip it called Nano. The Nano was, in many ways, an excellent processor, but it never saw much sales traction or competitive adoption. At the time, it was VIA’s big step up from the low-power C7 family into a more capable product — but volume shipments never materialized and the HP 2133 update that was rumored to use a Nano instead of VIA’s C7 went with an Atom instead.

Does VIA have a secret weapon up its sleeve?

Over the long holiday weekend, we got an interesting email from reader Juraj Tralalak, pointing us to a patent VIA received three years ago for a combined x86/ARM microprocessor. Some of you may recall that we explored the idea of how AMD might build a combined x86/ARM design for a 2016 release date — VIA’s patent appears to cover one of the methods we discussed for constructing such a processor.

Specifically, this VIA patent describes a chip that can translate ARM and x86 instructions into a third, internal set of microinstructions. This isn’t a dramatic departure from how current x86 processors function — only Atom still uses native x86, all other AMD and Intel chips translate native x86 commands into an internal set of instructions. What Centaur/VIA describe is a method that would allow the native ISA (x86 or ARM) to be set at device boot, with the chip then translating and executing either ARM or x86 commands thereafter. The native x86 and ARM instructions would be cached in an instruction cache and handed over to a translation circuit as needed.

The diagram above shows a proposed register design divided into sections that would be shared between x86 and ARM as well as the segments unique to both. VIA filed for the patent four years ago — with a new chip coming from Centaur in 54 days, a four-year lead time isn’t impossible for a new architecture that uses aspects of this type of design. One very important question, however, would be whether or not the chip was compatible with ARMv7 or ARMv8. If VIA did built a chip based on this patent, it would presumably have waited until it could assure ARMv8 compatibility — launching an ARMv7 part at this point would be a mistake, in our opinion.

Just to be clear, we’re not claiming that the countdown on Centaur’s website refers specifically to a hybrid ARM/x86 core — just that it’ll be interesting to see if the company’s upcoming hardware is based on the architecture described above.

In terms of the leaked benchmark figures, given how well the Nano performed against the Atom, it is entirely possible that the Isaiah II will actually be a very competitive chip. Before we get too excited, though, we need to see VIA actually ship commercial volumes of the chip. The low-cost Nano-based HTPC boxes that lots of people were salivating over never materialized. Hopefully Isaiah II won’t suffer the same fate.