The Future of AMD, Chiplets, 3D Stacked Memory and moving past Moore's Law

AMD's latest slide deck reveals a lot about the company's future plans.

| Source: AMD Skip to content 2019 Rice Oil & Gas HPC Conference Slides Author: Mark Campbell

The Future of AMD, Chiplets, 3D Stacked Memory and moving past Moore's Law

Moore's Law is dead; it is hard to deny this fact. Transitions to new leading-edge process nodes are taking longer than longer with each generation; these shifts often result in a new competitor removing itself from the market. Leading-edge silicon is an expensive and cut-throat business.



With the move to 7nm, Globalfoundries was forced to remove itself from the leading-edge silicon race, leaving TSMC and Samsung as the world leaders when it comes to chip manufacturing. Yes, Intel is there too, but they are hardly worth considering given their lack of interest in producing hardware for 3rd parties.



To counteract the so-called "slowing down" of Moore's Law, product designers need to think smarter, relying on architectural advancements and multi-chip technologies to deliver the performance increases that node shifts previously offered. Today, product design is more critical than ever, but to truly scale future chips will need to work together and form a larger whole.



At the Rice Oil and Gas HPC Conference, AMD's Forrest Norrod hosted a talk which was called "Evolving System Design for HPC: Next Generation CPU and Accelerator Technologies", where he discussed AMD's future hardware design.



In this talk, Norrod explained why the multi-chip approach was necessary with EPYC and why their Chiplet-based approach is the way forward with their 2nd Generation EPYC processors. 3D packaging technologies were also briefly referenced, pointing towards a memory technology which appears to move beyond HBM2.







Monolithic dies have their benefits, but moving forward it is clear why things need to change. We cannot rely on node transitions alone to create products with more transistors and increased performance. Simply put, we can't scale chips past a certain size, and the expense of large chips makes for a difficult pill to swallow for customers.



The industry needed a way to scale products to offer increased performance while delivering high silicon yields and low product pricing. This is where AMD's MCM (Multi-Chip-Module) designs come into play, allowing the company's first generation EPYC processors to scale to 32 cores and 64 threads, utilising four interconnected 8-core processors to do so.









Moving forward, AMD plans to take things one step further. Instead of merging four identical chips together, why not design several chips that are explicitly designed for specific tasks? Through this, AMD's second Generation EPYC and 3rd Generation Ryzen products will offer increased scaling and allow each piece of silicon to be optimised to deliver the best latency and power characteristics.



Using smart design techniques and processor "chiplets", AMD's Zen 2 architecture is designed to scale far beyond its predecessor, using small, high-yield chips using both cutting-edge 7nm and affordable 14nm process nodes. With this cutting-edge design, AMD hopes to deliver incredible performance levels and reasonable pricing to both desktop and enterprise customers.









Perhaps the most exciting part of AMD's slides is their "memory innovation", which explicitly mentions "On-Die 3D Stacked Memory". This feature is "in-development" and should not be expected in any soon-to-be-released products, but it points towards a future where AMD has truly three-dimensional chip designs.



In many ways, AMD's On-die stacked memory makes us think of Intel's Forveros technology, though given what little information AMD has supplied here, we cannot draw any firm conclusions regarding the technology. Should we expect future AMD chips to offer a large amount of low-latency memory on their future CPU dies?







With their Zen 2-based products, AMD plans to deliver PCIe 4.0 to the masses, before Intel has an opportunity to deliver the high-speed interconnect to their customers. Even so, AMD is looking further ahead and at the future of product interconnectivity.



In the slide below, AMD claims that CCIX and GenZ support is "coming soon", hinting at (but not confirming) that the company's Zen 2 products will support these new interconnectivity standards. Intel announced their CXL connectivity standard earlier this week, but it looks like AMD may have beaten them to the punch with CCIX and GenZ support.









In mid-2019, AMD plans to release their EPYC "ROME" series processors, the world's first 7nm datacenter CPU, which is said to offer 2x as much performance per socket as their last-generation products and up to 4x as much Floating Point performance per socket vs their previous generation products.



With up to 64 cores and 128 threads, increased instructions per cycle (IPC) and PCIe 4.0, AMD hopes that their next-generation EPYC processors will revolutionise the datacenter market, securing the company a position within one of computing's biggest growth market.









You can join the discussion on AMD's future product plans over on the OC3D Forums.

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