One of the great and often unknown elements of the Vivado Design Suite and Vitis Unified Software Platform is how easy it can be to create a complex application.

The SP701 board is designed for industrial applications, including image processing. To support this, it contains both an MIPI CSI interface as well as MIPIDSI and HDMI outputs.

Creating image processing systems can be complex so you need to configure the input image capture stream, implement image recovery (e.g. demosiac to convert raw data to RGB pixels), frame buffers using VDMA, and finally create the image output path.

Architecting this image processing pipeline and configuring the settings can be time consuming.

However, if you have an SP701 board, there is a much faster way to get an image processing system up and running. Simply open the example design that's provided with the MIPI CSI-2 RX subsystem.

To get started with creating this example, first we need to create a new project targeting the SP701 board. From the IP library, add in the MIPI CSI-2 RS subsystem.

Once this is added into the project, double click on the MIPI IP core under the design sources. This will enable it to be reconfigured. Leave the configuration as is with its default configuration and then select the application example design.

On the application example tab, select the SP701 from the target board menu before clicking OK and closing the MIPI CSI-2 dialog box.

With the example application set for the target board, the next step is to right click on the MIPI CSI-2 block under the design sources menu and select Open IP Example Design.

This will prompt you for the location to save the example project before opening a new Vivado project which implements an image processing application, including the CSI-2 input configured to be used with the Pcam 5C and outputs images over DSI and HDMI.

Creating the example design will take a few minutes, but once created, the block diagram will show a comprehensive image processing solution.

Within this block diagram you will notice the MIPI input path is followed by a demosiac to convert from raw pixels to RGB and a VDMA to store the frames in external DDR.

The output path uses an AXI Stream switch to enable the read channel from the VDMA to be routed to either the DSI output or HDMI output.

If the DSI output is selected, the image stream passes through a video processing subsystem before the DSI IP core.

When the user selects the HDMI output, the image stream is passed through a test pattern generator and color space converter, before being converted from an AXI Stream to parallel video. This parallel video drives the HDMI transmitter on the SP701 board.

To control the DSI, CSI and HDMI configuration, I2C buses are used and the design provides three I2C output interfaces, along with the necessary GPIO for the sensor and DSI display.

Of course, controlling all of this is a MicroBlaze processor, while the MicroBlaze application and image frame store is provided by the Memory Interface Generator connecting to the external DDR.

Overall design

Input image processing to VDMA

Output processing system

Once the hardware is built, we can export the XSA and start working with the application software in Vitis.

When the example is created, all the necessary application software is also provided so we just need to create a new workspace and the import from the SW directory with the following:

HW_Description

Embedded_System

This will pull through all the application software, so we then need to create a system debug configuration and run the application on the target hardware.

Of course, we need to make sure we have the HDMI, Pcam 5C, and DSI display connected to the SP701 board before we power on the board.

By running this on the hardware, I could connect over the UART and select the image processing path to be Pcam 5C to HDMI.

I was then able to capture the following images of my lab and display them on my HDMI monitor.

Now that we have the image processing pipeline working quickly, we can start developing more advanced applications using this as a base!

See My FPGA / SoC Projects: Adam Taylor on Hackster.io

Get the Code: ATaylorCEngFIET (Adam Taylor)

Access the MicroZed Chronicles Archives with over 300 articles on the FPGA / Zynq / Zynq MpSoC updated weekly at MicroZed Chronicles.