High-Level Synthesis (HLS) is one technology which throughout my engineering career has always been just around the corner. I first started in engineering back in 2000 as a graduate for Raytheon and remember sitting in a presentation just after I started on what was then called Handel C. While sadly the industry did not adopt Handel C on a large scale, here in the UK it became very popular in the academic community and is indeed still available in an evolved format today.

Today HLS has broken through into the main stream with FPGA vendors and EDA companies offering tools which convert C, C++, System C and Matlab into FPGA bit streams. Another inflection point has been reached with the advent of System on Chip (SoC) devices that tightly couple both processors and programmable within the same die. The ability to program both the processor and programmable logic in the same high level language would bring a number of benefits — the two most apparent being reduced time to market associated with higher level languages and design reuse between processor and programmable logic.

But what if we could design both the processor and the programmable logic not only with the same high level language but also with the same tool and move design elements from one side to the other with ease to ensure we could meet the performance requirements of the system?

One such tool which has just been released by Xilinx: SDSoC supports both the Zynq SoC and MPSoC and is based around the very popular Eclipse tool. SDoC is highly integrated with both Vivado HLS and Vivado (although the user never actually sees them) and enables the user to create complete SoC designs generating both the software application and the SoC configuration file (think bit file) utilizing both the processors and the programmable logic.



SDSoC welcome screen

What is really cool is that SDSoC gives us the engineer the ability to move design elements from the processor to the programmable logic side of the design to increase the performance by moving computationally complex functions into logic. It does this seamlessly for the end user — instantiating the control and communication flow between the PS and the PL using its connectively framework.

At the highest level developing an application in SDSoC follows the following stages:

Develop the application within C or C++

Profile the system performance

Accelerate functions in the programmable logic as indicated from the system performance, iterating as required until desired performance is achieved.

Create the final application build containing both the SW and Programmable logic design.

To do this SDSoC comes complete with a number of support libraries and support for three operating systems BareMetal, FreeRTOS and Linux. Of course the inclusion or not of different operating systems will have an impact on the application response time.

Over the next few blogs I intend to create a simple demonstration of a commonly used embedded system algorithm within SDSoC initially with it just running on the processor and then accelerating it within the programmable logic such that we can see the highs and the lows of using SDSoC in our application.

However what algorithm will I implement? Having thought a little about the algorithm, I wonder if the readers of this columns would like to select the actual algorithm implemented using SDSoC from those below:

Finite Impulse Response Filter – Commonly used for filtering signal received from an ADC however this example would focus upon SINC correction for a DAC.

A complex mathematical transfer function – Used in telemetry and control systems

Of course you are free to suggest another algorithm but please remember I have a day job as well.