At a special event last week, TSMC announced the first details about its 5 nm manufacturing technology that it plans to use sometime in 2020. CLN5 will be the company’s second fabrication process to use extreme ultraviolet (EUV) lithography, which is going to enable TSMC to aggressively increase its transistor density versus prior generations. However, when it comes to performance and power improvements, the gains do not look very significant.

Just like other fabs, TSMC will gradually ramp up usage of ASML’s Twinscan NXE:3400 EUV step and scan systems. Next year TSMC will start using EUV tools to pattern non-critical layers of chips made using its second-gen 7 nm fabrication technology (CLN7FF+). Usage of EUV for non-critical layers will bring a number of benefits to the CLN7FF+ vs. the original CLN7FF process, but the advantages will be limited: TSMC expects the CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. TSMC’s 5 nm (CLN5) technology will increase the usage of EUV tools and this will bring rather massive advantages when it comes to transistor density: TSMC is touting a 1.8x higher transistor density (~45% area reduction) when compared to the original CLN7FF, but it will only enable a 15% frequency gain (at the same complexity and power) or a 20% power reduction (at the same frequency and complexity). With the CLN5, TSMC will also offer an Extremely Low Threshold Voltage (ELTV) option that will enable its clients to increase frequencies of their chips by 25%, but the manufacturer has yet to describe the tech in greater detail.

The rather small, incremental improvements that TSMC is discussing for the CLN7FF to CLN7FF+ and CLN7FF+ to CLN5 transitions indicate that it gets increasingly harder to offer decent gains from generation to the next. It remains to be seen whether all of TSMC’s leading-edge customers will keep adopting all the latest process technologies that the company offers, or will miss certain cycles given small incremental increases, but large companies (such as Apple) adopted all the latest fabrication processes in the recent years (i.e., it made economic sense to adopt them).

Advertised PPA Improvements of New Process Technologies

Data announced by companies during conference calls, press briefings and in press releases TSMC 16FF+

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20SOC 10FF

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16FF+ 7FF

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16FF+ 7FF

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10FF 7FF+

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7FF 5FF

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7FF Power 60% 40% 60% <40% 10% 20% Performance 40% 20% 30% ? higher 15% Area Reduction none >50% 70% >37% ~17% 45%

Moving on to the readiness of TSMC’s process technologies with EUV, “Foundation” IP for CLN7FF+ has been validated in silicon, but various important blocks required for 28–112G SERDES, embedded FPGAs, HBM2, and DDR5 interfaces will not be ready before late 2018 or even early 2019. Fully certified EDA flows for CLN7FF+ will be ready by August. Meanwhile, EDA flows for CLN5 are in their infancy: version 0.5 will be ready by July and numerous IP blocks (PCIe 4.0, DDR4, USB 3.1, etc.) will not be ready until 2019.

Next up is equipment readiness. As reported, TSMC is building a separate fab to make chips using its CLN5 process technology. The new Fab 8 will use numerous Twinscan NXE:3400 scanners, but TSMC admits that at present the average daily power levels of the light sources for their EUV tools is only at 145 W, not enough for commercial usage. Some of the tools can sustain 250 W production for a couple of weeks and TSMC has plans to hit 300 W later this year, but EUV tools still need improvements. There are also some issues to be solved with things like pellicles (they transmit 83% of EUV light and are expected to hit 90% next year), so EUV lithography in general is not ready for prime time just now, but is on track for 2019 – 2020.

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