As Moore’s law has slowed, manufacturers have turned their attention to optimizing other aspects of their devices. Shrinking transistor designs and building smaller chips no longer delivers the performance and efficiency improvements that it once did. Improvements in packaging technology, on the other hand, offer real potential for performance gains and power consumption reduction.

At Semicon West, Intel unveiled multiple new tools in its proverbial toolbox for addressing advanced packaging questions. In the past, we’ve discussed Intel’s two-dimensional technology for connecting technology packages (EMIB, aka Embedded Multi-die Interconnect Bridge) and the three-dimensional technology it uses for upcoming parts like Lakefield (Foveros):

Now, Intel has unveiled a new system that allows it to deploy EMIB and Foveros together, in the same package. Dubbed Omni-Directional Interconnect (ODI), Intel claims it’ll be a major differentiating feature in the years to come.

“Our vision is to develop leadership technology to connect chips and chiplets in a package to match the functionality of a monolithic system-on-chip,” said Intel corporate vice president Babak Sabi. “A heterogeneous approach gives our chip architects unprecedented flexibility to mix and match IP blocks and process technologies with various memory and I/O elements in new device form factors.”

Intel has distributed a video showing how EMIB, Co-EMIB, and Foveros can be combined to create a single product. As a refresher, EMIB is a very small interposer layer embedded in a substrate. This layer connects to two PHYs and provides the same type of physical connection as an HBM interposer at a fraction the cost. EMIB is said to cost 0.3 picojoules (pJ)/bit of data transferred. Foveros, which allows Intel to stack chips in 3D face-to-face stacks, allowing for higher density scaling and even thinner bump pitches. Power cost for transferring data via Foveros is said to be even smaller than EMIB, at 0.15pJ/bit. Co-EMIB combines Foveros and EMIB in the same technology and deployed as part of the same design.

Omni-Directional Interconnect allows for top-packaged chips to communicate with other chips horizontally, similar to EMIB, or vertically, through TSVs, similar to Foveros. One unique feature of ODI, however, is the use of large TSVs to deliver power to the top of the die. Intel writes: “Much larger than traditional TSVs, the large vias have lower resistance, providing more robust power delivery simultaneously with higher bandwidth and lower latency enabled through stacking. At the same time, this approach reduces the number of TSVs required in the base die, freeing up more area for active transistors and optimizing die size.”

Intel also outlined a new approach, MDIO, which builds on its Advanced Interface Bus and offers 2x the pin speed and overall bandwidth density.

The cynical way to look at this situation is that Intel is pushing to talk about its packaging improvements because it doesn’t have CPUs to boast about. There’s undoubtedly a little truth to this situation — but less than you might think. Experts have been predicting that companies would shift to packaging optimization as Moore’s law slowed down for years. AMD’s own move to chiplets is an example of how companies of every sort, including those undeniably on the top of their game, are exploring new technologies. And the drive towards exascale requires that we find ways to move data from Point A to B with ever-smaller amounts of electricity.

There’s no word on when we’ll see products coming to market using technologies like Co-EMIB or ODI, but Intel is already discussing them in reference to its own chiplet plans. It wouldn’t be crazy to suspect a link between the two.

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