Yesterday AMD released a new roadmap during its Q4 2015 conference call. In most respects this roadmap differs little from AMD’s prior roadmap but AMD has updated its roadmap confirming the name of its next-gen APU “Bristol Ridge” and its first Zen-based CPU “Summit Ridge”. AMD has also added an entirely new slide highlighting the company’s focus on offering products for the highly lucrative data center market.

AM4, Bristol Ridge, and Summit Ridge on the Desktop

In AMD’s prior roadmap there was no specific codename listed for their 7th Gen A-Series Desktop and Mobile APUs. In the current roadmap AMD has confirmed what has more less been public knowledge for some time now, Bristol Ridge will be the follow on to Carrizo. As had also been rumored Bristol Ridge appears to be a refresh of Carrizo given that AMD has not announced any new CPU cores other than Zen and K12 and Bristol Ridge is clearly listed a non-Zen based product.

What process node and what generation of GCN graphics cores that Bristol Ridge will offer remains a mystery. AMD’s roadmap does promise that Bristol Ridge will offer performance-per-watt gains. Whether this is in comparison to its old Kaveri APU or to Carrizo isn’t clear. Additionally AMD has provided no information on whether Bristol Ridge will hit the desktop as a full on SoC (System-on-Chip) like Carrizo or as a more typical APU + Southbridge design like its previous desktop APUs. On the mobile side it seems clear that Bristol Ridge will follow in Carrizo’s footsteps and be offered as a pure SoC in the FP4 socket.

This roadmap also defines exactly how AMD will be reducing the number of sockets used by its products like they announced at CES earlier this year. For its desktop products there will be a single socket dubbed AM4. Very little is known about AM4 other than it will support chips with both DDR3 and DDR4 memory controllers. In a perfect world AMD would use AM4 to bring itself to parity with Intel in the desktop space by finally making the transition from a PGA (Pin Grid Array) socket to an LGA (Land Grid Array) like Intel’s been using since 2004.

UPDATE 1/28/16: I talked with AMD early this week and they confirmed that while products designed for the AM4 socket will contain DDR3 memory controllers they will not be enabled. Motherboard that use the AM4 socket will only support the use of DDR4 memory. Additionally both Bristol Ridge and Summit Ridge will be SoCs.

AM4 will support both its AMD’s Bristol Ridge APU which is set to launch in the middle of 2016 and its first Zen-based CPU named Summit Ridge which will arrive on the desktop in Q4. Bristol Ridge will offer compatibility will both DDR3 and DDR4 memory in the AM4 socket and Summit Ridge will only offer support for DDR4. Memory bandwidth has consistently placed a hard limit on the graphics performance of AMD’s APUs so the transition from DDR3 to DDR4 should allow AMD to offer a considerable jump in graphics performance of its upcoming APUs.

AMD Prepares to Attack the Datacenter Market

If you managed to read this far into the article then you’re in for a treat. By far the most interesting piece of AMD’s updated roadmap is the new slide laying out its data center efforts. AMD’s roadmap lists three separate products that it will be using to capture marketshare: Zen-based Opteron chips, K12-based high performance server chips, and a high-performance server class APU. All of these chips have been hinted at in their own way and based on the information that SemiAccurate has found hints of they will be delivered throughout 2017 in the order that I listed them.

The Zen core will first launch in late 2016 on the desktop inside of the Summit Ridge CPU. This will be followed in the first half of 2017 by new Opteron branded chips that will also integrate the Zen core. With the server versions of Bulldozer and Piledriver at a high level AMD paired two of the dies it used for its desktop chips into one chip using a packaging technique called a multi-chip module (MCM). But chip packaging techniques have advanced significantly since 2012 when Piledriver launched and the world is pretty much AMD’s oyster thanks to 2.5D and 3D packaging.

AMD lists four characteristics of their next-gen Opteron chips: Zen cores, large core counts with multi-threading (read: SMT), disruptive memory bandwidth, and high native I/O capacity. The use of Zen cores and SMT-like multithreading scheme are characteristics AMD has already detailed. What the company hasn’t talked about publicly is how its going offer disruptive memory bandwidth, and high native I/O capacity. I’m sure the speculation on these two topics will be interesting to read.

I will say that at first glance disruptive memory bandwidth would seem to imply the use of advanced memory technologies like High Bandwidth memory (HBM2) and high native I/O capacity could imply any number of thing including an integrated networking controller like AMD’s Opteron A1100 series chips offer. In any case it appears that AMD’s planning on doing more than just plopping its new Zen core into the server market and it will be fun to see what they do.

The four characteristics of AMD’s next-gen ARM chips are: K12 cores, the highest performance ARM servers, the same markets targeted by the current Opteron A1100 series chips, and designed for efficiency which appear to give slightly contradictory signals given that AMD’s also aiming for these chips to top the ARM server performance charts. Given the quality of the high performance ARM server chips that will be present in the market when K12-based chips finally launch sometime in 2017 the idea that AMD’s chips will offer the highest performance of all ARM server chips is an aggressive proposition.

Perhaps more interestingly despite AMD’s ambitious goals for K12’s performance and efficiency the market segments the company will be targeting with chips are the same they’re targeting right now with its Opteron A1100 offerings. AMD’s current ARM-based chips, while a good start, clearly have areas where K12-based chips should be able to completely outclass them; particularly in absolute performance and performance per watt. This raises the question of what do those target markets really need? Are low-cost off the shelf ARM cores good enough or will higher performance custom ARM cores lead to more sales.

Finally we have AMD’s most exotic attack on the datacenter: a high-performance server APU. AMD’s HSA initiative has always had the HPC market written all over it. It’s good to see that AMD finally believes that HSA has matured to the point where it’s no longer just a consumer technology but a viable memory architecture for HPC applications. AMD lists multi-teraflops for HPC and Workstation as a characteristic of this APU implying that this chip will at a minimum offer 2 TFLOP/s of single precision compute. AMD’s Kaveri offers just under a TFLOP of compute performance so with AMD’s server chip we’re looking at a significant departure from the kinds of APU configurations we’re use to seeing.

Whether this means that AMD’s designing a monolithic large die-size APU or will be packaging a pile of its consumer APU dies together into one chip remains to be seen. Although there are rational arguments for both options. What AMD means when they mention a transformational memory architecture and scale-up graphics performance is an open question. At the very bottom of the slide AMD also notes that its open to working on semi-custom projects for datacenter chips. It will be interesting to see if any of AMD’s semi-custom efforts make it into products outside the gaming console market.

With AMD’s new roadmap we have public confirmation of a lot little bits that we were already aware of. We also have a clear sign coming on the heels of the launch of AMD’s A1100 series chips that the company is committed to building new products for the datacenter market. The next two years are going to be nothing if not an interesting time as AMD tries to claw its way back to profitability with a variety of genuinely new products.S|A