Skynet Takes on Qualcomm Engineers

Article By : Nitin Dahad, EE Times

OpenSingularity Foundation's Skynet project won't be like in the movies... Hopefully.

LONDON — An organization developing what it claims is the world’s first blockchain chip and a network of hyper-scalable blockchain IoT networks to create an “intelligent machine economy” has taken on a number of former Qualcomm engineers to develop the chip and the ecosystem.

The Skynet project, launched by the OpenSingularity Foundation, envisions a network of intelligent machines (as in the movie “Terminator”), utilizing blockchain, IoT, and AI to create secure trusted networks of devices that can intelligently communicate with each other autonomously and on a large scale. The organization says that this will enable billions of interconnected identifiable IoT devices to participate effortlessly in a global machine-to-machine (M2M) economy powered by self-organizing AI networks with data integrity facilitated by blockchains, which provide solutions for device identity, secure decentralized micro-payments, and trusted communication.

The project aims to create a core chip based on RISC-V, with the core FPGA planned for introduction in December 2019 and the core system-on-a-chip (SoC) available 12 months later. It hopes to then have “billions” of connected devices deployed by August 2022, according to the timeline on its website.

Srinivasa Rao Nagarajam

Last month, OpenSingularity made a pair of prize hires of former Qualcomm engineers. Srinivasa Rao Nagarajam, who joined as director of engineering, was previously director of engineering at Qualcomm, where his work led to the inception of the Snapdragon processor. OpenSingularity says that it hired Nagarajam because of his expertise in SoC design, software enablement, and end-to-end product commercialization.

Venkat Tangirala, a 22-year Qualcomm veteran, joined OpenSingularity as its ecosystem director. At Qualcomm, Tangirala helped complete its 5G modem pre-silicon development.

Carl Shi, vice president of engineering at Qualcomm, also joined OpenSingularity’s board this month. Several other members of the team have come from roles within Qualcomm as well as backgrounds with Alibaba, Google Ventures, Samsung, and Motorola.

At the heart of Skynet is the Skynet core, a purpose-built chip that implements an SoC optimized for blockchain and AI applications. It will eventually use a 32-bit or 64-bit RISC-V core and contains patent-pending technology to provide the blockchain specific components: the hardware cryptocurrency wallet for secure key management and automated permission system and AI authentication; an on-chip SHA-256 hash accelerator to determine data integrity; and automated transaction signing allowing the sources of all blockchain interactions to be clearly identifiable.

It will also include a neural processing unit (NPU) to act as the brain of the device, performing classification tasks with human-level accuracy at a practical throughput and within a practical power budget (although the foundation doesn’t state what this is at the moment). The NPU will be optimized to accelerate all current types of neural-network algorithms, including DNNs, CNNs, and RNNs.

The Skynet core will be released under a license-free model, allowing SoC manufacturers to create implementations of the chip and bundle them with their solutions. The foundation also says that to support intelligent devices supporting deep-learning applications, high-end versions of the chip will also contain tensor processing units and tensor processor arrays. These will allow efficient execution of complex deep-learning-based AI models.

Typical IoT architecture based on a Skynet core.

Source: OpenSingularity Foundation

In its 80-page white paper, OpenSingularity presents its vision and details of the core, a modular blockchain SoC that will eventually provide a competitive alternative to Arm in the IoT chipset market. All Skynet core devices will inherently feature a hardware wallet, enabling devices to use blockchains and crypto-currencies with the security of a ledger wallet “but with the added bonuses of a brain-on-chip system for AI authentication and human-like intelligent capabilities.”

All devices using the core would have the capacity to become intelligent and utilize the blockchain network. This would have applications in IoT devices in self-driving cars, smart cities, and smartphones. All would be able to connect via its Skynet open network (SON), which OpenSingularity says is a scalable IoT infinite-chain platform.

The SON will enable these devices to exchange value in milliseconds, deploy algorithms across the network, train off of vital private data, find one another in a secure manner, utilize any other network such as bitcoin or ethereum, and learn from its KnowledgeNet, comprised of improved fundamental infrastructures such as AWS and Imagenet.

OpenSingularity says that to host a modern Linux operating system (such as Ubuntu) for the SON blockchain to run on, it will include a set of modular processors in the Skynet core. It says that the RISC architecture of the Arm processor achieves a simple design, fast clock rate, small die sizes and efficient memory usage, expert design support, and leading software tools. Its product range also features a system-wide approach to security with TrustZone.

Initially, the Skynet project will target integrating processing cores from the Arm Cortex-M family for low-power embedded applications and the Arm Cortex-A 64-bit family of high-performance processors for high-end applications based on feedback from development partners, who advocate its low power and small footprint. The ecosystem also provides the advanced microcontroller bus architecture (AMBA) to interconnect the multiple peripherals (IO, coprocessors, and memory controllers), and multiple vendors provide trusted peripherals for a wide variety of process nodes.

The extensive penetration of Arm is also significant initially, with a tried-and-tested community that supports the entire software stack of bootloaders, kernels, drivers, libraries, applications, and software development tools such as compilers, profilers and debuggers.

Nevertheless, OpenSingularity says it is diligently exploring the alternative of developing a custom processor based on the RISC-V open-source instruction set architecture (ISA) as it — and the surrounding ecosystem — reaches practical maturity. The group says that recent implementations of the RISC-V core show promising results with smaller die size and better performance compared to Arm processors (BOOMv2 versus ARM Cortex-A9).

OpenSingularity comments in its paper, “RISC-V may provide an alternative to Arm’s monopoly, resulting in a very cost-effective Skynet core because the licensing fees to Arm would be eliminated, and this cost-saving could be passed on to SoC manufacturers as an incentive to accelerate adoption. We will monitor the progress of the RISC-V ecosystem expansion and decide as to which CPU core as a base of the Skynet core.”

It also plans to accelerate development of the entire software stack by partnering with SoC manufacturers to develop the whole integration stack as required by specific applications.

The foundation goes to great lengths to evaluate the characteristics of the Arm versus RISC-V architecture for its blockchain IoT chip.

As a RISC, Arm aims for fixed length, simple but powerful instructions that execute within a single cycle at high clock speed. The architecture is based on a number of principles to achieve simple design and fast clock rate. A pipeline is designed to be decoded in one stage with no need for microcode. A large set of general-purpose registers are defined for fast execution of instructions. Arm adopts a load/store architecture wherein data processing instructions apply to registers only and the load/store scheme is used to transfer data from memory.

However, there are a few differences from pure RISC. Arm adopts variable cycle execution for certain instructions, such as multiple register load/store to achieve faster and higher code density. Inline barrel shifter improves performance and code density, but leads to more complex instructions. The Thumb 16-bit instruction set enables about 30% code density improvement. Conditional execution improves performance and code density by reducing branch. Some enhanced instructions are added for DSP operations.

In its counter-argument, the foundation adds that existing ISAs, such as x86/x64, are proprietary and very complex. The details are often obscured in lengthy manuals, and some details of the ISA are not made public at all. Furthermore, the widely used ISAs have been around for years, and their designs carry baggage as a result; e.g., for backward compatibility. Proprietary ISAs are owned, managed, and controlled by corporate entities like Intel and Arm Holdings.

The RISC-V project came out of UC Berkeley to address these issues. The open-source approach taken by RISC-V means that many different companies can provide hardware implementations of the RISC-V architecture. Creating an ecosystem in which multiple vendors can compete in implementing a single ISA should result in many of the benefits seen in other open-source projects. OpenSingularity adds that RISC-V aims to create a modern ISA incorporating the best current ideas in processor design. The ISA strives to be much simpler than the legacy ISAs while being practical and intending to accommodate fast hardware implementations.

It argues that many embedded processors in IoT applications need to be cheap, reliable, and simple, but don’t necessarily require speed, support for an operating system, multiple cores, or support for 64-bit operations. On the other hand, it recognizes that there are other applications that require processors with multiple cores and 64-bit operations.

OpenSingularity chose the RISC-V because of its ability to approach this plethora of design choices by introducing some options into the ISA. In this respect, it adds that the RISC-V is really not a single ISA but more of a collection of related ISAs.

RISC-V offers three base integer ISAs: RV32I, RV64I, and RV128I for 32-bit, 64-bit, and 128-bit address widths, respectively. Forty instructions of fixed 32-bit width are provided for hardware integer operations, and there are several standard extensions, including one for embedded processors with only 16 registers.

A compressed instruction set compresses the regular 32-bit instructions into 16 bits similar to Arm’s Thumb instruction set for embedded applications, helping reduce the size of code to increase processor performance (being that it allows more instructions to be cached, reducing the time to fetch instructions from main memory, which is often a performance bottleneck).

— Nitin Dahad is a European correspondent for EE Times.

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