Third Workshop on Computer Architecture Research with RISC-V

in conjunction with ISCA’19

Phoenix, Arizona, USA

June 22, 2019

IMPORTANT DATES:

Abstract submission deadline: March 22, 2019

Full paper submission deadline: March 29, 2019 23:59 PST

Author notification: April 19, 2019

The Third Workshop on RISC-V for Computer Architecture Research (CARRV) seeks original research papers on the design, implementation, verification, and evaluation of RISC-V cores, SoCs, and accelerators. Submission of early work is encouraged.

The topics of specific interest for the workshop include, but are not limited to:

– RISC-V cores and SoC architectures

– RISC-V simulation/emulation infrastructure

– RISC-V ISA extensions

– RISC-V-based Hardware accelerators

– Security architectures and techniques

– Formal methods

– Verification methodologies

– Hardware/software interfaces

– RISC-V ISA and implementation performance analysis

– RISC-V compilers and dynamic translation tools

Submission instructions are available at the workshop web site.