Edit: There is now a tool in IceStorm to do this: icebram

Example usage:

Generate a random hex file for synthesis. Say we have a memory that is 8 bits wide x 512 words deep: icebram -g 8 512 > datafile_syn.hex Run synthesis (Yosys) and place&route (arachne-pnr). Use $readmemh("datafile_syn.hex", memory); in your Verilog code to initialize the memory. Replace memory content in the generated IceStorm .asc file: icebram datafile_syn.hex datafile.hex < synout.asc > final.asc Pack final IceStorm .asc file into binary bit-stream with icepack .

Simply repeat steps 3. and 4. whenever you got a new datafile.hex .

Theoretically this is possible of course, but it's not implemented yet. Afaics the following changes would be required:

1) Yosys' memory_bram pass would need to somehow store the information how a memory in the original design is broken up into individual SB_RAM40_4K cells, preferably by storing this information in attributes on the cells.

2) Arachne-pnr already can create a placelist. This should be extended to also write a file that contains the information from the attributes in 1) plus the relevant placement information.

3) A tool must be written that is using this information to patch the memory content of IceStorm .asc files.

I can do 1) but it would be nice if somebody else would do 2) and 3).