Intel founders Robert Noyce and Gordon Moore gave the semiconductor industry two legacies. First, there is Moore’s Law, which everyone knows but which is often misunderstood. Second, there is the planar integrated circuit. Noyce would have shared the Nobel Prize awarded in 2000 for the integrated circuit, if he had been alive then.

Noyce and Moore led the industry through the invention of the first commercial transistors and integrated circuits–the bipolar junction transistor and then the planar integrated circuit technology at Fairchild Semiconductor, the first company they founded. However, they then led a second industry transition when they left Fairchild and founded Intel to make high-density memory, as well as low-power logic chips, with a completely new transistor–the Metal-Oxide-Semiconductor Field-Effect Transistor.

The chips used just one transistor type (p-type or n-type) of MOSFET and had three supply voltages (+12 Volt, 0 Volt or Ground, and -5 Volt). Nevertheless, they were still much lower power and higher density than integrated circuits made with bipolar junction transistors.

In those days there was no monolithic integration of Complementary MOSFET (n-type and p-type) technology which we know as CMOS. It was not until 15 years later, in the early 1980s, that CMOS integrated circuits became Intel’s and the industry’s choice for its logic and memory chips due to the need for reduced power consumption, even though it was more complex and costly to fabricate.

As we know, high performance computing data centers today consume enormous amounts of power, and mobile computing chips are constrained by energy supply and battery life. Both these segments are now challenged by the slowdown in the rate of supply voltage scaling per CMOS process generation.

In cases where the computing applications can use parallelism, such as graphics and parallelizable algorithms, we have exploited the multi-core processing approach to reduce power. This was the “right-hand turn” that Intel took in 2005.

But there are still applications that cannot be parallelized, so called single-threaded ones. In addition, the energy of moving data from memory to the computing logic and back over the interconnect wires is now dominating the power consumption of computing.

Back in the 1990s the industry was improving CMOS logic switching energy efficiency 3x per process generation. This was enabled by the Dennard scaling law which prescribed a reduction of the MOSFET gate length and width, the power supply voltage, and the gate oxide thickness by 0.7x in each new process generation.

Two thirds of the improvement in the switching energy was enabled by the supply voltage (V) scaling of 0.7x per process generation starting from 5V down to 1.25V. Unfortunately for the industry, Dennard scaling stopped in 2003 with the 130nm node. After that the switching energy reduction per generation has decreased.

The 30% decrease in the supply voltage is no longer possible because of the constraint set by the MOSFET’s off-state leakage current. The steepness with which we can turn CMOS transistors on or off is limited by the physics of the thermal energy distribution of electrons to 60 mV for every 10x change in current at room temperature. The effect is called the Boltzmann Tyranny.

As Dennard scaling ended around 2003, power density no longer remained approximately constant in each new process generation. The power density increase had to be surmounted by slowing or limiting the CPU clock frequency increase.

The increase in compute performance was achieved by using multiple parallel processing cores. This was possible since Moore’s Law still continued and enabled CMOS technology to increase the density of transistors by ~2x per process generation, thus reducing the cost per transistor for each of those generations. That’s the fundamental premise of Moore’s Law.

Energy vs. delay for 32-bit arithmetic logic units in Intel’s process technology generations. (Source: Intel)

Since the end of Dennard scaling, Intel has innovated to continue Moore’s Law, and led what we call the MOSFET materials and device structure scaling era in which:

Channel mobility was increased by straining the channel at the 90nm node

Gate oxide leakage was reduced by using a high-k gate dielectric at the 45nm node

Short-channel source-to-drain off-state transistor leakage was reduced using FinFETs

FinFETs also enabled device area scaling using the fin’s height

Looking ten years ahead, power dissipation and power density are seen as the limiters to performance improvements for computing both in data centers and mobile devices. We are once again facing a challenge just like Intel was with the 80386processor in the 1980s–computing performance is limited by power consumption or heat that can be practically removed from a chip in a package.

The last time we faced this challenge Intel changed its microprocessor manufacturing process technology from one using only n-channel MOSFETs to CMOS with complementary n-type and p-type MOSFETs providing two transistors in a process technology.

In the next installment of this series, I will identify pending limiters as we continue to scale CMOS, and steer us on a path to overcome them.

–Ian Young is a director of exploratory integrated circuits and a senior fellow in Intel’s technology and manufacturing group.

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