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Applied Materials has taken the wraps off a new etching system meant to turn vertically stacked, three-dimensional transistors from lab experiments into commercial reality. The new Centura Avatar solves multiple problems facing manufacturers who are interested in 3D NAND but find their current equipment not up to the task of actually building it. While we’re specifically talking about 3D NAND today, a number of the challenges to scaling flash memory apply to scaling CPU logic as well.

Some of you may recall our future of CPU scaling stories from earlier this year, where we explored multi-core CPU trends as well as cutting-edge manufacturing materials and techniques. 3D chip stacking is expected to be a critical component of NAND manufacturing in the next decade. It’s important to understand that there are two sorts of “3D manufacturing.” One method refers to stacks of conventional 2D planar silicon; the other — which is what we’re talking about today — refers to actually building a 3D NAND structure.

First, a little context.

NAND manufacturing is a huge business. The key to understanding why Applied Materials is pushing 3D NAND, however, isn’t the big graph of flash demand — it’s the small graph labeled “Incredible cost/bit reduction.” Let’s zoom in.

Moving from 100nm to 60nm cut costs by nearly an order of magnitude. Manufacturers got close to that over the next two jumps, from 60nm to 40nm. 40nm to 20nm, by contrast, barely moves the bar. After 20nm, the line just trails off into a weak projection of “Hey, we’ll get something out of it at some point!” That’s the problem facing planar silicon, and it’s an issue we’ve discussed before.

What do you do if you can’t figure out how to scale planar manufacturing effectively below 20nm? You rethink the manufacturing process. Specifically, you take conventional 2D NAND:

Fold it over once (we’ve taken the liberty of nicknaming this interim step the NANDwich).

And stand it on edge.

Why 3D NAND is hard

According to the folks at Applied Materials, trying to build 3D NAND structures in real life would be like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata — and that’s before we discuss gate trenches or the staircases. Conventional etching systems deal with aspect ratios of 3:1 – 4:1, 3D etching requires an aspect ratio of 20:1 or more — and that’s not easy to pull off.

Avatar is designed to achieve smooth vertical sidewalls without bending or warping, to transition smoothly between alternate stack layers, and to stop at the right point when etching contacts on the NAND “staircase.” This last point is critical — if the machine doesn’t stop at precisely the right point, it’ll punch through into the next layer or underlying substrate, ruining the cells.

The Avatar system is designed to etch both mask and dielectric simultaneously, in order to keep additional equipment costs from ballooning and overall throughput high. Critically, it can also be used to extend the lifespan of older process geometries by allowing manufacturers to build 3D NAND on 40-50nm processes. While such structures would still be larger than the equivalent chips built on 30-20nm tech, the tremendous efficiency gain from going vertical will more than offset the difference.

As for when 3D chips will be available for commercial purchase, Applied Materials was vague on that point. Candidly, we don’t expect to see them in the near future. The new Avatar equipment is expensive and can’t be swapped in at the drop of a hat. What’s important is that it provides a way to cut cost/GB and boost die density without relying solely on new process nodes or on squeezing more bits into each NAND cell. It’s a significant step forward when the semiconductor industry isn’t exactly spoiled for scaling options, and we expect to see companies adopting the new etch equipment in the years ahead.