L1: Introduction and Basics

L2b: Course Logistics

L3: Memory Trends, Challenges, and Opportunities

L6b: Computation in Memory

L7: Computation in Memory II

L8: Computation in Memory III

L11a: The DRAM Latency PUF

L11b: D-RaNGe: True Random Number Generation with Commodity DRAM

L11c: Voltron: Reduced-Voltage Operation of Commodity DRAM Devices

L11d: Eden: Energy-Efficient High-Performance DNN Inference with Approximate DRAM

L12a: EIN: Understanding and Modeling Error Correction in DRAM

L12b: SoftMC: Flexible and Open-source Memory Controller

L12c: CROW: Improving DRAM Performance and Energy Efficiency Using Copy Rows

L12d: SMASH: Hardware-software Co-design for Sparse Matrix Compression

L13b: Memory Interference and Quality of Service

L14: SIMD Processors and GPUs

L15: Memory Interference and Quality of Service II

15.11

Fri.