We’ve covered both sides of the board with parts and even plated the edges. Now what? Smaller parts? The bypass caps under the devices are so small that I can “see” them better with my fingertip than with my eyes. These little braille bumps could just as easily (or almost as easily) be placed on an inner layer of the board.

Design for Outcome

If the approach taken is to simply squash the components closer together foregoing things like silkscreen, solder-mask, machine placement, rework, thermal dissipation, isolation, and so on, then the worst thing that could happen is a design win. You won’t be in business for long if it costs you more money to ship and support products than people will pay for those products.

You won’t be in business for long if it costs you more money to ship and support products than people will pay for those products.

Cutting corners on design rules will do that for you. First pass assembly yields and warrantee performance both rely on clean placement. Knowing that Electrical Engineers would cut those corners is why we have Designers in the first place. Electrical Designers provide the team with options that lead to black ink.

It seems inevitable that there will be one huge inductor that violates the headroom limit. Slotting out a few layers of the PCB will create a recess that could buy you that crucial half-millimeter in the Z-stack. It’s not truly embedded into the PCB but uses the same technology. Chips go into die cavities on substrates all the time.

Plan view with the inductor pads on layer 3.

Note that these preliminary views didn’t have enough copper pull-back from the cavity edge (thin red) to create the seal-ring on the target layer that makes up the inductor’s footprint. I had to go with via-in-pad and route the connecting shapes on the layer below. As usual, the primary component layer is the bottom. The physical design team ends up having the board face-down on nearly every phone, tablet, or laptop that I’ve ever seen. So, in this case, layer 3 gives me the depth that includes the core 3–4 dielectric where most of the thickness of this six-layer board lies.

A black hole to recess the tall inductor.

If we took the additional steps of populating the cavity during fabrication, filling the remaining air-space in the slot with resin, and then doing further lamination processes so that the component disappears from the face of the board, we would have embedded components.

We would need an X-ray to see them.

Pros:

The main reason is to open up space or get around keep-out areas on the surface of the PCB.

In the bypass cap example, the inductive loops would shorten since the via does not have to go all of the way through the board, which will make the SI/PI folks happy.

Another scenario is a series resistor on an internally routed clock. The clock net can remain internal from beginning to end.

The part is naturally shielded from some of the EMI (electro magnetic interference) running wild around the surface of the PCB.

Cons:

You better be really sure about the values selected, because embedded components are not field-serviceable or anywhere-else-serviceable.

Keep-outs around the cavity are similar to the board edge clearance expanding the net footprint.

Some fabrication shops may not be up to speed yet — this adds cost.

Same for the CAD tools. You’ll have to own and learn how to use the embedded features. I only know this stuff on Cadence Allegro; it’s not that difficult to use but it requires the “miniaturization” upgrade.

This metal core board represents my first attempt using controlled depth slots for parts. According to the date code of 41–99, I’ve been doing this stuff for a while now.

As with any new technology, we have to thank the early adopters for paving the way. Just as surface mount is now more common than through-hole technology, it is foreseeable that inner layers will eventually be a normal part of the placement plan. One of our can-do vendors, AT&S, generated a white paper on embedding the silicon itself and then testing the reliability through numerous means. While I’ve done chip on board, chip in board is new to me.

In their paper, AT&S has some caveats that would also apply to embedded discrete components.One of the key process steps of the embedding process flow (Figure 1) is the laminating process in the press, where the components are embedded into prepreg materials under high pressure and high temperature. The components have to withstand this stress environment, where pressure and temperature are increasing and decreasing due to the press profiles used and the behavior of resin flow of the prepreg materials.

Fgure 1 — J. Stahr et al

In addition, the cooling of the PCB after curing of the resin can be even more important for the stress loading of the embedded components. Here, the different coefficients of thermal expansion of the involved materials as glass, resin, ceramic component, Si dies or GaAs dies are the key parameters that can introduce residual stresses in the system.

So the gist is that we need to run this by our Mechanical and Process Engineering teams before jumping into the embedded pool, not to mention the fab shop. If not already, the time will come for IoT (Internet of Things) and other categories to follow in the steps of the cell phone industry.

Ice cold potatoes!

When you have eleven pounds of potatoes and a ten pound bag, you have to be creative, especially if you don’t like mashed potatoes. This analogy comes to mind after taking a drive up to Idaho over the holidays. Gas in the Mid-West is so cheap and the rental car was so miserly with it that cruising up to the center of nowhere for nothing seemed like a good use of time. It was. After about an hour on an icy serpentine backroad, I wound up at a quarry and had to go back the way I came in. That’s when the inspiration for this article hit me. Just thought I’d share that little tidbit.

Ultimately, this is a viable alternative for when the board is completely Tetris on placement and we’re asking the EE what parts they can live without. Timelines being what they are, we can’t always afford to model our own solutions to these problems. This is one more tool to get where we need to be.