By: Michael Feldman

Launched on December 11, the European Commission’s Mont-Blanc 2020 project will focus on the production of an ARM-based system-on-chip (SoC) capable of powering exascale supercomputers.

Representing the fourth iteration of the Mont-Blanc project, the effort will bring together some of the biggest players in Europe with supercomputing expertise, including Arm Limited, Atos/Bull, the Barcelona Supercomputing Centre (BSC), Forschungszentrum Jülich, the French Alternative Energies and Atomic Energy Commission (CEA), Kalray Corporation, and SemiDynamics.

The last two will be key to the project thanks to their background in chip design. Kalray is the developer of MPPA, an ultra-efficient manycore microprocessor aimed at low-power, high performance applications in the datacenter (storage and networking) and elsewhere (autonomous vehicles), while SemiDynamics is a processor architecture specialist, with a focus on RISC-V development for both ASIC and FPGA implementations.

The principle goal of the project is to design a low-power exascale SoC and deliver an initial ARM chip in the form of a proof-of-concept demonstration. While a production version of the processor is beyond the scope of the effort – so far, the EU has only allocated 10.1 million Euros for the project – the work will include the “implementation of critical building blocks and provide a blueprint for its first generation implementation.” Its focus will be on coming up with a design that balances vector length, network-on-chip (NoC) bandwidth, and memory bandwidth, with the power limitations inherent in an exascale supercomputer.

The chip is to be developed in a modular manner such that the functional blocks can be repurposed for other markets where low-power ARM technology is demanded – the rationale being to improve the economic value of the design work. The press announcement mentions autonomous driving as one potential “embedded HPC” application.

It’s no surprise that Mont-Blanc settled on ARM for its exascale architecture since the first three phases of the project were all ARM-focused. The third phase is a pre-exascale prototype is being constructed by Atos/Bull and will be powered by Cavium’s ThunderX2 ARM chip. Cavium, by the way, would have been a plausible partner for Mont-Blanc 2020, but given the chipmaker’s non-European credentials – it’s headquartered in Silicon Valley – the EC opted for Kalray (France) and SemiDynamics (Spain).

Given ARM’s involvement in the effort, it’s reasonable to speculate that the resulting processor will be some implementation of ARMv8-A SVE, a 64-bit processor design that incorporates a technology known as Scalable Vector Extension (SVE). The SVE specification enables processor designers to select vector lengths from 128 to 2048 bits, with a programming model that enables software to run across different implementations without modification. Fujitsu is currently designing an ARMv8-A SVE implementation for its Post-K exascale supercomputer that’s scheduled to be delivered to RIKEN in the 2021-2022 timeframe.

In any case, we’ll find out soon enough. Although the announcement did not come with a delivery date on the proof-of-concept demonstration, the 2020 timeframe is implied. After the chip is designed, the production of processors can commence once a suitable manufacturer is found. CEA is in line to become Europe’s first exascale customer, with Atos/Bull as the system provider. Since both of these organizations are part of the Mont-Blanc 2020 project, it’s conceivable that this effort will act as the R&D vehicle for this system and even other European supercomputing deployments further down the road.