This article was originally published last week, but without a diagram

It is around 10-17J for a device with 20nm feature size.

This tiny amount of energy was known last year, when the transistor structure was first revealed, but now the structure has been refined to allow flash-like readout simplicity, and it has been simulated in sufficient depth to predict: 5ns write time, good behaviour in arrays and to suggest suitable write, erase and read strategies for arrays.

echo do_shortcode('[inread_parallax slot="DFP-EW-InRead2-Mobile" width="300"]'); ?

echo do_shortcode('[inread_parallax slot="DFP-EW-InRead2-Mobile" width="300"]'); ?

It uses the unique characteristics of the ‘6.1-Å family’ – named for the lattice constant they share – whose members (indium arsenide, gallium antimonide and aluminium antimonide) exhibit useful properties when used together.

The memory cell, much like flash, uses a floating gate to store the memory state but, instead of using oxide isolation, the InAs floating gate is isolated by the anomalously-large conduction-band discontinuity with AlSb – that offers an extraordinarily long theoretical storage time – greater than the age of the universe, is one estimate.

However, much as the isolation is near-perfect, only just over 2V is needed to breach it for programming, due to the dual quantum well resonant tunnelling junction (made from alternating layers of AlSb and InAs) between the floating gate and the control gate.

Where the new transistor departs from last years is that the new channel is normally-off (normally-on transistors cannot be paralleled in arrays) and has better-defined on and off states.

“The channel exploits the unusual [type-III] band alignment of In(Ga)As and GaSb, where the conduction band of InAs is below the valence band of GaSb,” Professor Manus Hayne, who is leading the research, told Electronics Weekly. “This means that, even in the absence of doping, electrons will flow from the full valence band of the GaSb into the conduction band of the InAs channel. This was the case before, but here we have made the In(Ga)As channel narrow so that confinement pushes the energy of the channel state up to just above the GaSb valence band, such that it is unoccupied and normally-off, unless a suitable voltage is applied. This allows a readout that is similar to flash, and should deliver far superior 1-0 contrast to our previous devices allowing them to be connected in a fully-addressable array.” A patent for this has been applied for.

Simulating the gate programming resonant tunnelling junction using Nextnano.MSB has revealed the tunnelling current flow as well as modelling the confined states for different voltages. Another Nextnano product, nextnano++, was also used.

“The current flow can then be fed into the SPICE model of the device, and nextnano++ used to simulate the read,” said Hayne. “The very low level of disruption to neighbouring bits is seen as a result of the new model calculating the current flow, and the fact that the resonant tunnelling has a very sharp onset with applied voltage. Another important aspect is that because we can model the current flow, we can also model the write/erase speed, and it is fast.”

Emptying the floating gate of carriers (nominally setting the device to ‘logic 1’ state) takes 3ns, charging it takes just over 5ns.

Local disruption is low enough for the transistors to be used in arrangements analogous to both NAND and NOR flash – with individual bit operations possible in the latter case.

“We propose to short the drain contacts in pairs to the backgate [ground],” said Hayne. “This allows a high bit density architecture where the only contacts to the array are the wordlines, bitlines and a single ground.” This arrangement is also the subject of a patent application.

While write and erase look certain to be ultra-low-power, the jury is still out on read power. “Read will also be low energy but, as with all memories, it will depend on how little source-drain current can be reliably detected,” said Hayne, pointing out that his memory will not need the reconstructive write that is necessary after reading a ‘1’ from DRAM. Nor will it need DRAM’s periodic refresh.

The new work is published as ‘Simulations of ultralow-power nonvolatile cells for random-access memory‘ in IEEE Transactions on Electron Devices.