By Adam Taylor

When I introduced the Zynq UltraScale+ MPSoC’s PS (Processing System), I explained that it contained more processors than just those within the APU, RPU, and GPU. It also includes a Platform Management Unit (PMU) and Configuration Security Unit (CSU). The PMU is responsible for initialization during boot and platform monitoring during operation. The CSU is responsible for secure boot once the PMU releases it. The CSU also provides anti-tamper capabilities, key management and storage, and cryptographic acceleration.

Here’s a diagram of the PMU taken from the Zynq UltraScale+ MPSoC Technical Reference Manual:

In this blog post, we are going to look a little more in-depth look at the Zynq UltraScale+ MPSoC’s PMU because we really need to understand how it works, how we interact with it, and if necessary how we develop our own more complex platform management program using it.

The PMU has several roles in operation of the MPSoC. These roles can be summarized as platform management, however in more detail the PMU:

Performs initialization during boot. This process uses Sysmon to check the power supplies, initializes the PLLs, runs the Built in Test, and checks for errors before releasing the CSU.

Performs power management during operation. The PMU can shut down power domains or individual power islands or enter deep-sleep mode. Once in deep-sleep mode, the PMU is also suspended. Only the PMU can receive a wake-up trigger.

Monitors the system for errors and is capable of reporting these both internally and externally via the PS_ERROR_STATUS pin on the dedicated MIO.

Provides support for higher-level system management as may be required for functional-safety applications. It is possible for the user to upload their own more advanced PMU software, for instance to run a software test library (STL).

To reliably provide this platform-management function, the PMU has been implemented using triple-modular-redundant processors, which utilize voting along with ECC-protected RAM. The PMU ROM stores the initial application required to perform the initialization functions and transition between power schemes as necessary during operation of the Zynq UltraScale+ MPSoC.

Both the RPU and the APU are defined as power masters, which means they can ask the PMU to power down domains or islands. The APU and RPU can interact with the PMU through its global register space or via inter-process interrupts (IPI), which is how we control the power-management functions within the PMU. To support this there is a Xilinx Power Management Framework library available that complies with the IEEE P2415 Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems, which can be used by the application software. This framework library allows multiple processors running different operating systems to interact with the PMU.

As different power modes are entered and with a mix of powered and unpowered domains, it is possible to isolate powered domains from unpowered domains to prevent crowbarring. This also provides a very useful benefit: the PMU can isolate domains without powering them down. This ability to isolate domains from each other is very useful when it comes to functional-safety and secure applications.

The PMU has general purpose I/O that is connected to the Zynq UltraScale+ MPSoC’s MIO, used for interfacing with the outside world. There are also a number of dedicated PS I/O pins such as the POR signal and PS_ERROR_Status. Internally, there are error signals provided in both directions between the PS and the PL. The PMU also has four periodic interval timers and the ability to process interrupts, which makes it a very capable platform for monitoring device status. A 32-bit AXI interface connects to the low-power domain switch, which allows the PMU to access other PS resources.

As I mentioned earlier, we may wish to execute a more complex platform management on the PMU in some applications— to run a software test library, for example. To do this, we upload our own program into the PMU RAM, first checking to ensure that the PMU is in its sleep mode. We can command the PMU to enter sleep mode by issuing the inter-process interrupt to PMU channel 0. This also enables the branching to the user code being loaded in to the RAM once the PMU exits sleep mode.

The PMU is a very important element of the Zynq UltraScale+ MPSoC. We will return to a discussion of the PMU several times in future blog posts, including an example that shows you how to load your own PMU application. However, we first need to examine a few more building blocks and the power management framework.

Code is available on Github as always.

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