A. Sidewall electrode oxidation optimization

According to the previous reports46,47,48, the properties of tantalum oxide formed by Ta oxidation mainly depend on oxidation process conditions, especially on oxidation temperature and time: below 400 °C, most of the oxygen is dissolved in the tantalum lattice (which is called the solution of interstitial oxygen)46, while above 400 °C, the oxidation rate becomes faster as the annealing temperature rises47; additionally, after the complete oxidation, the thickness of the oxidized part would double48.

As in our device, since the switching material is formed through oxidation of Ta sidewall electrode, Ta oxidation condition and optimization are critical to the proposed structure. Therefore, three annealing conditions (300 °C/2 h, 400 °C/15 min, 500 °C/30 min) were investigated with comprehensive consideration of temperature and time to fabricate 2D RRAM devices with simply metal-insulator-metal (MIM) structure (Ta/TaO x /Pt) (See Oxidation Optimization in Methods section), allowing for both the component analysis as well as corresponding electrical measurements (as shown in Fig. 1).

Figure 1 SEM cross-section images (Top-(a–c)); AES profile (Middle-(d–f)); and corresponding device switching characteristics (Bottom-(g–i)) of sidewall electrode oxidation experiments under different annealing conditions: annealing 2 h/300 °C (Left-(a,d,g)); annealing 15 min/400 °C (Middle-(b,e,h)); annealing 30 min/500 °C (Right-(c,f,i)). The thickness of oxidized TaO x layers increase with elevated temperature. Full size image

The combination of cross-sectional profiles provided by scanning electron microscope (SEM) images (Fig. 1(a–c)) and oxygen distributions along depth direction provided by auger electron spectroscopy (AES) (Fig. 1(d–f)) clearly show the different composition distributions in three annealing conditions. Among which, 400 °C/15 min annealing is enough to form 11 nm TaO x film with proper oxygen concentration gradient, demonstrating that the novel critical process of this novel structure meets the temperature requirement of CMOS back-end process. In addition, according to the DC measurement displayed in Fig. 1 (g–i), device annealed under 400 °C/15 min condition shows best switching characteristics. In comparison, 500 °C/30 min annealing devices cannot be switched due to the 94 nm thick oxide layer and in case of 300 °C/2 h annealing samples, although there are some lucky devices can also be switched (on/off ratio smaller than 400 °C/15 min ones), their oxide thickness can hardly be detected (as depicted in Fig. 1(a,d)), indicating the risk of reproducibility and yield.

B. Novel 3D vertical RRAM fabrication

By utilizing the above optimized condition, the novel 3D VRRAM with cells in two vertical stacked layers is experimentally demonstrated based on Ta sidewall electrode oxidation, adopting 400 °C/15 min oxidation condition. Meanwhile, devices with conventional 3D structure are also fabricated as a comparison (See Device Fabrication in Methods section). The schematic view of both structures and the detailed fabrication processes of the proposed novel 3D RRAM cell are illustrated in Fig. 2. The core distinction of the fabrication processes of both structures lies in that, instead of PVD or ALD to form a continuous switching layer in conventional structure, partially oxidation of the isolated sidewall electrodes can naturally form the self-confined switching areas on the edge of sidewall electrodes in the novel 3D structure. The transmission electron microscope (TEM) and energy dispersive x-ray spectroscopy (EDX) characterizations confirm the differences as shown in Figs 3 and 4.

Figure 2 (Top) 3D vertical RRAM array architecture of conventional structure with continuous oxide resistive switching layer and novel structure with self-localized resistive switching region formed around Ta sidewall electrode. TEM images of enlarged view of RRAM cells in both structures demonstrate the differences. (Bottom) Fabrication process of the proposed novel 3D vertical RRAM structure. Full size image

Figure 3 TEM images of (a) conventional structure; (b) proposed novel structure; (c) top cell in the proposed novel structure; (d) bottom cell in the proposed novel structure. TEM images clearly show that the switching layers of top cell and bottom cell are a consecutive TaO x film in conventional structure while the switching regions are isolated by Si 3 N 4 layer and confined to the Ta sidewall electrodes. The proposed SEO structure is well demonstrated here. Full size image

Figure 4 (Left) Horizontal EDX line scans with corresponding elements profiles labeled as (a,b) in Fig. 3(a); (Right) Horizontal EDX line scans with corresponding elements profiles labeled as (c,d) in Fig. 3(b). EDX analysis of elements profile further confirms the switching region in the proposed SEO structure is totally isolated by Si 3 N 4 layer. Full size image

TEM images display that the spontaneously confined TaO x switching regions only exist around the sidewall electrodes after annealing in the proposed novel structure (Fig. 3(a)), while a consecutive TaO x switching layer deposited by sputtering covers on the whole sidewall of the hole-region in conventional structure (Fig. 3(b)). To further carefully compare the elements profile differences between both structures, EDX component analysis are conducted on the isolation layer and sidewall electrode region near sidewall of the hole in both structures. Shown by the Fig. 4(a,b), TaO x can be seen only in the resistive cell region in the novel structure and no TaO x in the counterpart of the isolation layer, while TaO x exists in both cell and isolation layers in conventional structure (Fig. 4(c,d)). Additionally, in conventional structure cell region shown by Fig. 4(a), it is observed that element N is detected in the TaO x region besides the isolation Si 3 N 4 layers, indicating that a conducting TaN phase may be formed by reaction between Ta 2 O 5 and Si 3 N 4 , raising the risk of short-circuiting the vertical adjacent cells. By contrast, the cells in novel structure are cut off completely without the similar concerns, further demonstrating the improvements.

It is worth noting that the concentration gradient in novel 3D structure is similar to that of the optimization experiment in Fig. 1, which validates that our self-confined 3D structure will not affect the oxidation process to form TaO x with uniform quality which can ensure the resistive switching properties. In addition, the enlarged TEM images (Fig. 3c,d) indicate that switching layer thicknesses of top and bottom cells are also similar to the 2D cell with the same optimized annealing condition, which further indicates the stability and uniformity of the critical oxidation process. This feature is essential for RRAMs to maintain highly uniform performance in 3D era with scaled dimensions. For instance, as the increase of stacking layers and the decrease of hole dimensions, the conformality of TMO switching layer deposition (PVD or ALD) process would inevitably get deteriorated due to the limitation of conventional etching and deposition processes, leading to the severe variations of deposited switching layer thickness and consequently resulting in electrical performance dispersions in conventional 3D VRRAM devices. However, in case of the proposed structure, the thickness of switching TMO layer is mainly determined by partially oxidation of sidewall electrodes, which is not sensitive to the scaled dimension of 3D structure, facilitating the uniform formation of switching cells and accordingly the good device-to-device uniformity control.

C. Switching characteristics

Electrical characterizations were performed on Agilent B1500A semiconductor characterization system. During the measurements, the voltage is applied on Ta sidewall electrode, while keeping Pt top electrode grounded all the time.

The typical switching characteristics of novel structure and conventional structure are displayed in Fig. 5(a,b), respectively. The resistance switching occurs along direction of the arrows shown in the figures, with set voltage about 1V and reset voltage about 2V in both structures, which meets the requirement of integration. Meanwhile, the very similar performances demonstrate that the switching layer formed by optimized oxidation process in novel structure exhibits the comparable switching characteristics with the sputtering switching layer in conventional structure, which further confirms the TEM and EDX results in Figs 3 and 4. In addition, the identical characteristics of the up- and bottom- cell in the proposed structure complementally verifies the process uniformity of sidewall electrode oxidation (SEO), corresponding to the same thicknesses in both layer shown in Figs 3 and 4. Furthermore, switching window >10X was obtained without requiring current compliance in reset operation, which is beneficial to simplify the peripheral circuit design. The excellent self-compliance and controllable reset process are due to the gradient profile of oxygen concentration in TaO x corresponding to the SEO process.

Figure 5 (Switching Characteristics) Typical I-V curves from randomly chosen adjacent cells in both conventional structure (a) and proposed SEO structure (b). The devices show not only excellent bipolar switching characteristics but also nearly identical initial switching curves. (Resistive Distributions) Resistive distributions in conventional structure and proposed SEO structure. (c) device-to-device variability obtained from 30 randomly selected devices; (d) cycle-to-cycle variability obtained from 107 consecutive pulse operation cycles. HRS/LRS ratio >10X is obtained in proposed SEO structure. (Endurance performances) Endurance characteristics of conventional structure and proposed SEO structure. Pulse operation configuration: set 1.3 V/200 ns; reset −1.6 V/500 ns. ~108 cycles was obtained without verification and any noticeable degradation in proposed SEO structure. Conventional structure degrades after ~106 cycles. Full size image

Since that the distributions of resistance are critical parameters for memory array performance and also key issues for 3D RRAM array integration, 30 randomly selected devices were measured to obtain the cumulative probability of both structures, as well, cycle-to-cycle variability was obtained from 107 consecutive pulse operation cycles in one randomly selected device of both structures, respectively. Compared with conventional structure, remarkable improvements of both device-to-device (Fig. 5(c)) and cycle-to-cycle (Fig. 5(d)) uniformity of HRS are achieved in the novel structure. As mentioned above, the SEO process helps to form uniform oxide films in different layers, thus improving the device-to-device uniformity. At the same time, the enhanced cycle-to-cycle uniformity is mainly benefited from the confined switching region which can effectively suppress the diffusion of oxygen vacancies (V O s) and consequently improving the stability of the conductive filaments (CFs) morphology.

D. Reliability behaviors

The comparison of reliability performances (endurance and retention) was also experimentally performed in detail. During pulse measurements, the proper pulse programming conditions are optimized as: 1.3 V/200 ns for set operation and −1.6 V/500 ns for reset operation without any verification operation. Endurance as high as ~108 cycles was obtained without any noticeable degradation in the proposed cell structure (Fig. 5(e)). In contrast, (Fig. 5(f)) shows that the HRS of the conventional cell degraded at only ~106 cycles under the same test configuration. The marvelous improvement of endurance capability of the novel 3D structure is attributed to the more confined oxygen distribution of physically isolated resistive cells due to SEO process. To be specific, in the novel structure, benefited from the good isolation, oxygen vacancies (V O s) involved in the formation or rupture of CFs in the cell region can be well maintained as the cycling times increasing, thus significantly mitigating the endurance degradation.

As for the non-volatile memory (NVM), retention property determines the time limit for data storage, which is the critical reliability parameter. In the case of RRAM, the degradation of low resistive state (LRS) is more serious, since that the CFs evolution in LRS is directly related to the V O s diffusions under the action of both concentration gradient and thermal effect. Especially in small dimensions, the trade-off of retention and low operation current gets more obvious41, for the reason that the CFs are more vulnerable in the low current region and small sizes. This degradation will be more serious in 3D structures as the heat accumulation is more obvious due to the heat dissipation problems of the complex multi-layer structures. In this paper, in order to carefully investigate the influence of 3D structures on the retention performances as well as the V O s diffusion behavior, devices of four different resistance states (LRS-1, LRS-2, LRS-3 & HRS) of both structures were baked at 150 oC. As shown in Fig. 6, both low resistive state (LRS) and high resistive state (HRS) of conventional devices exhibit distinct drift to higher resistance states. And notably, the aggravation of retention degradation with increased LRS in conventional devices well demonstrates the trade-off between retention capability and low current operation in conventional 3D structure41. However, only slight changes in all the four resistive states were observed in the novel structure devices (Fig. 6) even after the 180 h baking, indicating the superior retention feature of the proposed structure. Furthermore, the proposed structure, with good stability of relative high resistance in LRS, also demonstrates great potential for low power application.

Figure 6 Retention behavior of four different resistive states (LRS_1 (103 ohm), LRS_2 (3*104 ohm), LRS_3 (106 ohm), HRS (108 ohm)) at 150 °C for conventional structure and proposed SEO structure. For conventional structure, resistance state shows distinct drift to higher resistance state. For proposed SEO structure, each resistance state can maintain almost unchanged >180 h@150 °C. Full size image

We believe that the significant reliability improvements of the proposed sidewall electrode oxidation (SEO) cell are due to the automatic formation of self-confined switching area which can significantly inhibit the degradation caused by the combination of oxygen vacancies diffusion and thermal effect during switching process. Additionally, adoption of Si 3 N 4 dielectric layers, which acts as powerful oxygen-blocking layers and heat sinks43,44,45, further prevents the unwanted diffusions of oxygen vacancies. It is widely accepted that CF consisting of V O s in TMO RRAM device has higher V O concentration in the center of CF and the redistribution of V O s driving by concentration gradient and thermal effect will give critical impacts on resistance drift of LRS and consequently retention characteristics of RRAM devices21,22. Figure 7(a) illustrates the schematic diagram of oxygen vacancies diffusions inside the proposed SEO cell and the conventional cell. A thermal diffusion model was proposed to gain insightful understanding of the reliability issues (Fig. 7(b)), based on which distribution of V O s density in the resistive cell region versus time can be calculated.

Figure 7 Schematic diagram of (a) Oxygen vacancies diffusion inside the conventional structure and the proposed SEO structure; (b) thermal diffusion model of the time dependent oxygen vacancies density distribution. Full size image

Corresponding to Fig. 7(b), the vertical direction in 3D structure is set as X axis to calculate the diffusion of V O s between resistive cell and the adjacent isolation layer or resistive film in both structures. The processes of V O s concentration varying with time in the resistive cell regions can be described by the following equations21,22:

V O s concentration

In which, c(x, t) is the time-varying V O s concentration along the cell region, Q T is the total quantity of oxygen vacancies per unit area, D is the diffusion coefficient with the expressions as follows:

Diffusion coefficient

Intrinsic diffusion coefficient

where E a is the activation energy (1.16 ev for TaO x 21 and >4.7 eV49 for Si 3 N 4 ), k is the Boltzmann constant (1.38 × 10−23 J/K), q is the electron charge (1.6 × 10−19C), λ is the lattice constant in isolation layer (0.76 for TaO x and 0.79 for Si 3 N 4 ), f is the oscillation frequency of phonon (~1013).

Furthermore, since cell resistance is mainly related to the oxygen vacancies distribution, resistance change versus time due to V O s diffusion can be derived from V O s density evolution versus time. As shown in Fig. 8(a), by characterizing the temperature dependence of LRS for both structures, the conduction mechanism is demonstrated as variable range hopping21,50, with the relationship between conductivity and V O s density as expression (4):

Figure 8 Calculated LRS_2 (fittings of other resistances are not shown here) degradation from the proposed model of the conventional structure and the proposed SEO structure at 150 °C fits well with the experimental data. With the standard of 20% resistance change, the proposed SEO structure shows highly improved retention behavior in comparison with the conventional structure. Full size image