By Adam Taylor

Having introduced the basics of constraints within Vivado in my most recent blog posts, this post will focus upon timing constraints.

At the most basic level within an FPGA, we use a clock to provide a regular timing reference upon which to transmit and receive data. If we were to analyze this by hand we would need to consider the clock period, set up (Tsu) and hold (Thd) times, and the clock-to-output (TclkQ) time to ensure that our design violates none of these times:

We can check for timing violations by hand for a single register. However, as we implement complex designs within FPGAs containing millions of flip flops and complex, non-ideal clock trees, accounting for skew and jitter must be automated by the EDA tool—in this case the Vivado Design Suite; there are just too many things to check by hand.

To understand timing constraints in Vivado we must first understand the terminology used to drive these constraints, as identified by Xilinx User guide UG903, “Vivado Design Suite User Guide: Using Constraints”:

These terms help us understand and define our design’s timing behavior in the FPGA.

Before we look at how we define these constraints, I think it’s a good idea to explain what setup and hold requirements are in a little more detail. Most of the other terminology is pretty straightforward.

The set-up time specifies the amount of time that the data must be stable and unchanging on the flip-flop’s data input before the next clock edge occurs. Note that we may be dealing with more than one clock here. The launch clock is associated with the source that launches the data. The capture clock is associated with the destination flip-flop that captures the data. The set-up requirement is the clock’s capture edge time minus the launch edge time. Note that these clocks can be different—they can have different phases or different clock periods. If different launch and capture clocks are used then the set-up requirement is the smaller of the two when you consider the worst-case relationships between the two clocks.

Hold time is the time that the data must be stable and unchanging after the capture clock edge. The hold time is the greater of the current capture edge minus the next launch edge. If the launch and capture clocks are different, then worst-case timing between clocks becomes an important consideration.

Vivado analyzes both the set-up and hold times and provides the results of these analysis. The resulting report shows the design slack. Positive slack means that the register will not clock in a wrong value or go metastable. Negative slack means metastability is an issue because of a timing violation.

Of course to perform the timing analysis we need to define the clock or clocks and provide the design tool with appropriate design information. To define a clock in XDC, we need to provide in the most basic definition:

Clock Name

Clock period in ns

Waveform definition, defined in absolute time

Vivado encompasses three concepts for clocks, which are defined slightly differently:

Primary Clocks – those that enter through an I/O pin

Generated Clocks – those which are generated automatically via an internal PLL or by the design (for instance, dividing a clock by two with a flip-flop). With generated clocks, one describes how the master clock (either a prime or other generated clock) modifies the waveform

Virtual Clocks – These are not attached to anything within the design netlist but can be used for I/O timing

Primary and virtual clocks are created using the command:

create_clock –period –name –waveform [source objects]

For example, if we wish to define a clock with a 10nsec input and 50% duty cycle from an input pin, we can use the line below:

create_clock – period 10ns –name sys_clk –waveform {0 5} [get_ports sys_clk]

The interesting part in this line is “–waveform {0 5}”, which defines the transition points of the edges of the waveform at 0 and 5 ns hence 50:50 for a 10nsec clock. To have a different waveform duty cycle, for instance 30:70, we would use “–waveform {3 10}”.

Generated clocks are created using the command:

create_generated_clock –name –source –edges –divide_by –multiply_by –duty_cycle –edge_shift –master_clk –combinatorial

For example to divide the clock above by two we could write:

create_generated_clock –name clk_div2 –divide_by 2 –source [get_ports sys_clk] [get_pins divider_out]

In the next blog we will continue to look at timing constraints such as clock groups, uncertainty and exceptions.

You can access previous instalments of the MicroZed chronicles here

Please see the previous entries in this MicroZed Chronicles series by Adam Taylor:

Adam Taylor’s MicroZed Chronicles Part 69: Zynq SoC Constraints Overview

Adam Taylor’s MicroZed Chronicles Part 68: AXI DMA Part 3, the Software

Adam Taylor’s MicroZed Chronicles Part 67: AXI DMA II

Adam Taylor’s MicroZed Chronicles Part 66: AXI DMA

Adam Taylor’s MicroZed Chronicles Part 65: Profiling Zynq Applications II

Adam Taylor’s MicroZed Chronicles Part 64: Profiling Zynq Applications

Adam Taylor’s MicroZed Chronicles Part 63: Debugging Zynq Applications

Adam Taylor’s MicroZed Chronicles Part 62: Answers to a question on the Zynq XADC

Adam Taylor’s MicroZed Chronicles Part 61: PicoBlaze Part Six

Adam Taylor’s MicroZed Chronicles Part 60: The Zynq and the PicoBlaze Part 5—controlling a CCD

Adam Taylor’s MicroZed Chronicles Part 59: The Zynq and the PicoBlaze Part 4

Adam Taylor’s MicroZed Chronicles Part 58: The Zynq and the PicoBlaze Part 3

Adam Taylor’s MicroZed Chronicles Part 57: The Zynq and the PicoBlaze Part Two

Adam Taylor’s MicroZed Chronicles Part 56: The Zynq and the PicoBlaze

Adam Taylor’s MicroZed Chronicles Part 55: Linux on the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 54: Peta Linux SDK for the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 53: Linux and SMP

Adam Taylor’s MicroZed Chronicles Part 52: One year and 151,000 views later. Big, Big Bonus PDF!

Adam Taylor’s MicroZed Chronicles Part 51: Interrupts and AMP

Adam Taylor’s MicroZed Chronicles Part 50: AMP and the Zynq SoC’s OCM (On-Chip Memory)

Adam Taylor’s MicroZed Chronicles Part 49: Using the Zynq SoC’s On-Chip Memory for AMP Communications

Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

Bringing up the Avnet MicroZed with Vivado