An adder is a digital logic circuit in electronics that is extensively used for the addition of numbers. In many computers and other types of processors, adders are even used to calculate addresses and related activities and calculate table indices in the ALU and even utilized in other parts of the processors. These can be built for many numerical representations like excess-3 or binary coded decimal. Adders are basically classified into two types: Half Adder and Full Adder.

What is Half Adder and Full Adder Circuit?

The half adder circuit has two inputs: A and B, which add two input digits and generates a carry and a sum. The full adder circuit has three inputs: A and C, which add three input numbers and generates a carry and sum. This article gives detailed information about what is the purpose of a half adder and full adder in tabular forms and even in circuit diagrams too. It is already mentioned that the main and crucial purpose of adders are addition. Below is the detailed half adder and full adder theory.

Half Adder

So, coming to the scenario of half adder, it adds two binary digits where the input bits are termed as augend and addend and the result will be two outputs one is the sum and the other is carry. To perform the sum operation, XOR is applied to both the inputs, and AND gate is applied to both inputs to produce carry.

Whereas in the full adder circuit, it adds 3 one-bit numbers, where two of the three bits can be referred to as operands and the other is termed as bit carried in. The produced output is 2-bit output and these can be referred to as output carry and sum.

By using a half adder, you can design simple addition with the help of logic gates.

Let’s see an example of adding two single bits.

The 2-bit half adder truth table is as below:

0+0 = 0

0+1 = 1

1+0 = 1

1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10, the sum result must be re-written as a 2-bit output. Thus, the equations can be written as

0+0 = 00

0+1 = 01

1+0 = 01

1+1 = 10

The output ‘1’of ‘10’ is carry-out. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out.

Now it has been cleared that a 1-bit adder can be easily implemented with the help of the XOR Gate for the output ‘SUM’ and an AND Gate for the ‘Carry’.

For instance, when we need to add, two 8-bit bytes together, then it can be implemented by using a full-adder logic circuit. The half-adder is useful when you want to add one binary digit quantities.

A way to develop two-binary digit adders would be to make a truth table and reduce it. When you want to make a three binary digit adder, the half adder addition operation is performed twice. In a similar way, when you decide to make a four-digit adder, the operation is performed one more time. With this theory, it was clear that the implementation is simple, but development is a time taking process.

The simplest expression uses the exclusive OR function:

Sum= A XOR B

Carry = A AND B

And an equivalent expression in terms of the basic AND, OR, and NOT is:

SUM=A|.B+A.B’

VHDL Code For Half Adder

Entity ha is

Port (a: in STD_LOGIC;

b : in STD_LOGIC;

sha : out STD_LOGIC;

cha : out STD_LOGIC);

end ha;

Architecture Behavioral of the above circuit is

begin

sha <= a xor b ;

cha <= a and b ;

end Behavioral

Full Adder

This adder is difficult to implement when compared to half-adder.

The difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs, whereas half adder has only two inputs and two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.

The output carry is designated as C-OUT and the normal output is represented as S which is ‘SUM’.

With the above full adder truth-table, the implementation of a full adder circuit can be understood easily. The SUM ‘S’ is produced in two steps:

By XORing the provided inputs ‘A’ and ‘B’ The result of A XOR B is then XORed with the C-IN

This generates SUM and C-OUT is true only when either two of three inputs are HIGH, then the C-OUT will be HIGH. So, we can implement a full adder circuit with the help of two half adder circuits. Initially, the half adder will be used to add A and B to produce a partial Sum and a second-half adder logic can be used to add C-IN to the Sum produced by the first half adder to get the final S output.

If any of the half adder logic produces a carry, there will be an output carry. So, C-OUT will be an OR function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit shown below.

The implementation of larger logic diagrams is possible with the above full adder logic a simpler symbol is mostly used to represent the operation. Given below is a simpler schematic representation of a one-bit full adder.

With this type of symbol, we can add two bits together, taking a carry from the next lower order of magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a multi-bit operation, each bit must be represented by a full adder and must be added simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be formed by cascading two of the 4-bit blocks.

Half Adder and Full Adder Using K-Map

Even the sum and carry outputs for half adder can also be obtained with the method of Karnaugh map (K-map). The half adder K-map is

The full adder K-Map is

With the above-mentioned truth tables, the results can be obtained and the procedure is :

A combinational circuit combines the different gates in the circuit where those can be an encoder, decoder, multiplexer and demultiplexer. The characteristics of combinational circuits are as follows.

The output at any instant of time is based only on the levels that are present at input terminals.

It does not use any memory. The previous state of input does not have any effect on the present state of the circuit.

It can have any number of inputs and m number of outputs.

The difference between half adder and full adder is that half adder produces results and full adder uses half adder to produce some other result. Similarly, while the Full-Adder is of two Half-Adders, the Full-Adder is the actual block that we use to create the arithmetic circuits.

Carry Lookahead Adders

In the concept of ripple carry adder circuits, the bits that are necessary for addition are immediately available. Whereas every adder section needs to hold its time for the arrival of carry from the previous adder block. Because of this, it takes more time to produce SUM and CARRY as each section in the circuit waits for the arrival of input.

For instance, to deliver output for the nth block, it needs to receive input from (n-1)th block. And this delay is correspondingly termed as propagation delay.

To overcome the delay in ripple carries adder, a carry-lookahead adder was introduced. Here, by using complicated hardware, the propagation delay can be minimized. The below diagram shows a carry-lookahead adder using full adders.

The truth table and corresponding output equations are

A B C C+1 Condition 0 0 0 0 No Carry Generate 0 0 1 0 0 1 0 0 0 1 1 1 No Carry Propagate 1 0 0 0 1 0 1 1 1 1 0 1 Carry Generate 1 1 1 1

The carry propagates equation is Pi = Ai XOR Bi and the carry generate is Gi = Ai*Bi. With these equations, the sum and carry equations can be represented as

SUM = Pi XOR Ci

Ci+1 = Gi + Pi*Ci

Gi delivers carry only when both the inputs Ai and Bi are 1 without considering the input carry. Pi is related to the carry propagation from Ci to Ci+1.

Advantages

The advantages and disadvantages of half adder and full adder are

The foremost purpose of a half adder is to add two single-bit numbers

Full adders hold the ability to add a carry bit which is the resulting from the previous addition

With full adder, crucial circuits such as adder, multiplexer, and many others can be implemented

The full adder circuits consume minimal power

VHDL Coding

VHDL coding for full adder include the following.

entity full_add is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

cin : in STD_LOGIC;

sum : out STD_LOGIC;

cout : out STD_LOGIC);

end full_add;

Architecture Behavioral of full_add is

component ha is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

sha : out STD_LOGIC;

cha : out STD_LOGIC);

end component;

signal s_s,c1,c2: STD_LOGIC ;

begin

HA1:ha port map(a,b,s_s,c1);

HA2:ha port map (s_s,cin,sum,c2);

cout<=c1 or c2 ;

end Behavioral;

Related Concepts

The concepts related to half adder and full adder just not stick to a single purpose. They have extensive usage in many applications and few of the related are mentioned :

Half adder and full adder IC number

Development of 8-bit adder

What are the half adder precautions?

JAVA Applet of a Ripple Carry Adder

Therefore, this is all about the half adder and full adder theory along with the truth tables and logic diagrams, the design of full adder using half adder circuit is also shown. Many of the half adder and full adder pdf documents are available to provide advanced information of these concepts. It is furthermore important to know that how 4 bit full adder is implemented?