As part of Europe’s multi-pronged approach to address research into and development of high performance computing (HPC) and data infrastructure with supporting innovation ecosystem, the European Processor Initiative (EPI) has completed its first anniversary with details of a new common platform for heterogenous compute environments.

The EPI’s objective is to design and implement a roadmap for a new family of low power European processors for exascale computing, implementing vector instructions and specific accelerators with high bandwidth memory access, as well meeting high security and safety requirements. The specific challenge is to build two exascale computing machines which rank in the top three globally. This will be achieved through intensive use of simulation, development of a complete software stack and tape-out in the most advanced semiconductor process node available, providing a competitive chip that can effectively address the requirements of the HPC, artificial intelligence (AI), automotive and trusted IT infrastructure markets.

The European Processor Initiative timeline (Source: EPI)

Over the last year, the EPI – a project with 27 partners from 10 European countries – has submitted several architectural designs to the European Commission and has now presented its updated roadmap to the public. The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles consisting of RISC-V based (EPAC), multi-purpose processing array (MPPA), embedded FPGA (eFPGA) and cryptography hardware engine. The first Rhea chips will be fabricated in N6 technology aimed at the highest processing capabilities and energy efficiency.

The Rhea chips will be integrated into test platforms, both in workstations and supercomputers in order to validate the hardware units, develop the necessary software interfaces, and run applications. Rhea aims to be the European processor for several experimental platforms towards exascale HPC and future automotive designs.

As part of its initiative to harmonize the heterogeneous computing environment by defining a common approach, the new EPI common platform (CP), which is in early development, will include the global architecture specification (hardware and software), common design methodology, and global approach for power management and security. The CP in the Rhea family of processors will be organized around a 2D-mesh network-on-chip (NoC) connecting computing tiles based on general purpose Arm cores with the additional accelerator tiles as indicated previously.

The new EPI common platform provides a common backbone for the heterogeneous high-performance compute platform based on the Rhea chip which features |Arm, RISC-V and embedded FPGA tiles (Source: EPI)

A common software environment between heterogeneous computing tiles will harmonize the system, acting as a common backbone of IP components for IO connection with the external environment such as memories and interconnected or loosely coupled accelerators. With this CP approach, EPI will provide an environment that can seamlessly integrate any computing tile. The right balance of computing resources matching the application needs will be defined through a carefully designed ratio of the accelerator and general-purpose tiles.

The EPI SW environment has its roots in the Mont-Blanc programs. From this standpoint, EPI leverages all efforts made by the European Commission and the European HPC community to create the Arm software ecosystem in HPC. The second generation of EPI NoC is based on Mont-Blanc2020. The seven partners of Mont-Blanc are also full members, either directly or as key partner of EPI.

The idea behind EPI is rooted in Horizon 2020, the biggest EU research and innovation program with almost €80 billion funding over the 2014-2020 period, and was planned by the EC with one of the calls in the ICT work program; in parallel, in March 2017, the EC also initiated the formal signature of the EuroHPC declaration, which later brought the setup of the Joint Undertaking (JU) which supports the EPI initiative. The intention of the JU is to make Europe less reliant on foreign technology in a field that is essential for many areas of the digital economy in high-performance computing and beyond, such as connected and autonomous vehicles, and big data servers. The JU will also support the development of world-class scientific, public sector and industrial applications, in particular through centers of excellence in HPC applications in many domains, including personalized medicine, bio-engineering, weather forecasting and climate change, discovering new materials and medicines, oil and gas exploration, designing new planes and cars, and smart cities.

Nitin Dahad Nitin Dahad is a correspondent for EE Times, EE Times Europe and embedded.com. With 35 years in the electronics industry, he's had many different roles: from engineer to journalist, and from entrepreneur to startup mentor and government advisor. He was part of the startup team that launched 32-bit microprocessor company ARC International in the US in the late 1990s and took it public, and co-founder of The Chilli, which influenced much of the tech startup scene in the early 2000s. He's also worked with many of the big names - including National Semiconductor, GEC Plessey Semiconductors, Dialog Semiconductor and Marconi Instruments.