A "sea change in the computing industry"

A new startup out of MIT emerged from stealth mode today to announce that they're shipping a 64-core processor for the embedded market. The company, called Tilera, was founded by Dr. Anat Agarwal, the MIT professor behind the famous and venerable Raw project on which Tilera's first product, the TILE64 processor, is based. Tilera's director of marketing, Bob Doud, told Ars that TILE64 represents a "sea change in the computing industry," and the company's CEO isn't shy about pitching the chip as the "first significant new chip architectural development in a decade." So let's take an initial look at what was announced about TILE64 today, with further information to follow as it becomes available.

TILE64

Tell me if this sounds familiar: a grid of processor "tiles" arranged in a mesh network, where each tile houses a general purpose processor, cache, and a non-blocking router that the tile uses to communicate with the other tiles on the chip. If you've followed my coverage of Intel's Terascale research project—especially the 80-core Polaris prototype—then you know that this description fits what Intel has been working on for the past few years and aggressively publicizing for a year or so.

But the basic tile + processor/cache + router + mesh network idea was pioneered by Dr. Agarwal and MIT's RAW project about a decade ago, and now those same ideas also form the basis for TILE64. TILE64 consists of a mesh network of 64 tiles, with each tile containing a general-purpose processor core and a non-blocking router. The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW ISA with a few important and peculiar features.

Tilera's PR department is extremely focused on the mesh network and larger SoC architectures as the initial selling points of the processor, so information on the individual cores is hard to come by. Based on my discussion with Tilera and the diagrams that the company provided (see below), each core has a register file and three functional units: two integer ALUs and a load-store unit. The cores also have a split L1 cache (probably 16K), and a 64K chunk of L2 that has an interesting feature. When there's a miss in one core's L2, the core checks the L2 caches of the other cores for the needed data before propagating the miss out to main memory. In this respect, the L2s collectively act like a large 4MB L3.

As you can probably make out from the diagram above, TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a flexible I/O interface that can be software-configured to handle a number of protocols.

TILE64 is fabbed on TSMC's trailing-edge 90nm process and runs at speeds from 600MHz to 900Mhz. The launch of a 90nm product at a time when the processor market is moving from 65nm to 45nm was undoubtedly done in order to keep costs down. Tilera won't be able to afford to migrate this product to a smaller process node until they get enough volume to justify the investment.

The initial entries in the TILE64 line are now shipping on PCIe daughterboards for development and production purposes. The processor is also available in lots of 10,000 for $435, and further entries to the TILE family are planned to include different core counts.