Aries’ “M100PFS” module runs Linux on Microchip’s RISC-V based PolarFire SoC with FPGAs up to 265K LE. Features include up to 8GB LPDDR4, up to 64GB eMMC, and support for up to 16x SERDES lanes.



Aries Embedded announced one of the first compute modules equipped with the PolarFire SoC, a Linux-powered, FPGA-enabled RISC-V SoC from Microchip’s Microsemi unit (see farther below). The M100PFS has the same 74 x 42mm footprint as Aries’ similar M100PF module, which is equipped with the PolarFire FPGA without the Linux-ready RISC-V cores.







M100PFS

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The M100PFS supports applications including wireline access networks, cellular infrastructure, defense, commercial aviation, industrial automation, and IoT. Other Linux-ready modules from Aries include the M6UL

This is the first board-level implementation of the PolarFire SoC we’ve seen except for Microchip’s official, $2,000 dev kit. There’s also an upcoming, and presumably more affordable, PolarFire SoC Icicle Kit in the works with 40-pin GPIO. A few details on the Icicle kit were leaked in December when Microchip launched its early access program to its Linux-compatible “Mi-V” RISC-V development tools for the PolarFire SoC. At the time, the production release was scheduled for Q3 2020, the same as for the Aries modules.

Unlike the FPGA-only M100PF module, the new M100PFS supports more entry-level FPGA models. Two versions of the M100PFS module with different FPGA capabilities are available for order with shipments due in Q3 2020. Mid-range 93KLE and 161KLE FPGAs are available on request, and the largest 460K LE capability will be available in a later model.

The two major M100PFS SKUs are:

M100PFS-025ADA0 — MPFS025T FPGA with 23K LE, 68 math blocks, 4x SERDES; 1GB LPDDR4 RAM for HMS (RISC-V/Linux); 4GB eMMC

— MPFS025T FPGA with 23K LE, 68 math blocks, 4x SERDES; 1GB LPDDR4 RAM for HMS (RISC-V/Linux); 4GB eMMC M100PFS-250AECC — MPFS250T FPGA with 254K LE, 784 blocks, 16x SERDES; 4GB LPDDR4 each for HMS and FPGA; 8GB eMMC

All the models that can be ordered now provide 12.5Gbps SERDES and 2x PCIe root port/end points. There are 2x 64-bit AXI4 processor-to-fabric interfaces and 3x 64-bit AXI4 fabric-to-processor interfaces, as well as a 32-bit APB processor-to-fabric link.

The M100PFS integrates 32 MBit SPI NOR flash accompanied by an “execute in place” Quad SPI flash controller. It also supports up to 64GB eMMC on request.







M100PFS and block diagram

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M100PFEVP

The 3.3V, 0 to 70°C tolerant module has dual 180-pin Samtec board-to-board connectors to express I/O including 2x GbE, 2x CAN 2.0 A and B, 2x SPI, 2x I2C, 5x multi-mode UARTs, and single USB 2.0 OTG and MMC 5.1 SD/SDIO connections. The module offers GPIO, an RTC, a clock distribution, and various timers, including 5x watchdogs.

There was no mention of a carrier board, but the FPGA-only M100PF module has an optional M100PFEVP baseboard. The carrier is equipped with a microSD slot plus 2x GbE ports, a micro-USB port, and 4x DB9 ports, including 2x UART and 2x CAN ports. The M100PFEVP is further equipped with a TFT, HSMC, and 3x PMOD connectors.

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The M100PFS module will be available with the Linux- and FPGA PolarFire SoC development tools described below. Aries has introduced a variety of Linux-enabled compute modules based on Intel PSG (Altera) FPGA SoCs. Eval kits based on the modules include the Arria 10 SoC based MAXEVK and the Cyclone V SoC powered MCV.



PolarFire SoC background

Microchip’s PolarFire SoC combines its previously launched PolarFire FPGA with 4x RISC-V U54-MC CPU cores supplied by SiFive. Microchip claims PolarFire SoC advantages over hybrid Arm/FPGA SoCs like the Xilinx Zynq such as the more customizable, open RISC-V design, lower power consumption and much better real-time deterministic capabilities. In December, the company called it “the first SoC FPGA with a deterministic, coherent RISC-V CPU cluster and a deterministic L2 memory subsystem enabling Linux plus real-time applications.”







PolarFire SoC architecture

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The PolarFire SoC uses a modified version of SiFive’s 28nm fabricated, 960MHz to 1.5GHz U54-MC quad-core complex, which also powers SiFive’s Freedom U540 SoCs on its HiFive Unleashed development board. The official PolarFire SoC dev kit combines the SBC with Microchip’s own previously released, PolarFire FPGA equipped HiFive Unleashed Expansion Board

Branch predictors on the U54-MC cores have been deactivated to enable more deterministic behavior, among other changes. The PolarFire SoC inherits the extensive security and reliability features of the PolarFire FPGA. These include single and double error correction and double error detection (SEC-DED) on all memories.



Further information

The M100PFS is available for order with pricing undisclosed. It’s expected to ship in Q3 2020. Early access and customization services are available by special request. More information may be found in the Aries Embedded announcement and product page.