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RC 2017/10 was my first retrochallenge. I reverse engineered the Berkely Softworks georam for Commodore 64/128 computers, published the design files and built a clone. For RC2018/04 I’d like to pick up where I left off and design a 4MB version of the ram expansion.

The Berkeley Softworks geroam is a 512K memory expansion for the Commodore 64/128 originally designed for GEOS. It was designed completely using standard TTL chips so reverse engineering was quite easy. For the 4MB version the plan is to use a simple PLD to reduce the number of chips.

The original schematics can be partitioned in a few main blocks. The register section is formed by U3B, U4, U5 and U13A. The decoder U13A select the correct register based on IO/2 (the system asserts this when the address is within $df00-$dfff), A0 and A7. Because of the incomplete decoding the two registers are mirrored in the range $df80-$dfff. U3B produces a clean clock for U4 and U5, if the enable is asserted a write to the register will occur. U4 maps to $dfff (block register) and U5 maps to $dffe (page register).

The memory section includes U6-8, U9-U12 and U13B. DRAMs require the address to be split into Row and Column which are multiplexed on the same pins. The three 74HC157 multiplexers (U6-U8) serve exactly this purpose. The U13B decoder selects the DRAM array if the I/O1 signal is asserted ($de00-$deff) and generates the output enable (OEx) or write enable (WEx) to the correct set of DRAMs. U10 and U12 map to the first 256KB of expanded memory while U9 and U11 map to the second 256KB section.

The memory control end refresh section includes U1, U2 and U3A. The circuit is very clever. A 4 bit bidirectional shift register is used to create a state machine that generates the RAS#, CAS# and SEL for both access cycles and refresh cycles. The state machine is clocked by the Commodore dot clock which is 8 times faster than PHI2. Memory refresh is performed while PHI2 is deasserted to allow the CPU to access the memory without any wait states.

DOT_CLOCK PHI2 RAS# SEL CAS# Notes 0 1 1 1 1 idle 1 1 0 1 1 RAS# asserted 2 1 0 0 1 SEL mux switch 3 1 0 0 0 CAS# asserted 4 0 1 1 1 idle 5 0 1 1 0 CAS# before RAS# refresh cycle 6 0 1 0 0 7 0 0 0 0

The table above shows the valid states and the sequences that are used. It’s easy to notice that only 3 of the 4 bits are used and the shift register is reset at the beginning of every half PHI2 cycle with all ones. Then a single zero is shifted in for every dot_clock. The shift direction is determined by the level of the PHI2 clock giving the desired behavior of hidden refresh cycles. The U3A flip-flop is used to initialize the state machine to a known state upon exiting reset. U1A generates PHI2#. U1B and U1C generate the control signals for the shift register to implement the state machine. R1 sharpens the dot_clock rising edge to improve timing.

4MB Design

The design uses two 4Mx4 DRAM chips. The two registers have been extended to full 8-bits (only one needed to be, but using the same IC makes BOM management simpler). All the logic is implemented in a 16V8 PLD. The Row and Column multiplexers are not changed. In the next part I will be discussing the layout progress and the PLD code.