Device properties

In this work, 5 μm × 5 μm Pt/W/TaO x /Pt cross-point devices arranged in word structures (Fig. 1a) are used to realize the three Trit (trinary digit) modular addition. The device stack 25 nm Pt/ 13 nm W/7 nm TaO x /30 nm Pt is depicted in Fig 1b. The typical I-V characteristic of this device is shown in Fig. 1c. In supplementary S1, the I-V characteristic of an 80 nm × 80 nm cross-point device is also shown, highlighting the scaling potential of these devices. During RESET process, the maximum applied voltage |V stop | defines the final resistive state (1.8 V in Fig. 1c). This feature is also present in pulse mode, thus can be implemented in memory and logic operations for controlling the multi-level states.

Figure 1 Resistive switching device structures. (a) Scanning electron microscopy image of 1 × 3 array with the inset showing 5 × 5 μm2 single device (b) Transmission electron microscopy image of single device cross-section, 7-nm-thick TaO x switching layer and 13-nm-thick tungsten ohmic electrode. (c) Typical bipolar operation of SET-RESET switching in DC sweep mode for a single ReRAM (5 × 5 μm2) device within the 1 × 3 array. Full size image

Figure 2a shows the cumulative probability of low resistance state (LRS) and six multi-level resistive states, which are obtained for 200 ns pulses in the range of V stop = −1.50 V to −2.25 V. Each state is based on 5 devices with 10 cycles. The inset explains the statistical information of distribution. The tight distribution highlights the excellent switching properties of this device. In Fig. 2b, the mean value for each of the resistive state R0 to R5 is given.

Figure 2 Resistance distribution. (a) Pulses of 200 ns and pulse height in the range of −1.5 V to −2.25 V (0.15 V steps) enable highly accurate resistive state control. (b) Mean values of the final resistance levels. Full size image

For the proposed arithmetic operation, the input operands are applied to the top (TE) and bottom (BE) electrode, respectively. To enable an equidistant voltage stepping, we use a predefined OFFSET voltage (V OFFSET ) for each pulse. The operand voltages are V op = 0.00 V to 0.75 V with increment of 0.15 V. The actual pulse applied at the bottom electrode is therefore V BE = V OFFSET + V op1 and V TE = −(V OFFSET +V op2 ) for the top electrode. Thus, the overall potential difference is V stop = V TE –V BE = −(2 V OFFSET + V op1 + V op2 ). Since the overall device voltage is always negative, a logic operation corresponds to a RESET pulse whose amplitude depends on the actual operands. To show the multi-level pulse operation mode, we set V BE = 0.75 V and vary V TE from −0.75 V to −1.50 V (Fig. 3a). The resulting resistances are depicted in Fig. 3b. Depending on the overall device voltage (V stop = −1.50 V to −2.25 V) six different resistance states (R0, R1, R2, R3, R4 and R5) are easily accessible (Fig. 3b). Note that three resistive states would be sufficient to represent a ternary numeral system (Trit). This multi-level device property is used for the modular arithmetic operation. To enable highly reproducible RESET operation, we always apply a DC SET operation before each pulsed RESET operation. Note that also nanosecond pulsed SET operations are feasible, but not applied in this work. Details on the pulsed SET operation can be found in Supplementary S2.

Figure 3 Basic logic functionality. (a) The logic operands p and q are applied to top (TE) and bottom (BE) electrode, respectively. An OFFSET voltage V OFFSET is used to enable an equal stepping of operand voltages. In this example, V op1 = 0 V holds while V op2 is varied from 0 V to 0.75 V. (b) Depending on the pulse height, R0…R5 are written to the device. Here, a read-out voltage of 0.1 V was used to show the actual resistive states. Full size image

Developed Modular Arithmetic Working Principle

The new developed algorithm calculates the carries and sums directly in the ReRAM devices, which store the results until they are read out. Initially, all the devices in a wordline are initialized, i.e. written to the LRS. Starting from this state the sum bit of significance 0 (s 0 ) can be directly calculated in the device of significance 0 while the other devices are calculating the first output carry c 1 . The actual sum or carry calculating devices are shifted for each significance one device to the left.

In general, for the carry algorithm (Fig. 4a), first the device state of the actual device is read, to check whether the input carry c in is 0 or 1. In case of 1, V OFFSET is set to 0.875 V whereas in case of 0, the OFFSET remains V OFFSET = 0.75 V. Next, the logic operation is conducted after a SET operation using the evaluated OFFSET. We apply V TE = −(V OFFSET + V op1 ) to the top electrode and V BE = V OFFSET + V op2 to the bottom electrode. Finally, the resistive state of the device is read and evaluated. To enable a proper modulus operation the ReRAM device has to provide 2n states for an n-ary number system. The background is that in a n-ary number system the operands at each specific significance are in the range of 0…n-1, i.e., the sum of two operands is at most 2n-1. Since, an input carry of 1 may also occur, the totally required number of states per device is 2n. Thus, for a ternary number system six states (R0…R5) are required. If the state is R ≤ R2, the output carry c out is 0 and R0 is written back. For R > R2, the device is written to R1, i.e. c out = 1. Note that prior to the write back operation, the SET operation is conducted to enable a highly controlled R1 state. In supplementary S4, the required peripheral circuitry is depicted. Note that a certain minimum crossbar array size is required to justify the peripheral circuitry overhead. In this respect, a suitable selector device is a key component enabling large-scale ultra-dense multi-level ReRAM arrays.

Figure 4 State machine. (a) Algorithm for carry calculation. First, the input carry is read and OFFSET is adjusted correspondingly. Next, the logic operation is conducted and high resistive states >R2 are mapped to R1 otherwise to R0. (b) Algorithm for sum calculation. The OFFSET evaluation and logic signal application is the same as for carry. The mapping is as follows: R3 → R0, R4 → R1 and R5 → R2. Start and stop of the algorithm are marked by light blue color, Read by blue color, and logic and RESET steps by yellow color. Full size image

Based on the input carry, the final sum can be calculated (Fig. 4b). As for the carry calculation, the required level of the V OFFSET (either 0.75 V or 0.875 V) is first evaluated. Next, the operand voltages V TE = −(V OFFSET + V op1 ) and V BE = V OFFSET + V op2 are applied after the SET operation. Based on a final readout, the mapping R3 → R0, R4 → R1 and R5 → R2 has to be conducted to complete the modulo sum operation. The corresponding write back operation is done subsequently after the SET operation.

Since the signals which are applied to the TE are the same in both algorithm, these can be conducted in parallel on devices of different significance. Thus the cycle count can be kept low.

Proof-of-concept

For the proof-of-concept measurement, a two Trit modular addition is selected, adding the ternary numbers p = p 1 p 0 and q = q 1 q 0 . Since the sum output z = z 2 z 1 z 0 needs three Trit digits, three ReRAM devices are required for this operation and initialized to LRS firstly. The addition is performed in a word-line structure (cf. Fig. 1a). For the exemplary addition, operand 1 is p = 21 (=7) and operand 2 is q = 22 (=8). Note that input 0 corresponds to V op = 0.00 V, input 1 corresponds to V op = 0.15 V and input 2 corresponds to V op = 0.30 V, using the earlier described incremental stepping of 0.15 V. In Fig. 5a–c, the sequentially obtained resistive states are shown. The arrows mark the order of steps without showing the in between SET-steps.

Figure 5 Proof of concept measurement. This example is for p = 21 (2·3 + 1 · 1 = 7) and q = 22 (2·3 + 2 · 1 = 8). (a) The sequence of resistive states in ReRAM device z 2 , (b) ReRAM device z 1 and (c) ReRAM device z 0 . The final values are: z 2 = R1, z 1 = R2 and z 0 = R0. This corresponds to 1·9 + 2 · 3 + 0·1 = 15. Numbers and arrows indicate the state changes. In between SET-steps are not shown. Full data for this example can be found in supplementary S4–S6. Full size image

The algorithm described in Fig. 4 realizes the following mathematical modulo sum operation:

In device z 0, the sum operation is conducted directly:

z 0 = (1 + 2) rem 3 = 0 (s 0 ).

Note that the function ‘rem’ returns the remainder. Starting from LRS, the device is reset (p 0 = 1 = > V TE = −0.9 V and q 0 = 2 = >V BE = 1.05 V, i.e. −1.95 V). According to Fig. 2b, this voltage leads to state R3, as can be also seen in Fig. 5c directly. According to the sum algorithm (Fig. 4b), R3 is finally mapped to R0, see Fig. 5c.

In device z 1 , first the carry operation is conducted:

z 1 = (1 + 2) div 3 = 1 (c 1 = 1).

The function ‘div’ returns the floor quotient. Starting from LRS, the device is toggled to R3 state by applying p 0 and q 0 to calculate the carry c 1 . According to the carry algorithm (Fig. 4a), R3 is then mapped to R1, see Fig. 5b.

Next, the second cell sum Trit is obtained by the following operation:

z 1 = (2 + 2 + c 1 ) rem 3 = 2 (s 1 ).

Since c 1 = 1 holds the V OFFSET = 0.875 V is applied, and the accessed state is R5. According to the sum algorithm (Fig. 4b), R5 is then mapped to R2, see Fig. 5b.

For cell z 2 (Fig. 5a), again the carry operation is conducted first:

z 2 = (1+2) div 3 = 1 (c 1 = 1).

Starting from LRS, R1 state is accessed via R3.

Since we consider a two Trit addition, the final sum bit equals the carry c 2 :

z 2 = (2 + 2 + c 1 ) div 3 = 1 (c 2 = s 2 = 1).

According to the carry algorithm (Fig. 4a), R5 is then mapped to R1, see Fig. 5a.

The final sum is stored directly in memory:

Sum z = z 2 z 1 z 0 = 120 (=15).

In Fig. 6 the schematics of applied operation voltages and corresponding states are depicted. The first line shows the voltages at the common bottom electrode (BE) acting as a wordline (WL). The second, fourth and sixth lines show the voltages applied to the three separate top electrodes (V TE2 , V TE1 , V TE0 ) acting as bitlines (BL) while the third, fifth and seventh lines represent the resistance states (R TE2 , R TE1 , R TE0 ) at each BL. The three background colors are used. The gray shows the LRS after SET. The yellow depicts the logic implementations and the blue shows the corresponding states after the logic implementation. Overall twelve steps are presented. Step 1–2 show the initialized LRS and logic implementation. Step 3–4 depict the corresponding resistance states with the the LRS after SET. Step 5–6 show implementations and the corresponding states. The state is set to LRS in Step 7. The logic is implemented with adjusted OFFSEET in Step 8 and the corresponding states are shown in Step 9. The LRS after SET is shown in Step 10. Step 11–12 show the logic implementations and the corresponding resistance states. The states (R TE2 , R TE1 , R TE0 ) shown in Step 12 and Step 6 depict the final sum stored in memory (Sum z = z 2 z 1 z 0 = 120). The more details of overall steps are given in Supplementary S4-S6. A truth table for the overall state definition (R0 – R5) is shown in the Fig. 7. Each combination of p (TE) and q (BE) sets the corresponding state with and without the adjustment of OFFSET.

Figure 6 Schematics of operation. Schematics of operation for applied voltages (V TE , V BE ) are shown. The gray shows the LRS after SET. The yellow depicts the logic implementations and the blue shows the corresponding states after the logic implementation. Step 1 is the LRS after initialization and Step 2 is logic implementation. Step 3 is the resistance states based on Step 2. Step 4 is the LRS after SET and Step 5 implements the RESET for the modulo operation. Step 6 is the corresponding resistance states and Step 7 is the LRS after SET. Step 8 is the logic implementation with adjusted OFFSET and Step 9 is the corresponding resistance states. Step 10 is the LRS after SET. Step 11 is the logic implementation and Step 12 is the corresponding resistance states. Full size image