The Ryzen CPUs are the first products from AMD based on the Zen architecture. Zen is the designation of the micro architecture, which describes the basic structure of the individual chip. AMD integrated some typical improvements, but also some real new features. All of this is supposed to result in an IPC (instruction per cycle) improvement of more than 52 percent.

The rather conventional measures to improve the performance include the size increase of several buffers by at least 50%, and some buffer sizes were even doubled compared to the previous generation.

One of the bigger new features is the Micro-op cache, which can store up to 2000 already decodes micro-ops. Besides performance gains, such a cache will also improve efficiency. The competitor Intel already uses this type of cache since Sandy Bridge, which shows that AMD must catch up.

Four individual cores are combined in a so-called CPU Complex, which share 8 MB L3 cache. Despite the internal cache allocation in so called slices, every core is supposed to access every individual cache area with the same latency. The whole buffer is also supposed to run in sync with the highest clocked core.

Ryzen is also AMD first architecture with simultaneous multi-threading. The basic principle is similar to Intel's Hyper Threading: Thanks to a comparatively small number of additional transistors, every core gets a second virtual core, so two threads can be executed simultaneously.

Every logical core gets both exclusive as well as shared units. The resources of the latter are allocated based on special demand-oriented algorithms, which can result in higher single-core performance in single-thread applications compared to a fixed allocation (like 50/50, for example).

Media reports say that according to AMD, about five percent additional transistors can increase the performance in synthetic benchmarks by up to 41%. However, it is also a fact that SMT does not have any advantages when an application cannot really benefit from the high number of eight cores.

AMD also uses the so called "Infinity Fabric" to connect individual functional units on an architectural level, which is supposed to increase the performance. This is also the end of the module design, where the shared floating point unit could become the bottleneck in certain situations.