A team of scientists in Germany and the US have developed a new kind of logic gate that could crack the size problems haunting the processor industry.

The problem is that the conventional CMOS method of producing chips requires ever-smaller transistors, but once you get to working in measurements of single-figure nanometers, the current production techniques don't work. Other building systems are being trialed but none are ready for full-scale market production at the right price.

Now scientists at the Technische Universität München (TUM) and Notre Dame University in Indiana have published a new paper in the journal Nanotechnology that suggests using 3D-stacked nanomagnets to build a new kind of logic gate.

The system uses three input magnets, one of which sits 60 nanometers below the other two so as to increase magnetic effects. Output comes from a single magnet, which can use the fields generated to signify either a one or zero for binary computation.

New design could prove magnetic for chip firms

"The 3D majority gate demonstrates that magnetic computing can be exploited in all three dimensions, in order to realize monolithic, sequentially stacked magnetic circuits promising better scalability and improved packing density," said TUM doctoral candidate Irina Eichwald, lead author of the paper.

While each of the magnets is comparable in size to a current transistor, they don't need the accompanying wiring that comes in processors today, since they operate using coupling fields. Magnet-based circuits can also require fewer magnets than the equivalent transistor-based circuit would need transistors to get the job done.

In addition, the new magnetic systems use less power than conventional transistors, function well at room temperature, and are resistant to radiation damage.

This kind of system has been demonstrated in 2D setups before, but now the boffins have devised a way to stack them in 3D silos. This means that they can either replace or work in conjunction with existing transistor technology.

"It is a big challenge to compete with silicon CMOS circuits," said Dr. Markus Becherer, leader of the research group within TUM's Institute for Technical Electronics. "However, there might be applications where the non-volatile, ultralow-power operation and high integration density offered by 3D nanomagnetic circuits give them an edge." ®