The RISC-V open standard ISA has been gaining traction in both academic and commercial circles over the last year, during which we've gotten our ports of binutils, GCC, and Linux merged upstream. Additionally, SiFive has announced a Linux-capable, 64-bit, quad core development board which will be available in Q1 2018. This talk discusses the history of the ISA, SiFive's open source RTL implementations of RISC-V, the state of RISC-V software, and our plans for the upcoming year.

The RISC-V instruction set architecture is an open standard originally designed for computer architecture research that, over the past few years, has been gaining widespread popularity in industry: for example, the RISC-V Foundation, which governs the standard, now claims over 100 members. SiFive recently announced the U54 processor IP, a 64-bit, quad core, Linux-capable processor. The Freedom U500 is based on Rocket Chip, an open source processor generator written in Chisel, a HDL implemented as a Scala embedded DSL.

This talk will discuss the RISC-V ISA, and the Rocket Chip processor generator. As the author is a maintainer of the RISC-V ports of binutils, GCC, Linux, and glibc, the main focus of this talk will be on the state of the RISC-V software ecosystem. If everything goes well, the first version of glibc that contains RISC-V support will release right at the start of FOSDEM and I'll be able to announce that the core software is upstream. We have a handful of distribution partners (Debian, Fedora, and OpenEmbedded) actively working on distributions based on our pre-release ports right now, so with any luck we'll also be able to announce early distro support :).

This talk will be followed by a BOF for open discussions about RISC-V ecosystem in room J1.106