At an ISSCC session Monday, Intel went into new detail on its forthcoming 8-core, 16-thread Xeon processor, a 64-bit processor that's a member of the Nehalem family. Much of the session was focused on the packaging and power aspects of the device, so I'll recap some of the more interesting parts of that here.

The Intel presenter explained that the Xeon has three different clock and voltage domains: the core region, the uncore region, and the I/O region. (You may recall from previous coverage of Nehalem that the "uncore" region of the processor is so named because it's the area that doesn't have a processor core in it; this area is mostly cache.)

These separate clock and voltage domains are used for power management, and the isolation that they provide also aids Intel in implementing "Turbo Mode." Turbo mode is Intel's name for its technology that lets it shut down one or more cores in order to focus the chip's power budget on the cores that are actually active (i.e., by increasing the voltage and clockspeed of the active cores). The cores' variable voltage ranges from 0.85V to 1.1V, while the voltages and clocks of the uncore and I/O domains are fixed.

If it's broken, just re-label it

One major part of the Xeon presentation is Intel's "cache and core recovery" scheme, which lets the company salvage a usable part from a defective chip by disabling the defective regions and selling the chip with a lower core count or cache amount.

So for instance, if testing and validation finds a defect in a cache slice on a chip, then Intel can disable that slice and sell the chip with lower cache. And likewise with cores, so that you might buy a six-core chip from Intel that was originally produced as an 8-core Xeon but had two defective cores.

An 8-core Xeon chip with two cores and two cache blocks

The company claims that it can effectively isolate the nonfunctioning cache and cores, so that these extra parts don't increase the chip's power draw by letting through leakage current.

During the Intel presenter's discussion of how this core and cache "recovery" scheme "enables multiple product options" from the same die, I couldn't help but think back to one Intel wag's response to the news of AMD's triple-core "Toliman" part; this guy said, and I wish I could find the quote, something to the effect of, "we like for all of the cores on our products to actually work." It was an ice burn at the time, but now it appears that Intel has bowed to the inevitable realities of Moore's Law and will be taking essentially the same tack with all of their parts from here on out.

Both Intel's 8-core Nehalem and Sony's 8-core (sort of) Cell processor have this sort of capability to shut down a nonfunctioning core at the production stage, so that the companies can still sell the part at a lower core count. I realize that a typical journalist needs at least three data points to spot a "trend," but if you'll indulge me for a moment, I'd like to suggest that the 8-core mark may be the point at which you absolutely have to do this or risk punishingly low yields.

In any event, for as long as the multicore train rolls on, and, as I'll argue in a forthcoming article, it may not be that long, you can expect to see this "disable the broken parts and sell it anyway" strategy used by everyone who's selling into the 8-core and up space.

Listing image by Intel