2nd Workshop on Open-Source Design Automation (OSDA)

A Friaday workshop at the 2020 Conference on Design, Automation, and Test in Europe (DATE)

March 13, 2020, Grenoble, France

PDF version of this CfP

Motivation

Field-programmable gate array (FPGA) technology is becoming more and more relevant: recent examples include Intel’s acquisition of Altera in 2015, Amazon’s 2016 announcement of FPGAs within their AWS cloud infrastructure, and Microsoft’s statement in 2018 that more than 100K FPGAs were deployed in their Azure cloud for machine learning acceleration. With traditional cloud infrastructure -- which are mainly processor based -- software engineers have a choice of open-source (e.g. GNU GCC, Clang) and proprietary compilers (Microsoft, Intel) to use. However, the wide availability of FPGA technology contrasts with the narrow ways in which one can access them -- through proprietary tools.

There is no doubt that proprietary EDA tools are successful, mature, and are fundamental for hardware development. However, the “walled garden” approach created by closed-source toolflows can hamper novel FPGA-based applications and EDA innovation alike by requiring that researchers either operate within the limits of what has already been imagined, or require that they attempt to simulate their effects on incomplete models, potentially leading to incorrect conclusions. For such an off-the-shelf field-programmable technology, unlike fixed-function ASICs, this seems like a lost opportunity.

Another recent development has been growing activity in the open-source community to produce open equivalents of EDA tools, as well as efforts to document FPGA architectures. For instance, Yosys has been widely used for behavioral synthesis since 2012 and Project Icestorm, the first fully open-source FPGA design flow has been available since 2015; together they enabled Trenz Electronic’s icoBOARD, a Raspberry Pi accessory that could be programmed entirely using its ARM CPU, a platform not otherwise supported by the vendor. The availability of low-cost FPGA development boards such as the icoBOARD, TinyFPGA, IceZUM Alhambra, amongst others have also played a part in fostering this “Open FPGA” movement. The advantages of open design automation -- as Linux has provided for operating systems -- are many: unrestricted research and development, improved quality due to competition, teaching benefits, as well as lowering the barrier and risk to entry, and time to market, of start-ups for building novel FPGA applications, tools, and silicon. With such an open-source ecosystem in place, reprogrammable logic could achieve the same success and inspire the next generation of hardware engineers as the Raspberry Pi has done for software engineers.

This workshop intends to provide an avenue for industry, academics, and hobbyists to collaborate, network, and share their latest visions and open-source contributions, with a view to promoting reproducibility and reusability in the design automation space. DATE provides the ideal venue to reach this audience since it is the flagship European conference in this field -- particularly poignant due to the recent efforts across the European Union (and beyond) that mandate “open access” for publicly funded research to both published manuscripts as well as software code necessary for reproducing its conclusions. A secondary objective of this workshop is to provide a peer-reviewed forum for researchers to publish “enabling” technology such as infrastructure or tooling as open-source contributions -- standalone technology that would not normally be regarded as novel by traditional conferences -- such that others inside and outside of academia may build upon it.

Topics of interest

Open-source FPGA tools -- the latest developments, breakthroughs, challenges and surveys on the toolflows required to target real silicon parts: synthesis, simulation, place and route, etc.

Open-source IP for FPGAs -- contributions that enrich the IP ecosystem and reduce the need to “re-invent the wheel”, e.g. PCIe and DDR controllers, debug infrastructure, etc.

Design methodologies provided as open-source -- such as hardware description languages (e.g. MyHDL, Chisel), domain specific (DSL), high level synthesis (HLS), or asynchronous methods.

Directions on where the open-source FPGA movement should go, current weaknesses in the toolchain, and/or perspectives from industry on how open-source can affect aspects of safety, security, verification, IP protection, time-to-market, datacenter/cloud infrastructure, etc.

Discussions and case studies on how to license, acquire funding, and commercialise technologies surrounding open-source hardware, which may be different to open software.

Workshop program

OSDA 2020 will be focussed on open-source hardware verification, and open-source ASIC flows.

Begin End Duration Title 08:30 08:45 0:15 Workshop opening Verification Block 1 08:45 09:45 01:00 Jim Lewis

OSVVM

Open Source VHDL Verification Methodology (OSVVM) is an advanced verification methodology and library that simplifies the creation of structured, transaction-based tests and test environments that are powerful enough for ASIC verification, yet simple enough for small FPGA verification. OSVVM is implemented as two separate open source libraries: OSVVM Utility Library and OSVVM Verification IP Library. Currently these are hosted on GitHub. With the IEEE 1076-2019 standardization effort, the 1076 packages are now IEEE Open Source. Following the path of IEEE 1076, OSVVM has been accepted as an IEEE Open Source project and will bemigrating the primary Git repository to the IEEE hosted site sometime in Q1 2020. OSVVM was named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study. In Europe, VHDL is used in 78% of all FPGA designs and OSVVM is used by 30% of the FPGA Verification teams -- SystemVerilog and UVM is only used by 20% of the FPGA Verification teams. The OSVVM Utility Library uses a set of packages to create features that rival language based implementations (such as SystemVerilog and UVM) in both conciseness, simplicity, and capability. This presentation provides an overview of OSVVM's capabilities, including: transaction-based Modeling, constrained random test generation, functional coverage with an API for UCIS coverage database integration, intelligent coverage random test generation, utilities for testbench process synchronization, utilities for clock and reset generation, transcript files, self-checking -- alerts and affirmations, message filtering -- logs, scoreboards and FIFOs (data structures for verification), memory models. The OSVVM Verification IP Library is a growing set of transaction based models. Currently Looking to improve your VHDL FPGA verification methodology? OSVVM provides a complete solution for VHDL ASIC or FPGA verification. There is no new language to learn. It is simple, powerful, and concise. Each piece can be used separately. Hence, you can learn and adopt pieces as you need them. 09:45 10:00 00:15 Pitch talks for the poster session 10:00 10:30 00:30 Coffee break (and poster session) Verification Block 2 10:30 11:15 00:45 Tristan Gingold

GHDL recent developments and the future of EDA FOSS

GHDL is an open-source VHDL simulator that fully supports VHDL 93 and many features of VHDL 2008. Last year, I got many requests (including at least one at OSDA) to support synthesis. Although this is work in progress, it is now possible to use GHDL as a synthesis front-end for Yosys and to handle non-trivial designs like the microwatt Power cpu. On many fronts, the EDA FOSS is making progress but there are missing features like analog mixed simulation, vhdl/verilog mixed designs or constraints based simulation. 11:15 12:00 00:45 Wilson Snyder

Verilator, Accelerated

In this talk Wilson Snyder will present a quick summary of Verilator, the big 4th simulator, and recent accelerations in feature development, followed by examples of accelerating the simulation runtime of a real RISC-V design. 12:00 13:00 01:00 Lunch break (and poster session) ASIC Block 13:00 13:45 00:45 Jean-Paul Chaput

Coriolis2

Starting in 1990, Sorbonne Université-CNRS/LIP6 developed Alliance, a complete VLSI CAD toolchain released under GPL. In this spirit, we are assembling an upgraded design flow for ASICs based on FOSS tools like GHDL & Yosys for logical synthesis and Coriolis2 for physical design. We will present the flow with a focus on the Coriolis2 part. Its main features are mixed design (digital/analog), symbolic layout (for digital parts) and a comprehensive Python interface. The use of symbolic layout allows portability accross a wide range of nodes and foundries, and most importantly, frees up us from NDA preventing the sharing/reuse of the design layout. This should be an important milestone toward the creation of an open hardware community. 13:45 14:30 00:45 Tim Edwards

Open All the Way

"Open hardware" is traditionally thought of as pertaining to HDL source code for FPGAs. But open EDA tools exist for taking HDL all the way to the foundry to produce a working ASIC. I present several flows for this task, including qflow and OpenROAD; and Ravenna, efabless' new 2ndgeneration RISC-V processor built end-to-end with open EDA tools. 14:30 15:00 00:30 Coffee break (and poster session) FPGA Block 15:00 15:45 00:45 David Shah

Adapting nextpnr to Xilinx FPGAs

nextpnr is an open source FPGA place and route framework which began development in mid 2018, initially containing support for two different Lattice FPGA families but aimed at supporting any real-world architecture. Recent work has focussed on supporting the popular Xilinx 7-series and UltraScale+ FPGAs using two other open source projects, RapidWright and Project X-ray. These larger and more advanced FPGAs have provided some interesting challenges in packing, placement, routing and even bitstream generation. Although support is still experimental, nextpnr is now capable at building complex real-world designs for these architectures such as 64-bit SoCs with DDR3 memory. 15:45 16:45 01:00 Claire Wolf

The Yosys ecosystem

Yosys is an open source HDL synthesis tool and more, with applications in synthesis for FPGAs and ASICs, and formal verification. This presentation gives a broad overview over the Yosys ecosystem, with a closer look at FPGA synthesis for Lattice iCE40 (with Project Icestorm), Lattice ECP5 (with Project Trellis), and Xilinx devices (with Project X-Ray and Project Leuctra), as well as formal verification (SBY, MCY). The low cost of the open source formal verification tools, as well as the low cost of commercial tools based on that open source infrastructure, allows the use of formal verification techniques in new ways, beyond traditional use-cases for formal hardware verification tools. 16:45 17:00 00:15 Workshop closing 17:00 17:30 00:30 (Optional) Holistic plenary discussion on the workshop and future directions of OSDA

Poster session

Title Goavec-Merou, G.; Hugeat, A.; Bernard, J.; Bourgeois, P.-Y. & Friedt, J.-M.

Platform independent CPU-FPGA co-design framework: application to cascaded finite impulse response filter synthesis Zeller, H.

SystemVerilog support in Open Source Tools Rodriguez-Ferrandez, I.; Cabo, G.; Barrera, J.; Giesen, J.; Jover-Alvarez, A. & Kosmidis, L.

Skeletor: An Open Source EDA Tool Flow from Hierarchy Specification to HDL Development Le Lann, J.-C.; Badier, H. & Kermarrec, F.

Towards a Hardware DSL Ecosystem: RubyRTL and Friends Melo, R. A.; Valinoti, B.; Cicuttin, A.; Crespo, M. L.; Garcia, L.; Mannatunga, K. S. & Samayoa, W. O. F.

ComBlock: a simple core for FPGA-processors communication Melo, R. A. & Valinoti, B.

PyFPGA: a Python Package to abstract the use of FPGA development tools

Important dates

What When Submission deadline January 12, 2020 Acceptance notification January 19, 2020 January 26, 2020 Camera-ready final version February 19, 2020 Workshop March 13, 2020

Submission details and requirements

Prospective authors are invited to submit original contributions (up to six pages), extended abstracts describing work-in-progress or position papers (not exceeding two pages), and demo proposals that would be of general interest. Papers must be submitted as an A4-sized PDF, in the IEEE conference format.

In line with OSDA’s mission, we encourage and will favour submissions that make all artifacts used for experimentation (benchmarks, code, etc.) available for private peer-review. Accepted submissions are required to publish these artifacts under an OSI-approved (preferably permissive) license.

The proceedings of this workshop containing all accepted papers will be published on the open-access arXiv repository. Every accepted paper must have at least one author registered to attend the workshop by 31 January. Selected papers may also be considered for a special-issue journal.

Submission closed

Registration link

Organizing Team

Claire Wolf, SymbioticEDA, Austria

Christian Krieg, TU Wien, Austria

Program Committee

Andrea Borga, oliscience, Netherlands

Xin Fang, Qualcomm, USA

Hipolito Guzman-Miranda, University of Seville, Spain

Steve Hoover, Redwood EDA, USA

Dirk Koch, University of Manchester, UK

Mieszko Lis, University of British Columbia, Canada

Brent Nelson, Brigham Young University, USA

Steffen Reith, RheinMain University of Applied Sciences, Germany

Davide Rossi, University of Bologna, Italy

Get Social

If you want to promote our initiative on social media channels please make use of the following official hashtags:

#OSDA2020 #OSDAconference #FPGA #DATEconference

We would very much appreciate if you help spreading the word!

Contact

Dr. Christian Krieg TU Wien christian.krieg(here.comes.the.sign.you.expect.here)tuwien.ac.at