newtekie1 The memory controllers are the memory bus.

No they are not , the bus is one component , namely the wiring that connect the memory and the controller is another. Bus load is somewhat of an improper metric , it's either on or off for a specific amount of clock cycles while the controller reads/writes on the data lines but the act of reading and writing can occur much slower/faster than what the bus can allow.You can totally change the bandwidth of a data transmissions by using a controller that say only reads the data lines each 2 cycles, therefor you can have a bus that's used "100%" but where the resulting bandwidth is half of what it can be because of the controller. And this can happen the other way around as well. Your thinking is flawed because you assume that the controllers are always as fast or slower than what they would need to be for a specific bus/clock combination.An obvious sign that controller load is independent from the default bus/frequency configuration the fact that you can overclock the memory and it will all still function correctly. Sure the controller may only be wired for 32 data lines but that doesn't mean it can't be faster than that and therefor report lower utilization. Bus load =/= memory controller load otherwise why would there even be a distinction between the two in the first place , come on man. :laugh: