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Gary Mobley, chip analyst with The Benchmark Company, this afternoon held a fascinating conference call concerning one of the most intriguing discussions going on in semiconductors today: RISC-V.

That is the name of a non-profit foundation founded by U.C. Berkeley professor David Patterson and his team to create one single “instruction set architecture” that can be used across all manner of chips, from the humblest embedded part on up to big server computers.

The man running the foundation, Rick O’Connor, a veteran of many chip companies, talked the audience through a series of slides, with some questions by Mobley at the end.

RISC-V has gained traction outside of academia.

Nvidia (NVDA) plans to put use ISA across all the “Falcon” CPUs that it puts in its various GPU chips, and Western Digital (WDC) has said it will use RISC-V across its processors.

As O’Connor describes it, RISC-V is a “dictionary” of all the words and phrases that can be used to make a chip run software. It is meant to replace the jumble of lexicons that run existing chips, such as Intel’s (INTC) “x86” instruction set, and ARM’s instruction set.

O’Connor’s sales pitch for RISC-V is that it is “far smaller than other commercial ISAs,” which can produce economic benefits when making chips with it; it is a “clean slate” approach, which has carefully thought through things such as what parts should be “user space,” in a chip, and what “privileged,” which might help avoid some really bad security issues like the recent “Spectre” bug faced by Intel; and it is designed to be extended as chips need to gain new capabilities.

As O’Connor explained in a single slide, the one pasted at the top of this post, most computing devices today are in a sense trapped in some “proprietary” instruction set, such as Intel’s. RISC-V suggests a certain lessening of the dominance of individual vendor designs, he implied.

Bear in mind, RISC-V is just the dictionary; it’s copyrightable, but not patentable. The actual underlying circuit designs still have to come from a chip vendor, which means there’s plenty of design work for Intel and Nvidia and others to do.

At the same time, Mobley, interestingly, asked if the ISA itself could be an “alternative” to a GPU or a digital signal processor (DSP).

O’Connor seemed to indicate that was the case, saying “As they exist today, if you start implementing that kind of functionality — such as vector instructions, for example -- you can implement all that functionality using the set of RISC-V extensions, instead of a proprietary instruction set architecture that might have existed up until now.”

That raises an interesting question for Nvidia as it rolls RISC-V out in chips in its next iteration of Falcon. Will an open, shared, standard ISA erode any of the lock-in that Nvidia gets for its GPUs? Or is the “CUDA” programming environment really the important software layer that helps Nvidia maintain and extend its dominance in programming?

Patterson, and RISC-V, made a big splash a year ago, when he described work that had been done at Alphabet’s (GOOGL) Google to develop the so-called “tensor processing unit” for Google’s cloud computing operations. The TPU, which Patterson and his team claim can achieve vast improvements in performance and efficiency versus Intel and Nvidia chips, was itself a result of work on RISC-V, as I explained in an article last summer in Barron’s print magazine.