That is the unfortunate effect of using a separate memory controller and I/O die.The cores and their L2/L3 cache are now not directly connected to the IMC, but go through an IF link first, then the internal routing of the "North Bridge" die.Latency will increase, there's no way around it...The reason cache size was increased is to compensate for this design quirk.I'm guessing it works fine... people game on their Threadrippers, and they have the same "issue" of having to jump on IF link to get to memory.

well you can't have it all,but this is what we've got so far-same core count for skus, r3 is 4c/8t,r5 is 6c/12t,r7 is 8c/16t.seems like the main point of this design was to introduce 12c for mainstream boards-boost frequencies around 300mhz higher than 12nm-same or worse latency-higher cache size-memory limitations pushed a bit higher-higher price both for skus and for the boards

The only reason for chiplets is production cost.



Half the chip(let) size may 5 times lower production cost. Weird huh ? It's because the unavoidable defects in the silicon... and the smaller you get, the higher chance that you end up with a perfectly working chip.

So AMD can produce these cheaper than with a monolithic design and have more profit, which they seriously need...

The fact that it has some performance benefit is just a +



Oh, and they can shove more cores in due to that significant production cost reduction...



I'm guessing it's literally cheaper for them to make 1x 16-core 3950X than it was to make 1x 8-core 1800X, but they are selling it with 50% higher launch price.

And still, for the consumers, the price per core is lower. Magic !