Value Deliverables

Programmable System Integration Up to 5.5M System Logic Cells at 20nm using 2 nd generation 3D IC

generation 3D IC Integrated 100G Ethernet MAC and 150G Interlaken cores

Increased System Performance Up to two speed-grade improvement with high utilization

30G transceivers for chip-to-chip, chip-to-optics, 28G backplanes

16G backplane capable transceivers at half the power



2400Mb/s DDR4 for robust operation over varying PVT

BOM Cost Reduction Up to 50% lower cost – half the cost per port for Nx100G systems

VCXO and fractional PLL integration reduces clocking component cost

2400Mb/s DDR4 in a mid-speed grade

Total Power Reduction Up to 40% lower power vs. previous generation

Fine granular clock gating with ASIC-like clocking

Enhanced System Logic Cell packing reduces dynamic power