

new file mode 100644

index 00000000000..ec0a791119b

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/Kconfig b/src/mainboard/cavium/Kconfignew file mode 100644index 00000000000..ec0a791119b--- /dev/null+++ b/ src/mainboard/cavium/Kconfig @@ -0,0 +1,30 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Facebook Inc +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +if VENDOR_CAVIUM + +choice + prompt "Mainboard model" + +source "src/mainboard/cavium/*/Kconfig.name" + +endchoice + +source "src/mainboard/cavium/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Cavium" + +endif # VENDOR_CAVIUM

new file mode 100644

index 00000000000..e1d0b64d4da

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/Kconfig.name b/src/mainboard/cavium/Kconfig.namenew file mode 100644index 00000000000..e1d0b64d4da--- /dev/null+++ b/ src/mainboard/cavium/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_CAVIUM + bool "Cavium"

new file mode 100644

index 00000000000..c311b1dbd8f

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig b/src/mainboard/cavium/cn8100_sff_evb/Kconfignew file mode 100644index 00000000000..c311b1dbd8f--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/Kconfig @@ -0,0 +1,68 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2018 Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_CAVIUM_CN8100_SFF_EVB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select COMMON_CBFS_SPI_WRAPPER + select RTC + select SOC_CAVIUM_CN81XX + select SPI_FLASH + select SPI_FLASH_STMICRO + +config MAINBOARD_DIR + string + default "cavium/cn8100_sff_evb" + +config MAINBOARD_VENDOR + string + default "Cavium" + +config DRAM_SIZE_MB + int + default 8192 + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 0 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0x87E028000000 + +config UART_FOR_CONSOLE + int + depends on DRIVERS_UART + default 0 + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +########################################################## +#### Update below when adding a new derivative board. #### +########################################################## +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "CN8100_SFF_EVB" + +endif

new file mode 100644

index 00000000000..988be4a8f9c

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/Kconfig.name b/src/mainboard/cavium/cn8100_sff_evb/Kconfig.namenew file mode 100644index 00000000000..988be4a8f9c--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_CAVIUM_CN8100_SFF_EVB + bool "CN8100 SFF EVB"

new file mode 100644

index 00000000000..97a03c4d28d

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/Makefile.inc b/src/mainboard/cavium/cn8100_sff_evb/Makefile.incnew file mode 100644index 00000000000..97a03c4d28d--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/Makefile.inc @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c +bootblock-y += memlayout.ld + +romstage-y += memlayout.ld +romstage-y += romstage.c +romstage-y += bdk_devicetree.c + +ramstage-y += mainboard.c +ramstage-y += memlayout.ld +ramstage-y += bdk_devicetree.c + +verstage-y += memlayout.ld

new file mode 100644

index 00000000000..7bc04ce01e8

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c b/src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.cnew file mode 100644index 00000000000..7bc04ce01e8--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/bdk_devicetree.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +// This file is automatically generated. +// DO NOT EDIT BY HAND. + +#include <bdk-devicetree.h> + +const struct bdk_devicetree_key_value devtree[] = { +{"DDR-CONFIG-DQX-CTL", "0x4"}, +{"DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2", "0xc0c0303"}, +{"DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1", "0x1030203"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-WR.RANKS4", "0x1"}, +{"DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1", "0x1"}, +{"DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2", "0x2"}, +{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0", "0x4"}, +{"DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2", "0x4"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0", "0x1"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0", "0x5"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2", "0x5"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0", "0x2"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1", "0x2"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2", "0x1"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0", "0x6"}, +{"DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1", "0x6"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0", "0x22"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0", "0x1f"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2", "0x1f"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0", "0x19"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1", "0x19"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2", "0x19"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0", "0x1f"}, +{"DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1", "0x1f"}, +{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1", "0x7"}, +{"DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2", "0x3"}, +{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1", "0x3"}, +{"DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2", "0x7"}, +{"DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1", "0x7"}, +{"DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2", "0x4080102"}, +{"DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1", "0x1010202"}, +{"DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX", "0x1"}, +{"DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX", "0x7"}, +{"DDR-CONFIG-CUSTOM-MIN-RODT-CTL", "0x1"}, +{"DDR-CONFIG-CUSTOM-MAX-RODT-CTL", "0x7"}, +{"DDR-CONFIG-CUSTOM-CK-CTL", "0x4"}, +{"DDR-CONFIG-CUSTOM-CMD-CTL", "0x4"}, +{"DDR-CONFIG-CUSTOM-CTL-CTL", "0x4"}, +{"DDR-CONFIG-CUSTOM-OFFSET-EN", "0x1"}, +{"DDR-CONFIG-CUSTOM-OFFSET", "0x2"}, +{"DDR-CONFIG-CUSTOM-DDR2T", "0x1"}, +{"DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT", "0x2"}, +{"DDR-CONFIG-CUSTOM-FPRCH2", "0x2"}, +{"PHY-ADDRESS.N0.BGX0.P0", "0xff000010"}, +{"PHY-ADDRESS.N0.BGX0.P1", "0xff000011"}, +{"PHY-ADDRESS.N0.BGX0.P2", "0xff000012"}, +{"PHY-ADDRESS.N0.BGX0.P3", "0xff000013"}, +{"PHY-ADDRESS.N0.BGX1.P0", "0xff002014"}, +{"PHY-ADDRESS.N0.BGX1.P1", "0xff002014"}, +{"PHY-ADDRESS.N0.BGX2.P0", "0xff000000"}, +{"BGX-ENABLE.N0.BGX0.P0", "1"}, +{"BGX-ENABLE.N0.BGX0.P1", "1"}, +{"BGX-ENABLE.N0.BGX0.P2", "1"}, +{"BGX-ENABLE.N0.BGX0.P3", "1"}, +{"BGX-ENABLE.N0.BGX1.P0", "1"}, +{"BGX-ENABLE.N0.BGX1.P1", "1"}, +{"BGX-ENABLE.N0.BGX2.P0", "1"}, +{"BDK-NUM-PACKET-BUFFERS", "0x1000"}, +{"BDK-PACKET-BUFFER-SIZE", "0x400"}, +{"BDK-SHOW-LINK-STATUS", "1"}, +{"BDK-COREMASK", "0"}, +{"MULTI-NODE", "0"}, +{"QLM-AUTO-CONFIG", "0"}, +{"QLM-DIP-AUTO-CONFIG", "1"}, +{"DDR-SPEED.N0", "1333"}, +{"DDR-CONFIG-SPD-ADDR.DIMM0.LMC0", "0x1050"}, +{"USB-PWR-GPIO.N0.PORT0", "12"}, +{"USB-PWR-GPIO-POLARITY.N0.PORT0", "0"}, +{"USB-REFCLK-SRC.N0.PORT0", "0"}, +{"GPIO-PIN-SELECT-GPIO15", "0x24f"}, +{"GPIO-PIN-SELECT-GPIO16", "0x24e"}, +{"GPIO-PIN-SELECT-GPIO17", "0x24b"}, +{"GPIO-PIN-SELECT-GPIO18", "0x247"}, +{"GPIO-PIN-SELECT-GPIO19", "0x24d"}, +{"GPIO-PIN-SELECT-GPIO20", "0x24c"}, +{"GPIO-PIN-SELECT-GPIO37", "0x24a"}, +{"GPIO-PIN-SELECT-GPIO38", "0x246"}, +{"GPIO-PIN-SELECT-GPIO7", "0xe1"}, +{"GPIO-PIN-SELECT-GPIO24", "0xeb"}, +{"GPIO-PIN-SELECT-GPIO27", "0xed"}, +{"GPIO-PIN-SELECT-GPIO28", "0xe3"}, +{"GPIO-PIN-SELECT-GPIO29", "0xe0"}, +{"GPIO-PIN-SELECT-GPIO30", "0xe2"}, +{"GPIO-PIN-SELECT-GPIO40", "0x112"}, +{"GPIO-PIN-SELECT-GPIO41", "0x113"}, +{"GPIO-PIN-SELECT-GPIO42", "0x114"}, +{"GPIO-PIN-SELECT-GPIO43", "0x115"}, +{"GPIO-PIN-SELECT-GPIO44", "0x116"}, +{"GPIO-PIN-SELECT-GPIO45", "0x117"}, +{"GPIO-PIN-SELECT-GPIO46", "0x118"}, +{"GPIO-PIN-SELECT-GPIO47", "0x119"}, +{"GPIO-POLARITY-GPIO7", "1"}, +{"GPIO-POLARITY-GPIO27", "1"}, +{"GPIO-POLARITY-GPIO28", "1"}, +{"GPIO-POLARITY-GPIO30", "1"}, +{0, 0}, +};

new file mode 100644

index 00000000000..19987274ff0

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/board.fmd b/src/mainboard/cavium/cn8100_sff_evb/board.fmdnew file mode 100644index 00000000000..19987274ff0--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/board.fmd @@ -0,0 +1,24 @@ +FLASH@0x0 8M { + WP_RO@0x0 0x400000 { + RO_SECTION@0x0 0x200000 { + # bootblock includes trusted/non-trusted CLIB, CSIB, + # and BL1FWs packaged in + # src/soc/cavium/common/Makefile.inc. + BOOTBLOCK@0x10000 0x70000 + FMAP@0x90000 0x1000 + COREBOOT(CBFS)@0x100000 0x100000 + } + } + RW_SECTION_A@0x400000 0xe8000 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0xe5f00 + RW_FWID_A@0xe7f00 0x100 + } + RW_UNUSED@0x4e8000 0x8000 + RW_ELOG@0x5d8000 0x1000 + RW_SHARED@0x5e0000 0x10000 { + SHARED_DATA@0x0 0x10000 + } + RW_NVRAM@0x5f0000 0x10000 + CONSOLE@0x700000 0x100000 +}

new file mode 100644

index 00000000000..98a6c46b7f3

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/board_info.txt b/src/mainboard/cavium/cn8100_sff_evb/board_info.txtnew file mode 100644index 00000000000..98a6c46b7f3--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Cavium +Board name: CN81XX SFF EVB +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n

new file mode 100644

index 00000000000..36332cc6e37

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.cnew file mode 100644index 00000000000..36332cc6e37--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/bootblock.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/soc.h> +#include <soc/spi.h> +#include <soc/uart.h> + +void bootblock_mainboard_early_init(void) +{ + if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + if (!uart_is_enabled(0)) + uart_setup(0, CONFIG_TTYS0_BAUD); + if (!uart_is_enabled(1)) + uart_setup(0, CONFIG_TTYS0_BAUD); + } +} + +static void configure_spi_flash(void) +{ + /* FIXME: Only tested on EM100 Pro */ + spi_init_custom(0, // bus + 25000000, // speed Hz + 0, // idle low disabled + 0, // zero idle cycles between transfers + 0, // MSB first + 0, // Chip select 0 + 1); // assert is high +} + +void bootblock_mainboard_init(void) +{ + configure_spi_flash(); +}

new file mode 100644

index 00000000000..d82b5ac05e3

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/cn81xx-linux.dtsi b/src/mainboard/cavium/cn8100_sff_evb/cn81xx-linux.dtsinew file mode 100644index 00000000000..d82b5ac05e3--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/cn81xx-linux.dtsi @@ -0,0 +1,496 @@ +/* + * Cavium Thunder DTS file - Thunder SoC description + * + * Copyright (C) 2016, Cavium Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/ { + model = "Cavium ThunderX CN81XX board"; + compatible = "cavium,thunder-81xx"; + interrupt-parent = <&gic0>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + /* socket 0 */ + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "psci"; + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "psci"; + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "cavium,thunder", "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "psci"; + numa-node-id = <0>; + next-level-cache = <&thunderx_L2_0>; + }; + }; + + thunderx_L2_0: l2-cache0 { + compatible = "cache"; + numa-node-id = <0>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, + <1 14 4>, + <1 11 4>, + <1 10 4>; + }; + + pmu { + compatible = "cavium,thunder-pmu", "arm,armv8-pmuv3"; + interrupts = <1 7 4>; + }; + + mmc_supply_3v3: mmc_supply_3v3 { + compatible = "regulator-fixed"; + regulator-name = "mmc_supply_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio_6_0 8 0>; + enable-active-high; + }; + + gic0: interrupt-controller@801000000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + #redistributor-regions = <1>; + ranges; + interrupt-controller; + reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */ + <0x8010 0x80000000 0x0 0x600000>; /* GICR */ + interrupts = <1 9 4>; + + its: gic-its@801000020000 { + compatible = "arm,gic-v3-its"; + reg = <0x8010 0x20000 0x0 0x200000>; + msi-controller; + numa-node-id = <0>; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + numa-node-id = <0>; + + refclkuaa: refclkuaa { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <116640000>; + clock-output-names = "refclkuaa"; + }; + + sclk: sclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sclk"; + }; + + uaa0: serial@87e028000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x28000000 0x0 0x1000>; + interrupts = <0 5 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + uaa1: serial@87e029000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x29000000 0x0 0x1000>; + interrupts = <0 6 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + uaa2: serial@87e02a000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x2a000000 0x0 0x1000>; + interrupts = <0 7 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + uaa3: serial@87e02b000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x87e0 0x2b000000 0x0 0x1000>; + interrupts = <0 8 4>; + clocks = <&refclkuaa>; + clock-names = "apb_pclk"; + skip-init; + }; + + watch-dog@8440000a0000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x8440 0xa0000 0x0 0x1000>, <0x8440 0xb0000 0x0 0x1000>; + interrupts = <0 9 4>; + }; + + pbus0: nor@0 { + compatible = "cfi-flash"; + reg = <0x8000 0x0 0x0 0x800000>; + device-width = <1>; + bank-width = <1>; + clocks = <&sclk>; + }; + + smmu0@830000000000 { + compatible = "cavium,smmu-v2"; + reg = <0x8300 0x0 0x0 0x2000000>; + #global-interrupts = <1>; + interrupts = <0 68 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, + <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>, <0 69 4>; + + mmu-masters = <&ecam0 0x100>, + <&pem0 0x200>, + <&pem1 0x300>, + <&pem2 0x400>; + + }; + + ecam0: pci@848000000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0 31>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + u-boot,dm-pre-reloc; + dma-coherent; + reg = <0x8480 0x00000000 0 0x02000000>; /* Configuration space */ + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x080 0x00000000>, /* mem ranges */ + <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>, /* SATA */ + <0x03000000 0x8680 0x00000000 0x8680 0x00000000 0x160 0x28000000>, /* UARTs */ + <0x03000000 0x87e0 0x2c000000 0x87e0 0x2c000000 0x000 0x94000000>, /* PEMs */ + <0x03000000 0x8400 0x00000000 0x8400 0x00000000 0x010 0x00000000>, /* RNM */ + <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x02 0x00000000>, /* NIC0*/ + <0x03000000 0x87e0 0xc6000000 0x87e0 0xc6000000 0x01f 0x3a000000>; + + mrml_bridge: mrml-bridge0@1,0 { + compatible = "pci-bridge", "cavium,thunder-8890-mrml-bridge"; + #size-cells = <2>; + #address-cells = <3>; + ranges = <0x03000000 0x87e0 0x00000000 0x03000000 0x87e0 0x00000000 0x10 0x00000000>; + reg = <0x0800 0 0 0 0>; /* DEVFN = 0x08 (1:0) */ + device_type = "pci"; + u-boot,dm-pre-reloc; + + mdio-nexus@1,3 { + compatible = "cavium,thunder-8890-mdio-nexus"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */ + assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>; + ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>; + mdio0@87e005003800 { + compatible = "cavium,thunder-8890-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x87e0 0x05003800 0x0 0x30>; + }; + mdio1@87e005003880 { + compatible = "cavium,thunder-8890-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x87e0 0x05003880 0x0 0x30>; + }; + }; + + mmc_1_4: mmc@1,4 { + compatible = "cavium,thunder-8890-mmc"; + reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sclk>; + }; + + i2c_9_0: i2c@9,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-twsi"; + reg = <0x4800 0 0 0 0>; /* DEVFN = 0x48 (9:0) */ + clock-frequency = <100000>; + clocks = <&sclk>; + u-boot,dm-pre-reloc; + }; + + i2c_9_1: i2c@9,1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-twsi"; + reg = <0x4900 0 0 0 0>; /* DEVFN = 0x49 (9:1) */ + clock-frequency = <100000>; + clocks = <&sclk>; + u-boot,dm-pre-reloc; + }; + + rgx0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-bgx"; + reg = <0x9000 0 0 0 0>; /* DEVFN = 0x90 (16:1) */ + }; + bgx0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-bgx"; + reg = <0x8000 0 0 0 0>; /* DEVFN = 0x80 (16:0) */ + }; + bgx1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8890-bgx"; + reg = <0x8100 0 0 0 0>; /* DEVFN = 0x81 (16:1) */ + }; + }; + + spi_7_0: spi@7,0 { + compatible = "cavium,thunder-8190-spi"; + reg = <0x3800 0x0 0x0 0x0 0x0>; /* DEVFN = 0x38 (7:0) */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sclk>; + }; + + gpio_6_0: gpio0@6,0 { + #gpio-cells = <2>; + compatible = "cavium,thunder-8890-gpio"; + gpio-controller; + reg = <0x3000 0 0 0 0>; /* DEVFN = 0x30 (6:0) */ + u-boot,dm-pre-reloc; + }; + + nfc: nand@b,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,cn8130-nand"; + reg = <0x5800 0 0 0 0>; /* DEVFN = 0x58 (b:0) */ + clocks = <&sclk>; + }; + }; + + pem0: pci@87e0c0000000 { + + /* "cavium,pci-host-thunder-pem" implies that + the first bus in bus-range has config access + via the "PEM space", subsequent buses have + config assess via the "Configuration space". + The "mem64 PEM" range is used to map the PEM + BAR0, which is used by the AER and PME MSI-X + sources. UEFI and Linux must assign the same + bus number to each device, otherwise Linux + enumeration gets confused. Because UEFI + skips the PEM bus and its PCIe-RC bridge it + uses a numbering that starts 1 bus higher. + */ + + compatible = "cavium,pci-host-thunder-pem"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0x1f 0x57>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + dma-coherent; + reg = <0x8800 0x1f000000 0x0 0x39000000>, /* Configuration space */ + <0x87e0 0xc0000000 0x0 0x01000000>; /* PEM space */ + ranges = <0x01000000 0x00 0x00000000 0x8830 0x00000000 0x00 0x00010000>, /* I/O */ + <0x03000000 0x00 0x10000000 0x8810 0x10000000 0x0f 0xf0000000>, /* mem64 */ + <0x43000000 0x10 0x00000000 0x8820 0x00000000 0x10 0x00000000>, /* mem64-pref */ + <0x03000000 0x87e0 0xc0000000 0x87e0 0xc0000000 0x00 0x01000000>; /* mem64 PEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic0 0 0 0 16 4>, /* INTA */ + <0 0 0 2 &gic0 0 0 0 17 4>, /* INTB */ + <0 0 0 3 &gic0 0 0 0 18 4>, /* INTC */ + <0 0 0 4 &gic0 0 0 0 19 4>; /* INTD */ + }; + + pem1: pci@87e0c1000000 { + compatible = "cavium,pci-host-thunder-pem"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0x57 0x8f>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + dma-coherent; + reg = <0x8840 0x57000000 0x0 0x39000000>, /* Configuration space */ + <0x87e0 0xc1000000 0x0 0x01000000>; /* PEM space */ + ranges = <0x01000000 0x00 0x00010000 0x8870 0x00010000 0x00 0x00010000>, /* I/O */ + <0x03000000 0x00 0x10000000 0x8850 0x10000000 0x0f 0xf0000000>, /* mem64 */ + <0x43000000 0x10 0x00000000 0x8860 0x00000000 0x10 0x00000000>, /* mem64-pref */ + <0x03000000 0x87e0 0xc1000000 0x87e0 0xc1000000 0x00 0x01000000>; /* mem64 PEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic0 0 0 0 20 4>, /* INTA */ + <0 0 0 2 &gic0 0 0 0 21 4>, /* INTB */ + <0 0 0 3 &gic0 0 0 0 22 4>, /* INTC */ + <0 0 0 4 &gic0 0 0 0 23 4>; /* INTD */ + }; + + pem2: pci@87e0c2000000 { + compatible = "cavium,pci-host-thunder-pem"; + device_type = "pci"; + msi-parent = <&its>; + msi-map = <0 &its 0 0x10000>; + bus-range = <0x8f 0xc7>; + #size-cells = <2>; + #address-cells = <3>; + #stream-id-cells = <1>; + dma-coherent; + reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */ + <0x87e0 0xc2000000 0x0 0x01000000>; /* PEM space */ + ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */ + <0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */ + <0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */ + <0x03000000 0x87e0 0xc2000000 0x87e0 0xc2000000 0x00 0x01000000>; /* mem64 PEM */ + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */ + <0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */ + <0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */ + <0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */ + }; + + tdm: tdm@d,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,thunder-8190-tdm"; + reg = <0x6800 0 0 0>; /* DEVFN = 0x68 (d:0) */ + clocks = <&sclk>; + }; + }; + + aliases { + serial0 = &uaa0; + serial1 = &uaa1; + serial2 = &uaa2; + serial3 = &uaa3; + i2c0 = &i2c_9_0; + i2c1 = &i2c_9_1; + spi0 = &spi_7_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + + memory@0 { + device_type = "memory"; + reg = <0x0 0x01400000 0x0 0x7EC00000>; + /* socket 0 */ + numa-node-id = <0>; + }; +};

new file mode 100644

index 00000000000..72ff6490147

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/ddr4-common.dtsi b/src/mainboard/cavium/cn8100_sff_evb/ddr4-common.dtsinew file mode 100644index 00000000000..72ff6490147--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/ddr4-common.dtsi @@ -0,0 +1,802 @@ +/***********************license start*********************************** +* Copyright (c) 2003-2016 Cavium Inc. (support@cavium.com). All rights +* reserved. +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are +* met: +* +* * Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* * Redistributions in binary form must reproduce the above +* copyright notice, this list of conditions and the following +* disclaimer in the documentation and/or other materials provided +* with the distribution. +* +* * Neither the name of Cavium Inc. nor the names of +* its contributors may be used to endorse or promote products +* derived from this software without specific prior written +* permission. +* +* This Software, including technical data, may be subject to U.S. export +* control laws, including the U.S. Export Administration Act and its +* associated regulations, and may be subject to export or import +* regulations in other countries. +* +* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" +* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR +* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT +* TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY +* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT +* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES +* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR +* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, +* QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK +* ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. +***********************license end**************************************/ +/ { +cavium,bdk { + /* Speed grade to use for DRAM in MT/s. Hardware may adjust this value + slightly to improve DRAM stability, so scope measurements may not + exactly match the frequency with MT/s. The Cavium supported speed + grades are: + 0 (auto-set from SPD contents) + 666 MT/s (DDR3 only) + 800 MT/s (DDR3 only) + 1066 MT/s (DDR3 only) + 1333 MT/s (DDR3 only) + 1600 MT/s + 1866 MT/s + 2133 MT/s (DDR4 only) + Parameters: + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-SPEED.N%d = "0"; + + /* Set to use a an alternate reference clock for DRAM than the usual + 50Mhz reference. The value of here specifies the frequency of the + alternate clock in Mhz. Currently the only supported reference + clock frequencies are 50Mhz and 100Mhz. + Parameters: + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-ALT-REFCLK.N%d = "0"; + + /* TWSI address of the DIMM SPD. The encoding of this address is + : [15:12]: TWSI bus the DIMM is connected to. + [11:7]: Reserved, set to zero. + [6:0]: TWSI address for the DIMM. + A value of zero means the DIMMs are not accessible. Hard coded + values will be read from DDR-CONFIG-SPD-DATA.Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-SPD-ADDR.DIMM%d.LMC%d.N%d = "0"; + // Note: The SPD addresses are not specified here so boards don't + // inherit a default. The default causes trouble with UEFI when it + // builds SMBIOS tables. + + /* DIMM SPD data to be used if memory doesn't support the standard + TWSI access to DIMM SPDs. The format of this is a binary blob + stored in the device tree. An example would be: + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-SPD-DATA.DIMM%d.LMC%d.N%d = []; + + /* Drive strength control for DDR_DQ* / DDR_DQS_*_P/N drivers. + 0x1 = 24 ohm. + 0x2 = 26.67 ohm. + 0x3 = 30 ohm. + 0x4 = 34.3 ohm. + 0x5 = 40 ohm. + 0x6 = 48 ohm. + 0x7 = 60 ohm. + _ else = Reserved. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-DQX-CTL.RANKS%d.DIMMS%d.LMC%d.N%d = "0"; + DDR-CONFIG-DQX-CTL = "0x4"; + + /* LMC Write OnDieTermination Mask Register + System designers may desire to terminate DQ/DQS lines for + higher-frequency DDR operations, especially on a multirank system. + DDR3 DQ/DQS I/Os have built-in termination resistors that can be + turned on or off by the controller, after meeting TAOND and TAOF + timing requirements. Each rank has its own ODT pin that fans out + to all of the memory parts in that DIMM. System designers may + prefer different combinations of ODT ONs for write operations into + different ranks. CNXXXX supports full programmability by way of + the mask register below. Each rank position has its own 8-bit + programmable field. When the controller does a write to that rank, + it sets the 4 ODT pins to the mask pins below. For example, when + doing a write into Rank0, a system designer may desire to terminate + the lines with the resistor on DIMM0/Rank1. The mask WODT_D0_R0 + would then be {00000010}. + CNXXXX drives the appropriate mask values on the ODT pins by + default. If this feature is not required, write 0x0 in this + register. When a given RANK is selected, the WODT mask for that + RANK is used. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-WODT-MASK.RANKS%d.DIMMS%d.LMC%d.N%d = "0"; + DDR-CONFIG-WODT-MASK.RANKS2.DIMMS2 = "0xc0c0303"; + DDR-CONFIG-WODT-MASK.RANKS4.DIMMS1 = "0x1030203"; + + /* Partial array self-refresh per rank. LMC writes this value to + MR2[PASR] in the rank (i.e. DIMM0_CS0) DDR3 parts when selected + during power-up/init, write-leveling, and, if + LMC()_CONFIG[SREF_WITH_DLL] is set, self-refresh entry and exit + instruction sequences. See LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and + LMC()_CONFIG[RANKMASK] and LMC()_RESET_CTL[DDR3PWARM,DDR3PSOFT]. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE1-PASR.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + + /* Auto self-refresh per rank. LMC writes this value to MR2[ASR] in + the rank (i.e. DIMM0_CS0) DDR3 parts when selected during + power-up/init, write-leveling, and, if LMC()_CONFIG[SREF_WITH_DLL] + is set, self-refresh entry and exit instruction sequences. See + LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and LMC()_CONFIG[RANKMASK] and + LMC()_RESET_CTL [DDR3PWARM,DDR3PSOFT]. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE1-ASR.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + + /* Self-refresh temperature range per rank. LMC writes this value to + MR2[SRT] in the rank (i.e. DIMM0_CS0) DDR3 parts when selected + during power-up/init, write-leveling, and, if + LMC()_CONFIG[SREF_WITH_DLL] is set, self-refresh entry and exit + instruction sequences. See LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and + LMC()_CONFIG[RANKMASK] and LMC()_RESET_CTL[DDR3PWARM,DDR3PSOFT]. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE1-SRT.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + + /* RTT_WR per rank. LMC writes this value to MR2[RTT_WR] in the rank + (i.e. DIMM0_CS0) DDR3 parts when selected during power-up/init, + write-leveling, and, if LMC()_CONFIG[SREF_WITH_DLL] is set, + self-refresh entry and exit instruction sequences. See + LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and LMC()_CONFIG[RANKMASK] and + LMC()_RESET_CTL[DDR3PWARM, DDR3PSOFT]. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE1-RTT-WR.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + + //DDR-CONFIG-MODE1-RTT-WR.RANKS1 = "0x4"; + DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS1.RANK0 = "0x4"; + DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK0 = "0x4"; + DDR-CONFIG-MODE1-RTT-WR.RANKS1.DIMMS2.RANK2 = "0x4"; + + //DDR-CONFIG-MODE1-RTT-WR.RANKS2 = "0x2"; + DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK0 = "0x2"; + DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS1.RANK1 = "0x2"; + DDR-CONFIG-MODE1-RTT-WR.RANKS2.DIMMS2 = "0x2"; + + DDR-CONFIG-MODE1-RTT-WR.RANKS4 = "0x1"; + + /* Output driver impedance control per rank. LMC writes this value + to MR1[D.I.C.] in the rank (i.e. DIMM0_CS0) DDR3 parts when + selected during power-up/init, write-leveling, and, if + LMC()_CONFIG[SREF_WITH_DLL] is set, self-refresh entry and exit + instruction sequences. See LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and + LMC()_CONFIG[RANKMASK] and LMC()_RESET_CTL[DDR3PWARM,DDR3PSOFT]. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE1-DIC.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + DDR-CONFIG-MODE1-DIC.RANKS4.DIMMS1 = "0x1"; + + /* RTT_NOM per rank. LMC writes this value to MR1[RTT_NOM] in the + rank (i.e. DIMM0_CS0) DDR3 parts when selected during + power-up/init, write-leveling, and, if LMC()_CONFIG[SREF_WITH_DLL] + is set, self-refresh entry and exit instruction sequences. See + LMC()_SEQ_CTL[SEQ_SEL,INIT_START] and LMC()_CONFIG[RANKMASK] and + LMC()_RESET_CTL[DDR3PWARM, DDR3PSOFT]. Per JEDEC DDR3 + specifications, if RTT_NOM is used during write operations, only + values MR1[RTT_NOM] = 1 (RZQ/4), 2 (RZQ/2), or 3 (RZQ/6) are + allowed. Otherwise, values MR1[RTT_NOM] = 4 (RZQ/12) and 5 (RZQ/8) + are also allowed. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE1-RTT-NOM.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + DDR-CONFIG-MODE1-RTT-NOM.RANKS2.DIMMS2 = "0x2"; + DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK0 = "0x4"; + DDR-CONFIG-MODE1-RTT-NOM.RANKS4.DIMMS1.RANK2 = "0x4"; + + /* Host Interface DQ/DQS Output Driver Impedance control for DIMM0's + Data Buffer. This is the default value used during Host Interface + Write Leveling in LRDIMM environment, i.e., + LMC()_CONFIG[LRDIMM_ENA] = 1, LMC()_SEQ_CTL[SEQ_SEL] = 0x6. + 0x0 = RZQ/6 (40 ohm). + 0x1 = RZQ/7 (34 ohm). + 0x2 = RZQ/5 (48 ohm). + 0x3-0x7 = Reserved. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE1-DB-OUTPUT-IMPEDANCE.RANKS%d.DIMMS%d.LMC%d.N%d = "0"; + + /* RTT park value per rank. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE2-RTT-PARK.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + + //DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1 = "0x1"; + DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS1.RANK0 = "0x1"; + + //DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2 = "0x5"; + DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK0 = "0x5"; + DDR-CONFIG-MODE2-RTT-PARK.RANKS1.DIMMS2.RANK2 = "0x5"; + + //DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1 = "0x2"; + DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK0 = "0x2"; + DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS1.RANK1 = "0x2"; + + DDR-CONFIG-MODE2-RTT-PARK.RANKS2.DIMMS2 = "0x1"; + DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK0 = "0x6"; + DDR-CONFIG-MODE2-RTT-PARK.RANKS4.DIMMS1.RANK1 = "0x6"; + + /* VREF value per rank. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE2-VREF-VALUE.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + + //DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1 = "0x22"; + DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS1.RANK0 = "0x22"; + + //DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2 = "0x1f"; + DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK0 = "0x1f"; + DDR-CONFIG-MODE2-VREF-VALUE.RANKS1.DIMMS2.RANK2 = "0x1f"; + + //DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1 = "0x19"; + DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK0 = "0x19"; + DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS1.RANK1 = "0x19"; + + DDR-CONFIG-MODE2-VREF-VALUE.RANKS2.DIMMS2 = "0x19"; + DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK0 = "0x1f"; + DDR-CONFIG-MODE2-VREF-VALUE.RANKS4.DIMMS1.RANK1 = "0x1f"; + + /* VREF range per rank. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + RANK#: Parameter can be different for each rank of a DIMM. This + specifies which rank the value is for. Rank must be + 0-3. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE2-VREF-RANGE.RANKS%d.DIMMS%d.RANK%d.LMC%d.N%d = "0"; + + /* Vref training mode enable, used for all ranks. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-MODE2-VREFDQ-TRAIN-EN.RANKS%d.DIMMS%d.LMC%d.N%d = "0"; + + /* RODT NCTL impedance control bits. This field controls ODT values + during a memory read. + 0x0 = No ODT. + 0x1 = 20 ohm. + 0x2 = 30 ohm. + 0x3 = 40 ohm. + 0x4 = 60 ohm. + 0x5 = 120 ohm. + _ else = Reserved. + In DDR4 mode: + 0x0 = No ODT. + 0x1 = 40 ohm. + 0x2 = 60 ohm. + 0x3 = 80 ohm. + 0x4 = 120 ohm. + 0x5 = 240 ohm. + 0x6 = 34 ohm. + 0x7 = 48 ohm. + _ else = Reserved. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-RODT-CTL.RANKS%d.DIMMS%d.LMC%d.N%d = "0"; + DDR-CONFIG-RODT-CTL.RANKS1.DIMMS1 = "0x7"; + DDR-CONFIG-RODT-CTL.RANKS1.DIMMS2 = "0x3"; + DDR-CONFIG-RODT-CTL.RANKS2.DIMMS1 = "0x3"; + DDR-CONFIG-RODT-CTL.RANKS2.DIMMS2 = "0x7"; + DDR-CONFIG-RODT-CTL.RANKS4.DIMMS1 = "0x7"; + + /* LMC Read OnDieTermination Mask Register + System designers may desire to terminate DQ/DQS lines for higher + frequency DDR operations, especially on a multirank system. DDR3 + DQ/DQS I/Os have built-in termination resistors that can be turned + on or off by the controller, after meeting TAOND and TAOF timing + requirements. + Each rank has its own ODT pin that fans out to all the memory + parts in that DIMM. System designers may prefer different + combinations of ODT ONs for read operations into different ranks. + CNXXXX supports full programmability by way of the mask register + below. Each rank position has its own 4-bit programmable field. + When the controller does a read to that rank, it sets the 4 ODT + pins to the MASK pins below. For example, when doing a read from + Rank0, a system designer may desire to terminate the lines with + the resistor on DIMM0/Rank1. The mask RODT_D0_R0 would then be {0010}. + CNXXXX drives the appropriate mask values on the ODT pins by + default. If this feature is not required, write 0x0 in this + register. Note that, as per the JEDEC DDR3 specifications, the ODT + pin for the rank that is being read should always be 0x0. When a + given RANK is selected, the RODT mask for that rank is used. + Parameters: + RANKS#: Specifies that this parameter only applies to DIMMs + with the supplied number of ranks. Support ranks is 1, 2, + or 4. Optional. + DIMMS#: Specifies that this parameter only applies when the + DIMMs per memory controller matches. Support number of + DIMMs is 1 or 2. Optional. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-RODT-MASK.RANKS%d.DIMMS%d.LMC%d.N%d = "0"; + DDR-CONFIG-RODT-MASK.RANKS2.DIMMS2 = "0x4080102"; + DDR-CONFIG-RODT-MASK.RANKS4.DIMMS1 = "0x1010202"; + + /* 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX.LMC%d.N%d = "1"; + DDR-CONFIG-CUSTOM-MIN-RTT-NOM-IDX = "0x1"; + + /* 1=120ohms, 2=60ohms, 3=40ohms, 4=30ohms, 5=20ohms + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX.LMC%d.N%d = "5"; + DDR-CONFIG-CUSTOM-MAX-RTT-NOM-IDX = "0x7"; + + /* 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MIN-RODT-CTL.LMC%d.N%d = "1"; + DDR-CONFIG-CUSTOM-MIN-RODT-CTL = "0x1"; + + /* 1=20ohms, 2=30ohms, 3=40ohms, 4=60ohms, 5=120ohms + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MAX-RODT-CTL.LMC%d.N%d = "5"; + DDR-CONFIG-CUSTOM-MAX-RODT-CTL = "0x7"; + + /* Drive strength control for DDR_CK_X_P, DDR_DIMMX_CSX_L, + DDR_DIMMX_ODT_X drivers. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-CK-CTL.LMC%d.N%d = "0"; + DDR-CONFIG-CUSTOM-CK-CTL = "0x4"; + + /* Drive strength control for CMD/A/RESET_L/CKEX drivers. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-CMD-CTL.LMC%d.N%d = "0"; + DDR-CONFIG-CUSTOM-CMD-CTL = "0x4"; + + /* Drive strength control for ODT, etc. drivers. + In DDR3 mode: + 0x1 = 24 ohm. + 0x2 = 26.67 ohm. + 0x3 = 30 ohm. + 0x4 = 34.3 ohm. + 0x5 = 40 ohm. + 0x6 = 48 ohm. + 0x7 = 60 ohm. + else = Reserved. + In DDR4 mode: + 0x0 = Reserved. + 0x1 = Reserved. + 0x2 = 26 ohm. + 0x3 = 30 ohm. + 0x4 = 34 ohm. + 0x5 = 40 ohm. + 0x6 = 48 ohm. + else = Reserved. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-CTL-CTL.LMC%d.N%d = "0"; + DDR-CONFIG-CUSTOM-CTL-CTL = "0x4"; + + /* Minimum allowed CAS Latency + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MIN-CAS-LATENCY.LMC%d.N%d = "0"; + + /* When set, LMC attempts to select the read-leveling setting that is + LMC()_RLEVEL_CTL[OFFSET] settings earlier than the last passing + read-leveling setting in the largest contiguous sequence of + passing settings. When clear, or if the setting selected by + LMC()_RLEVEL_CTL[OFFSET] did not pass, LMC selects the middle + setting in the largest contiguous sequence of passing settings, + rounding earlier when necessary. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-OFFSET-EN.LMC%d.N%d = "1"; + DDR-CONFIG-CUSTOM-OFFSET-EN = "0x1"; + + /* The offset used when LMC()_RLEVEL_CTL[OFFSET] is set. + Parameters: + %s: This setting can by specified by DRAM type (UDIMM or RDIMM) + Different settings can be used for each, or the type can be + omitted to use the same setting for both. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-OFFSET.%s.LMC%d.N%d = "0"; + DDR-CONFIG-CUSTOM-OFFSET = "0x2"; + + /* Enables software interpretation of per-byte read delays using the + measurements collected by the chip rather than completely relying + on the automatically to determine the delays. 1=software + computation is recommended since a more complete analysis is + implemented in software. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-RLEVEL-COMPUTE.LMC%d.N%d = "0"; + + /* Set to 2 unless instructed differently by Cavium. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-RLEVEL-COMP-OFFSET.%s.LMC%d.N%d = "2"; + + /* Turn on the DDR 2T mode. 2-cycle window for CMD and address. This + mode helps relieve setup time pressure on the address and command + bus. Please refer to Micron's tech note tn_47_01 titled DDR2-533 + Memory Design Guide for Two DIMM Unbuffered Systems for physical + details. + Parameters: + %s: This setting can by specified by DRAM type (UDIMM or RDIMM) + Different settings can be used for each, or the type can be + omitted to use the same setting for both. + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-DDR2T.%s.LMC%d.N%d = "0"; + DDR-CONFIG-CUSTOM-DDR2T = "0x1"; + + /* As result of the flyby topology prescribed in the JEDEC + specifications the byte delays should maintain a consistent + increasing or decreasing trend across the bytes on standard DIMMs. + This setting can be used disable that check for unusual + circumstances where the check is not useful. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-DISABLE-SEQUENTIAL-DELAY-CHECK.LMC%d.N%d = "0"; + + /* An additional sequential delay check for the delays that result + from the flyby topology. This value specifies the maximum + difference between the delays of adjacent bytes. A value of 0 + disables this check. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT.LMC%d.N%d = "0"; + DDR-CONFIG-CUSTOM-MAXIMUM-ADJACENT-RLEVEL-DELAY-INCREMENT = "0x2"; + + /* The parity input signal PAR_IN on each DIMM must be strapped high + or low on the board. This bit is programmed into + LMC0_DIMM_CTL[PARITY] and it must be set to match the board + strapping. This signal is typically strapped low. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-PARITY.LMC%d.N%d = "0"; + + /* Front Porch Enable: When set, the turn-off time for the default + DDR_DQ/DQS drivers is FPRCH2 CKs earlier. + 0 = 0 CKs + 1 = 1 CKs + 2 = 2 CKs + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-FPRCH2.LMC%d.N%d = "0"; + DDR-CONFIG-CUSTOM-FPRCH2 = "0x2"; + + /* Enable 32-bit datapath mode. Set to 1 if only 32 DQ pins are + used. + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MODE32B.LMC%d.N%d = "0"; + + /* Use Measured VREF + Parameters: + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-MEASURED-VREF.LMC%d.N%d = "0"; + + /* Supply a custom DLL write offset + Parameters: + BYTE#: Byte lane to apply the parameter to (0-8). + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-DLL-WRITE-OFFSET.BYTE%d.LMC%d.N%d = "0"; + + /* Supply a custom DLL read offset + Parameters: + BYTE#: Byte lane to apply the parameter to (0-8). + LMC#: Parameter can be different for memory controller. This + specifies which LMC the value is for. LMC must be + 0-3. Optional. + N#: Parameter can be different for each node. This specifies + which node the value is for. Node must be 0-3. Optional. */ + //DDR-CONFIG-CUSTOM-DLL-READ-OFFSET.BYTE%d.LMC%d.N%d = "0"; + + /* Choose the debug logging level used during DRAM initialization. + Zero disables debug logging. The possible debug levels are: + 0: Off, no logging + 1: Logging of DRAM initialization at a normal detail level + 2: Logging of DRAM initialization at FAE detail level + 3: Logging of DRAM initialization at TME detail level + 4: Logging of DRAM initialization at DEV detail level + 5: Logging of DRAM initialization at DEV2 detail level + 6: Logging of DRAM initialization at DEV3 detail level + 7: Logging of DRAM initialization at DEV4 detail level + Add in the following for special trace features. + 16: Trace specialized DRAM controller sequences. + 32: Trace every DRAM controller register write. */ + //DDR-VERBOSE = "0"; + + /* Run a short DRAM test after DRAM is initialized as quick check + for functionality. This is normally not needed required. Boards + with poor DRAM power supplies may use this to detect failures + during boot. This should be used in combination with the watchdog + timer. */ + //DDR-TEST-BOOT = "0"; + + /* The DRAM initialization code has the ability to toggle a GPIO to + signal when it is running. Boards may need to mux TWSI access + between a BMC and the SOC so the BMC can monitor DIMM temperatures + and health. This GPIO will be driven high when the SOC may read + from the SPDs on the DIMMs. When driven low, another device (BMC) + may takeover the TWSI connections to the DIMMS. The default value + (-1) disables this feature. */ + //DDR-CONFIG-GPIO = "-1"; + + /* Scramble DRAM to prevent snooping. This options programs the DRAM + controller to scramble addresses and data with random values. + Supported values: + 0: No scrambling + 1: Always scramble + 2: Scramble only when using trusted boot (Default) */ + //DDR-CONFIG-SCRAMBLE = "2"; +}; /* cavium,bdk */ +}; /* / */

new file mode 100644

index 00000000000..cd495e1f544

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cbnew file mode 100644index 00000000000..cd495e1f544--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/devicetree.cb @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/cavium/cn81xx + device cpu_cluster 0 on end +end

new file mode 100644

index 00000000000..b6d4ad8a7c2

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.cnew file mode 100644index 00000000000..b6d4ad8a7c2--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-2018 Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. (support@cavium.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. + */ + +#include <device/device.h> +#include <libbdk-hal/bdk-config.h> +#include <libbdk-hal/bdk-twsi.h> +#include <soc/twsi.h> +#include <soc/gpio.h> +#include <delay.h> + +extern const struct bdk_devicetree_key_value devtree[]; + +static void mainboard_init(struct device *dev) +{ + /* FIXME: stub */ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; + + bdk_config_set_fdt(devtree); + + /* + * Adapted from Cavium's devicetree TWSI-WRITE: + * Init board-specific I2C hardware: + */ + twsi_init(0, I2C_SPEED_STANDARD); + + /* Initialize IO expander U6 to power-up defaults */ + /* float all pins 0.0-0.7 */ + bdk_twsix_write_ia(0,0,0x21,6,1,1,0xff); + /* float all pins 1.0-1.7 */ + bdk_twsix_write_ia(0,0,0x21,7,1,1,0xff); + /* 0.x: all outputs low, but disabled */ + bdk_twsix_write_ia(0,0,0x21,2,1,1,0x00); + /* 1.x: all outputs low, but disabled */ + bdk_twsix_write_ia(0,0,0x21,3,1,1,0x00); + /* 0.x: no polarity inversion */ + bdk_twsix_write_ia(0,0,0x21,4,1,1,0x00); + /* 1.x: no polarity inversion */ + bdk_twsix_write_ia(0,0,0x21,5,1,1,0x00); + /* Initialize IO expander U89 to power-up defaults */ + /* float all pins 0.0-0.7 */ + bdk_twsix_write_ia(0,0,0x22,6,1,1,0xff); + /* float all pins 1.0-1.7 */ + bdk_twsix_write_ia(0,0,0x22,7,1,1,0xff); + /* 0.x: all outputs low, but disabled */ + bdk_twsix_write_ia(0,0,0x22,2,1,1,0x00); + /* 1.x: all outputs low, but disabled */ + bdk_twsix_write_ia(0,0,0x22,3,1,1,0x00); + /* 0.x: no polarity inversion */ + bdk_twsix_write_ia(0,0,0x22,4,1,1,0x00); + /* 1.x: no polarity inversion */ + bdk_twsix_write_ia(0,0,0x22,5,1,1,0x00); + /* set outputs SLIC_RESET_L=0 and SPI_SEL=0 */ + bdk_twsix_write_ia(0,0,0x21,6,1,1,0xee); /* 0.0 & 0.4 are outputs */ + + /* Select channel-0 in PCA9546A to enable SFI */ + bdk_twsix_write_ia(0, 0, 0x70, 0, 1, 1, 0x7); + mdelay(10); + /* Configure I2C-GPIO expander I/O directions */ + bdk_twsix_write_ia(0, 0, 0x22, 6, 1, 1, 0x07); + mdelay(10); + /* Configure I2C-GPIO expander I/O directions */ + bdk_twsix_write_ia(0, 0, 0x22, 7, 1, 1, 0x38); + mdelay(10); + /* Turn on SFP+ Transmitters */ + bdk_twsix_write_ia(0, 0, 0x22, 2, 1, 1, 0x0); + mdelay(10); + /* Set VSC7224 to I2C mode */ + bdk_twsix_write_ia(0, 0, 0x22, 3, 1, 1, 0x0); + mdelay(10); + /* Assert VSC7224 reset*/ + bdk_twsix_write_ia(0, 0, 0x22, 2, 1, 1, 0x80); + mdelay(50); + /* Deassert VSC7224 reset*/ + bdk_twsix_write_ia(0, 0, 0x22, 2, 1, 1, 0x0); + mdelay(50); + /* Page select FSYNC0 (0x30) */ + bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0030); + mdelay(10); + /* Set FSYNC0 for 10.3125Gbps See Table 3 */ + bdk_twsix_write_ia(0, 0, 0x14, 0x80, 2, 1, 0x2841); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x81, 2, 1, 0x0008); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x82, 2, 1, 0x7a00); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x83, 2, 1, 0x000f); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x84, 2, 1, 0x9c18); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x85, 2, 1, 0x0); + mdelay(10); + + /* All channels Rx settings set equally */ + bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0050); + mdelay(10); + /* Shrink EQ_BUFF */ + bdk_twsix_write_ia(0, 0, 0x14, 0x82, 2, 1, 0x0014); + mdelay(10); + /* Select min DFE Delay (DFE_DELAY) */ + bdk_twsix_write_ia(0, 0, 0x14, 0x90, 2, 1, 0x5585); + mdelay(10); + /* Set DFE 1-3 limit (DXMAX) = 32dec, AP Max limit = 127 decimal */ + bdk_twsix_write_ia(0, 0, 0x14, 0x92, 2, 1, 0x207f); + mdelay(10); + /* Set AP Min limit = 32 decimal */ + bdk_twsix_write_ia(0, 0, 0x14, 0x93, 2, 1, 0x2000); + mdelay(10); + /* Set DFE Averaging to the slowest (DFE_AVG) */ + bdk_twsix_write_ia(0, 0, 0x14, 0x94, 2, 1, 0x0031); + mdelay(10); + /* Set Inductor Bypass OD_IND_BYP = 0 & fastest Rise/Fall */ + bdk_twsix_write_ia(0, 0, 0x14, 0x9c, 2, 1, 0x0000); + mdelay(10); + /* Setting DFE Boost = none. Must set for rev C + * (if DFE in adapt mode) */ + bdk_twsix_write_ia(0, 0, 0x14, 0xaa, 2, 1, 0x0888); + mdelay(10); + /* Setting EQ Min/Max = 8/72 */ + bdk_twsix_write_ia(0, 0, 0x14, 0xa8, 2, 1, 0x2408); + mdelay(10); + /* Setting EQVGA = 96, when in EQVGA manual mode */ + bdk_twsix_write_ia(0, 0, 0x14, 0xa9, 2, 1, 0x0060); + mdelay(10); + /* Setting SW_BFOCM, bits 15:14 to 01 */ + bdk_twsix_write_ia(0, 0, 0x14, 0x87, 2, 1, 0x4021); + mdelay(10); + /* Turn off adaptive input equalization and VGA adaptive algorithm + * control */ + bdk_twsix_write_ia(0, 0, 0x14, 0x89, 2, 1, 0x7313); + mdelay(10); + /* Turn on adaptive input equalization and VGA adaptive algorithm + * control */ + bdk_twsix_write_ia(0, 0, 0x14, 0x89, 2, 1, 0x7f13); + mdelay(10); + + /* TAP settings for each channel 0-3 */ + /* Ch-0 Tx */ + bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0000); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x001f); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x9a, 2, 1, 0x000f); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x9b, 2, 1, 0x0004); + mdelay(10); + + /* Ch-1 Rx */ + bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0001); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x1400); + mdelay(10); + /* Transmitter Output polarity Inverted (Unfortunately, + * Rx polarity lines are wrongly inverted on board */ + bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x4000); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x000f); + mdelay(10); + + /* Ch-2 Tx */ + bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0002); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x001f); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x9a, 2, 1, 0x000f); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x9b, 2, 1, 0x0004); + mdelay(10); + + /* Ch-3 Rx */ + bdk_twsix_write_ia(0, 0, 0x14, 0x7f, 2, 1, 0x0003); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x1400); + mdelay(10); + /* Transmitter Output polarity Inverted (Unfortunately, + * Rx polarity lines are wrongly inverted on board */ + bdk_twsix_write_ia(0, 0, 0x14, 0x97, 2, 1, 0x4000); + mdelay(10); + bdk_twsix_write_ia(0, 0, 0x14, 0x99, 2, 1, 0x000f); + mdelay(10); + + /** + * The following hardware magically starts working after toggling + * GPIO_10_PHY_RESET_L: + * * SATA PHY + * * GBE PHY + * * XFI PHY + * * MMC + */ + gpio_output(10, 0); + udelay(100); + gpio_output(10, 1); +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +};

new file mode 100644

index 00000000000..9349362cfa9

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/memlayout.ld b/src/mainboard/cavium/cn8100_sff_evb/memlayout.ldnew file mode 100644index 00000000000..9349362cfa9--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/memlayout.ld @@ -0,0 +1 @@ + #include <soc/memlayout.ld>

new file mode 100644

index 00000000000..c35d0b38768

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/romstage.c b/src/mainboard/cavium/cn8100_sff_evb/romstage.cnew file mode 100644index 00000000000..c35d0b38768--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/romstage.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/exception.h> +#include <cbmem.h> +#include <romstage_handoff.h> +#include <soc/sdram.h> +#include <soc/timer.h> +#include <stdlib.h> +#include <console/console.h> +#include <program_loading.h> +#include <libbdk-hal/bdk-config.h> +#include <string.h> + +extern const struct bdk_devicetree_key_value devtree[]; + +void main(void) +{ + watchdog_poke(0); + + console_init(); + exception_init(); + + bdk_config_set_fdt(devtree); + + sdram_init(); + + watchdog_poke(0); + + cbmem_initialize_empty(); + run_ramstage(); +}

new file mode 100644

index 00000000000..1448ee62209

--- /dev/null

+++ b/ diff --git a/src/mainboard/cavium/cn8100_sff_evb/sff8104-linux.dts b/src/mainboard/cavium/cn8100_sff_evb/sff8104-linux.dtsnew file mode 100644index 00000000000..1448ee62209--- /dev/null+++ b/ src/mainboard/cavium/cn8100_sff_evb/sff8104-linux.dts @@ -0,0 +1,282 @@ +/* + * Cavium Thunder DTS file - Thunder board description + * + * Copyright (C) 2016, Cavium Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +/include/ "cn81xx-linux.dtsi" + +&mrml_bridge { + mdio-nexus@1,3 { + mdio0@87e005003800 { + rgmii00: rgmii00 { + reg = <0> ; + compatible = "marvell,88e1510", "ethernet-phy-ieee802.3-c22"; + }; + + qsgmii00: qsgmii00 { + qlm-mode = "0x000,qsgmii"; + reg = <0x10> ; + compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; + }; + qsgmii01: qsgmii01 { + qlm-mode = "0x001,qsgmii"; + reg = <0x11> ; + compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; + }; + qsgmii02: qsgmii02 { + qlm-mode = "0x002,qsgmii"; + reg = <0x12> ; + compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; + }; + qsgmii03: qsgmii03 { + qlm-mode = "0x003,qsgmii"; + reg = <0x13> ; + compatible = "vitesse,vsc8574", "ethernet-phy-ieee802.3-c22"; + }; + }; + mdio1@87e005003880 { + xfi00: xfi00 { + qlm-mode = "0x000,xfi"; + reg = <0x0>; + compatible = "aquantia,aqr105", "ethernet-phy-ieee802.3-c45"; + }; + }; + }; + + rgx0 { + rgmii00 { + reg = <0>; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&rgmii00>; + }; + }; + + bgx0 { + /* typename+qlm+typenumber eg : + qsgmii+bgx0+sgmmi0 + */ + qsgmii00 { + reg = <0>; + qlm-mode = "0x000,qsgmii"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&qsgmii00>; + }; + qsgmii01 { + reg = <1>; + qlm-mode = "0x001,qsgmii"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&qsgmii01>; + }; + qsgmii02 { + reg = <2>; + qlm-mode = "0x002,qsgmii"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&qsgmii02>; + }; + qsgmii03 { + reg = <3>; + qlm-mode = "0x003,qsgmii"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&qsgmii03>; + }; + + xfi00 { + reg = <0>; + qlm-mode = "0x000,xfi"; + local-mac-address = [00 00 00 00 00 00]; + phy-handle = <&xfi00>; + }; + }; + + bgx1 { + xfi10 { + reg = <0>; + qlm-mode = "0x010,xfi"; + local-mac-address = [00 00 00 00 00 00]; + }; + + xfi11 { + reg = <1>; + qlm-mode = "0x011,xfi"; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + + +}; + +&mmc_1_4 { + /* NOTE: the BDK is responsible for swapping the two slots. + * Unfortunately there does not appear to be any way to read the + * position of SW2-7 in software. + */ + mmc-slot@0 { + compatible = "mmc-slot"; + reg = <0>; + vmmc-supply = <&mmc_supply_3v3>; + max-frequency = <26000000>; + /* 1.8v is not supported */ + no-1-8-v; + /* Bus width is only 4 bits maximum */ + bus-width = <4>; + /* No write-protect switch is present */ + disable-wp; + /* There is no card detection available; polling must be used. */ + broken-cd; + /* High-speed mode is supported */ + cap-sd-highspeed; + /* speed up device probing */ + no-sdio; + no-mmc; + }; + mmc-slot@1 { + compatible = "mmc-slot"; + reg = <1>; + vmmc-supply = <&mmc_supply_3v3>; + max-frequency = <26000000>; + mmc-ddr-3_3v; + /* 1.8v is not supported */ + no-1-8-v; + /* Bus width is only 8 bits maximum */ + bus-width = <8>; + /* No write-protect switch is present */ + disable-wp; + /* There is no card detection available; polling must be used. */ + broken-cd; + /* High-speed mode is supported */ + cap-mmc-highspeed; + /* eMMC device is soldered onto the board */ + non-removable; + /* speed up device probing */ + no-sdio; + no-sd; + }; +}; + +&i2c_9_0 { + /* another pca9535 at 0x20 is only visible via jtag */ + gpio1: gpio-i2c@21 { + compatible = "nxp,pca9535"; + gpio-controller; + reg = <0x21>; + gpio_base = <48>; + pins = <48 16>; + ngpios = <16>; // standard + n_gpios = <16>; // deprecated, driver required + #gpio-cells = <2>; + }; + + gpio2: gpio-i2c@22 { + compatible = "nxp,pca9535"; + gpio-controller; + reg = <0x22>; + gpio_base = <64>; + pins = <64 16>; + ngpios = <16>; // standard + n_gpios = <16>; // deprecated, driver required + #gpio-cells = <2>; + }; + + mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; +}; + +&i2c_9_1 { + rom@54 { + compatible = "atmel,24c256"; + reg = <0x54>; + pagesize = <64>; + }; + + rtc@68 { + compatible = "isil,isl12057"; + reg = <0x68>; + }; +}; + +&spi_7_0 { + flash@0 { + compatible = "micron,n25q128a13", "spi-flash", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <16000000>; + #address-cells = <1>; + #size-cells = <1>; + }; + flash@1 { + compatible = "spinand,mt29f", "mt29f"; + reg = <0x1>; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-mode = "none"; + }; +}; + +&nfc { + nand@1 { + reg = <0x1>; + nand-ecc-mode = "none"; + }; +};

new file mode 100644

index 00000000000..49070cfbf20

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/Kconfig b/src/soc/cavium/Kconfignew file mode 100644index 00000000000..49070cfbf20--- /dev/null+++ b/ src/soc/cavium/Kconfig @@ -0,0 +1,2 @@ +# Load all chipsets +source "src/soc/cavium/*/Kconfig"

new file mode 100644

index 00000000000..ca8fbd0f46b

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfignew file mode 100644index 00000000000..ca8fbd0f46b--- /dev/null+++ b/ src/soc/cavium/cn81xx/Kconfig @@ -0,0 +1,27 @@ +config SOC_CAVIUM_CN81XX + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select BOOTBLOCK_CONSOLE + select DRIVERS_UART_PL011 + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select UART_OVERRIDE_REFCLK + select SOC_CAVIUM_COMMON + +if SOC_CAVIUM_CN81XX + +config ARCH_ARMV8_EXTENSION + int + default 1 + +config HEAP_SIZE + default 0x10000 + +config STACK_SIZE + default 0x2000 + +endif

new file mode 100644

index 00000000000..d265c19bb82

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/Makefile.inc b/src/soc/cavium/cn81xx/Makefile.incnew file mode 100644index 00000000000..d265c19bb82--- /dev/null+++ b/ src/soc/cavium/cn81xx/Makefile.inc @@ -0,0 +1,70 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2017-present Facebook, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ifeq ($(CONFIG_SOC_CAVIUM_CN81XX),y) + +# bootblock +bootblock-$(CONFIG_BOOTBLOCK_CUSTOM) += bootblock_custom.S +bootblock-y += bootblock.c +bootblock-y += twsi.c +bootblock-y += clock.c +bootblock-y += gpio.c +bootblock-y += timer.c +bootblock-y += spi.c +bootblock-y += uart.c +bootblock-y += cpu.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_DRIVERS_UART) += uart.c +endif + +################################################################################ +# romstage + +romstage-y += twsi.c +romstage-y += clock.c +romstage-y += gpio.c +romstage-y += timer.c +romstage-y += spi.c +romstage-y += uart.c +romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-< += cpu.c + +romstage-y += sdram.c +romstage-y += ../common/cbmem.c +# BDK coreboot interface +romstage-y += ../common/bdk-coreboot.c + + +################################################################################ +# ramstage + +ramstage-y += twsi.c +ramstage-y += clock.c +ramstage-y += gpio.c +ramstage-y += timer.c +ramstage-y += spi.c +ramstage-y += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c +ramstage-y += sdram.c +ramstage-y += soc.c +ramstage-y += cpu.c + +# BDK coreboot interface +ramstage-y += ../common/bdk-coreboot.c + + +CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include + +endif

new file mode 100644

index 00000000000..8517467de13

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/bootblock.c b/src/soc/cavium/cn81xx/bootblock.cnew file mode 100644index 00000000000..8517467de13--- /dev/null+++ b/ src/soc/cavium/cn81xx/bootblock.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. <support@cavium.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <soc/bootblock.h> +#include <soc/sysreg.h> +#include <soc/timer.h> +#include <libbdk-arch/bdk-asm.h> + +static void init_sysreg(void) +{ + /* The defaults for write buffer timeouts are poor */ + u64 cvmmemctl0; + BDK_MRS(s3_0_c11_c0_4, cvmmemctl0); + cvmmemctl0 |= AP_CVMMEMCTL0_EL1_WBFTONSHENA | + AP_CVMMEMCTL0_EL1_WBFTOMRGCLRENA; + BDK_MSR(s3_0_c11_c0_4, cvmmemctl0); +} + +void bootblock_soc_early_init(void) +{ +} + +void bootblock_soc_init(void) +{ + /* initialize system registers */ + init_sysreg(); + + /* Set watchdog to 5 seconds timeout */ + watchdog_set(0, 5000); + watchdog_poke(0); + + /* TODO: additional clock init? */ +}

new file mode 100644

index 00000000000..69985b78342

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.Snew file mode 100644index 00000000000..69985b78342--- /dev/null+++ b/ src/soc/cavium/cn81xx/bootblock_custom.S @@ -0,0 +1,257 @@ +/* + * Early initialization code for aarch64 (a.k.a. armv8) + * + * Copyright 2016 Cavium, Inc. <support@cavium.com> + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/asm.h> +#include <soc/addressmap.h> + +ENTRY(_start) + .org 0 + /** + * According to the reference manual the first instruction is fetched from + * offset 0x100, but at offset 0 a branch instruction is always placed. + * Support two entry points for now. + * To save memory put the cavium specific init code between those to entry + * points. + */ + ic ialluis + fmov d30, x0 /* Save X0 in FPR for use later */ + fmov d31, x1 /* Save X1 in FPR for use later */ + adr x1, _start /* x1 = _start location based on PC */ + fmov d29, x1 /* Save PC in FPR for use later */ + +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + /* Change the core to big endian mode for EL3 */ + mrs x0, SCTLR_EL3 + mov x1, 1<<25 /* Set SCTLR_EL3[ee]=1 */ + orr x0, x0, x1 + msr SCTLR_EL3, x0 + #define ENDIAN_CONVERT64(reg) rev reg, reg + #define ENDIAN_CONVERT32(reg) rev reg, reg + #define ENDIAN_CONVERT16(reg) rev16 reg, reg +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + /* Nothing needed, default is little endian */ + #define ENDIAN_CONVERT64(reg) + #define ENDIAN_CONVERT32(reg) + #define ENDIAN_CONVERT16(reg) +#else + #error Unknown endianness +#endif + + mov x0, (LMC0_PF_BAR0 >> 32) + lsl x0, x0, 32 + mov x1, (LMC0_PF_BAR0 & 0xffffffff) + orr x0, x0, x1 + + /* Test if DRAM PLL is running */ + ldr x1, [x0, LMC0_DDR_PLL_CTL0] + + tst x1, 0x80 + + b.ne cache_setup_done + + bl _setup_car + +cache_setup_done: + + /* Check that we're running on the node we're linked for */ + mrs x0, MPIDR_EL1 + ubfx x0, x0, 16, 8 /* Bits 23:16 are the physical node ID */ + mov x1, 0x0 + cmp x0, x1 + + b.ne _wfi + +node_check_done: + /* Get code position */ + mov x1, 0x020000 + mov x0, BOOTROM_OFFSET + add x1, x0, x1 + + adr x0, _start + + /** + * Check if IROM has loaded the code to CONFIG_BOOTROM_OFFSET. + * In case the offset is wrong, try to relocate. + * Ideally the following code is never executed. + * FIXME: Add region overlap check. + */ + cmp x0, x1 + b.eq after_relocate + +relocate: + /* Get bootblock length */ + ldr x2, =_program + ldr x3, =_eprogram + sub x2, x2, x3 + b copy_code + +.align 7 +copy_code: + ldp q0, q1, [x1], 32 /* Load 32 bytes */ + subs w2, w2, 32 /* Subtract 32 from length, setting flags */ + stp q0, q1, [x0], 32 /* Store 32 bytes */ + b.gt copy_code /* Repeat if length is still positive */ + dmb sy + + /* Load the actual location we're suppose to be at */ + adr x0, after_relocate /* Relative address */ + adr x1, _start /* Relative address */ + sub x0, x0, x1 /* This only works if _start is suppose to be zero */ + mov x1, BOOTROM_OFFSET + add x0, x0, x1 + br x0 /* Branch to relocated code */ + + ic ialluis /* Clear the icache now that all code is correct */ + +after_relocate: + /* Allow unaligned memory access as long as MMU is disabled */ + mrs x22, s3_0_c11_c0_4 + orr x22, x22, # (1 << 37) /* Set DCVA47 */ + msr s3_0_c11_c0_4, x22 + + bl start + + /* Real entry point */ + .org 0x100 + b _start +ENDPROC(_start) + + +ENTRY(_setup_car) + mrs x0, MIDR_EL1 + ubfx x0, x0, 4, 12 /* Bits 15:4 are the part number */ + cmp x0, 0xb0 + b.ge _wfi + +thunder1_cache_setup: + /** + * Setup L2 cache to allow secure access to all of the address space + * thunder1 compability list: + * - CN81XX + * - CN83XX + * - CN88XX + */ + #define REGIONX_START 0x1000 + #define REGIONX_END 0x1008 + #define REGIONX_ATTR 0x1010 + mov x0, L2C_PF_BAR0 >> 32 + lsl x0, x0, 32 + mov x1, (L2C_PF_BAR0 & 0xffffffff) + orr x0, x0, x1 + str xzr, [x0, REGIONX_START] /* Start of zero */ + mov x1, 0x3fffff00000 /* End of max address */ + ENDIAN_CONVERT64(x1) + str x1, [x0, REGIONX_END] + mov x1, 2 /* Secure only access */ + ENDIAN_CONVERT64(x1) + str x1, [x0, REGIONX_ATTR] + /* Update way partition to allow core 0 to write to L2 */ + #define L2C_WPAR_PP0_OFFSET 0x40000 + mov x1, L2C_WPAR_PP0_OFFSET + str xzr, [x0, x1] + ldr xzr, [x0, x1] /* Read back to make sure done */ + #undef REGIONX_START + #undef REGIONX_END + #undef REGIONX_ATTR + #undef L2C_WPAR_PP0_OFFSET + + /** + * At this point the whole CAR is readable and writeable, but if + * we touch to many cache-lines our code might get flushed out. + * We have to lock all cache-lines that are to be used as RAM, which are + * the ones marked as SRAM in memlayout. + */ + mrs x0, CTR_EL0 /* Get cache-line size */ + /* [19:16] - Indicates (Log2(number of words in cache line) */ + ubfx x0, x0, 16, 4 + mov x1, 4 /* Bytes in a word (32-bit) */ + lsl x0, x1, x0 /* Number of Bytes in x0 */ + + sub x1, x0, 1 + mvn x1, x1 /* Place mask in x1 */ + + ldr x3, =_sram + and x3, x3, x1 /* Align addresses with cache-lines */ + ldr x4, =_esram + add x4, x4, x0 + sub x4, x4, 1 + and x4, x4, x1 /* Align addresses with cache-lines */ + sub x2, x4, x3 /* Store sram length in x2 */ + +lock_cache_lines: + sys #0, c11, c1, #4, x3 + add x3, x3, x0 /* Increment address by cache-line bytes */ + subs w2, w2, w0 /* Subtract cache-line bytes from length */ + b.gt lock_cache_lines /* Repeat if length is still positive */ + + /** + * The locked region isn't considered dirty by L2. Do read/write of + * each cache line to force each to be dirty. This is needed across the + * whole line to make sure the L2 dirty bits are all up to date. + * NOTE: If we'd relocate we could memset the whole memory ! + */ + ldr x3, =_sram + and x3, x3, x1 /* Align addresses with cache-lines */ + ldr x4, =_esram + add x4, x4, x0 + sub x4, x4, 1 + and x4, x4, x1 /* Align addresses with cache-lines */ + sub x2, x4, x3 /* Store sram length in x2 */ + mov x4, x3 + b dirty_cache_line + +.align 7 +dirty_cache_line: + ldp q0, q1, [x3], 32 /* Load 32 bytes */ + subs w2, w2, 32 /* Subtract 32 from length, setting flags */ + stp q0, q1, [x4], 32 /* Store 32 bytes */ + b.gt dirty_cache_line /* Repeat if length is still positive */ + dmb sy + +clear_interrupts: + /** + * As the memory controller isn't running, but we access the DRAM's + * address space, some interrupt flags had been set. + * Tidy up our mess now on (valid for CN81XX only). + */ + mov x0, (L2C_TAD0_INT_W1C >> 32) + lsl x0, x0, 32 + mov x1, (L2C_TAD0_INT_W1C & 0xffffffff) + orr x0, x0, x1 + + ldr x1, [x0] + orr x1, x1, 0x1c00 /* Clear WRDISLMC, RDDISLMC, RDNXM */ + str x1, [x0] + + ret +ENDPROC(_setup_car) + +ENTRY(_wfi) + wfi +ENDPROC(_wfi) + +ENTRY(start) + bl arm64_init_cpu + + fmov x0, d30 /* The original X0, info from previous image */ + fmov x1, d31 /* The original X1, info from previous image */ + fmov x2, d29 /* The original PC we were loaded at */ + + /* Call C entry */ + bl bootblock_main + +ENDPROC(start)

new file mode 100644

index 00000000000..9716a5da6a9

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/chip.h b/src/soc/cavium/cn81xx/chip.hnew file mode 100644index 00000000000..9716a5da6a9--- /dev/null+++ b/ src/soc/cavium/cn81xx/chip.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_CAVIUM_CN81XX_CHIP_H +#define __SOC_CAVIUM_CN81XX_CHIP_H + +struct soc_cavium_cn81xx_config { +}; + +#endif /* __SOC_CAVIUM_CN81XX_CHIP_H */

new file mode 100644

index 00000000000..bd6514cd41e

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/clock.c b/src/soc/cavium/cn81xx/clock.cnew file mode 100644index 00000000000..bd6514cd41e--- /dev/null+++ b/ src/soc/cavium/cn81xx/clock.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * Copyright 2003-2017 Cavium Inc. <support@cavium.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/clock.h> +#include <arch/io.h> +#include <soc/addressmap.h> + +#define PLL_REF_CLK 50000000 /* 50 MHz */ + +union cavm_rst_boot { + u64 u; + struct { + u64 rboot_pin:1; + u64 rboot:1; + u64 lboot:10; + u64 lboot_ext23:6; + u64 lboot_ext45:6; + u64 reserved_24_29:6; + u64 lboot_oci:3; + u64 pnr_mul:6; + u64 reserved_39_39:1; + u64 c_mul:7; + u64 reserved_47_54:8; + u64 dis_scan:1; + u64 dis_huk:1; + u64 vrm_err:1; + u64 jt_tstmode:1; + u64 ckill_ppdis:1; + u64 trusted_mode:1; + u64 ejtagdis:1; + u64 jtcsrdis:1; + u64 chipkill:1; + } s; +}; + +/** + * Returns the reference clock speed in Hz + */ +u64 thunderx_get_ref_clock(void) +{ + return PLL_REF_CLK; +} + + +/** + * Returns the I/O clock speed in Hz + */ +u64 thunderx_get_io_clock(void) +{ + union cavm_rst_boot rst_boot; + + rst_boot.u = read64((void *)RST_PF_BAR0); + + return rst_boot.s.pnr_mul * PLL_REF_CLK; +} + +/** + * Returns the core clock speed in Hz + */ +u64 thunderx_get_core_clock(void) +{ + union cavm_rst_boot rst_boot; + + rst_boot.u = read64((void *)RST_PF_BAR0); + + return rst_boot.s.c_mul * PLL_REF_CLK; +}

new file mode 100644

index 00000000000..c054aa89872

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.cnew file mode 100644index 00000000000..c054aa89872--- /dev/null+++ b/ src/soc/cavium/cn81xx/cpu.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-present Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <arch/io.h> +#include <soc/cpu.h> +#include <bdk-coreboot.h> + +/* Return the number of cores available in the chip */ +size_t cpu_get_num_cores(void) +{ + uint64_t available = read64((void *)0x87e006001738ll); + return bdk_dpop(available); +}

new file mode 100644

index 00000000000..340ac1bc733

--- /dev/null

+++ b/ diff --git a/src/soc/cavium/cn81xx/gpio.c b/src/soc/cavium/cn81xx/gpio.cnew file mode 100644index 00000000000..340ac1bc733--- /dev/null+++ b/ src/soc/cavium/cn81xx/gpio.c @@ -0,0 +1,193 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <soc/gpio.h> +#include <arch/io.h> +#include <endian.h> +#include <soc/addressmap.h> + +union gpio_const { + u64 u; + struct { + u64 gpios:8; /** Number of GPIOs implemented */ + u64 pp:8; /** Number of PP vectors */ + u64:48; /* Reserved */ + } s; +}; +union bit_cfg { + u64 u; + struct { + u64 tx_oe : 1; /* Output Enable */ + u64 xor : 1; /* Invert */ + u64 int_en : 1; /* Interrupt Enable */ + u64 int_type : 1; /* Type of Interrupt */ + u64 filt_cnt : 4; /* Glitch filter counter */ + u64 filt_sel : 4; /* Glitch filter select */ + u64 tx_od : 1; /* Set Output to Open Drain */ + u64 : 3; + u64 pin_sel : 10; /* Select type of pin */ + u64 : 38; + } s; +}; + +struct cavium_gpio { + u64 rx_dat; + u64 tx_set; + u64 tx_clr; + u64 multicast; + u64 ocla_exten_trg; + u64 strap; + u64 reserved[12]; + union gpio_const gpio_const; /* Offset 90 */ + u64 reserved2[109]; + union bit_cfg bit_cfg[48]; /* Offset 400 */ +}; + +/* Base address of GPIO BAR */ +static const void *gpio_get_baseaddr(void) +{ + return (const void *)GPIO_PF_BAR0; +} + +/* Number of GPIO pins. Usually 48. */ +gpio_t gpio_pin_count(void) +{ + struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr(); + union gpio_const gpio_const; + + gpio_const.u = read64(®s->gpio_const.u); + + if (gpio_const.s.gpios > 64) + return 64; // FIXME: Add support for more than 64 GPIOs + return gpio_const.s.gpios; +} + +/* Set GPIO to software control and direction INPUT */ +void gpio_input(gpio_t gpio) +{ + struct cavium_gpio *regs = (struct cavium_gpio *)gpio_get_baseaddr(); + union bit_cfg bit_cfg; + + if (gpio >= gpio_pin_count()) + return; + + printk(BIOS_SPEW, "GPIO(%u): direction input

", gpio); + + bit_cfg.u = read64(®s->bit_cfg[gpio]); + bit_cfg.s.pin_sel = 0; + bit_cfg.s.tx_oe = 0; + write64(®s->bit_cfg[gpio], bit_cfg.u); +} + +/* 