Designing circuit boards for high speed applications requires special considerations. This you already know, but what exactly do you need to do differently from common board layout? Building on where I left off discussing impedance in 2 layer Printed Circuit Board (PCB) designs, I wanted to start talking about high speed design techniques as they relate to PCBs. This is the world of multi-layer PCBs and where the impedance of both the Power Delivery Network (PDN) and the integrity of the signals themselves (Signal Integrity or SI) become very important factors.

I put together a few board designs to test out different situations that affect high speed signals. You’ve likely heard of vias and traces laid out at right angles having an impact. But have you considered how the glass fabric weave in the board itself impacts a design? In this video I grabbed some of my fanciest test equipment and put these design assumptions to the test. Have a look and then join me after the break for more details on what went into this!

What I Mean By “High Speed”

The term “high speed design” can mean different things to different people depending on what they are used to working with, but for me it’s where the energy of the rising and falling edges of the signals dominate the behavior compared to the fundamental frequency of the signal itself. In other words a 10Mhz signal that has a 1ns rise time has a bandwidth of roughly 350Mhz as seen by the formula below. Ultimately it’s the energy in the rise/fall time of the signal that affects a lot of the design.

The relationship between the bandwidth and the rise time can be approximated as:

With regard to high speed design rules, my first rule of thumb is to be cautious about rules of thumb. I use rules of thumb as an early estimate that helps me to get an idea of how all of my design rules and goals play together.

As someone who has been doing design since the 1970’s I have seen the evolution of assumptions and design guidelines mature and it’s fair to say that there were a couple of things that we got wrong along the way, some things almost comically wrong. For example, I have heard people say that electrons slam into each other trying to turn corners at high speeds so it’s a bad thing to do, we now don’t think that way.

High Speed Design Assumptions

Some of the principles of high speed design are listed below. I can’t get to all of them in this one post but I do want to get to all of them in turn.

At high speeds it’s all about the propagation of the Electro-Magnetic (EM) field, not electrons.

High speed current follows the path of least impedance on a power or ground plane, not the path of least resistance.

Due to the geometry of the glass fabric weave used in the construction of the PCB, the impedance of a signal trace may change based upon the orientation and the position in relation to the weave.

Right angle corners in PCB traces may not be near as detrimental as often assumed.

In a properly designed multi-layer PCB, the placement of decoupling capacitors near the loads may not be near as critical as is assumed.

Ferrite beads in line with the various voltage traces may do more harm than good.

Differential pairs aren’t coupled to each other like we often depict, their return current is through the ground plane, not through the other half of the pair of traces.

Tightly coupling a differential pair may not have as good of noise rejection as two random paths provided they are the same length.

Since the current flows on the surface of a conductor (known as skin effect) high speed PCB’s may specify smooth or polished copper traces for the inner layers so that the path is smoother and straighter.

EM Fields

At high speeds it’s not so much about the flow of electrons but rather the energy in the Electromagnetic (EM) field and the way those fields propagate. Yes some electron displacement occurs along the way but a simple way of looking at this statement is that all of this works in a vacuum.

If you were to picture multiple traces in the same dielectric space you can see that the fields would overlap and consequently interact with each other. This is one of the primary causes of crosstalk. Another way of saying this is that crosstalk occurs in the whitespace between the conductors where the fields overlap and interact.

A function of thinking of signals and their EM fields racing around is that the return current follows as closely to the outbound signal as possible. Last time I talked at length about the fact that the path of minimum inductance is the path that forms the smallest loop between the outbound and return currents. Consequently this means that the return current follows the path of least inductance, hence the path of least impedance (Z). Impedance is the combination of resistance(R), inductive reactance (X L ) and capacitive reactance (X C ) all measured in Ohms (Ω)

The image on the left above shows the return current density follows the signal on a single layer. In real life, signals often jump layers and in order to have the return current continue to follow the signal closely (and therefore control the impedance) we have to place VIAs nearby that connect the internal reference (ground or power) planes. This is shown on the right.

Impedance Testing

To continue testing some of my design rules listed in the beginning I built a PCB to test the impedance of different PCB traces.

PCBs are constructed of layers of conductors (typically copper) and dielectrics (typically epoxy coated glass fibers). As speeds go up these materials become more and more specialized. Since the glass fibers or weave are uneven, they can have an effect based upon how the conductors interact with the weave of the fibers as shown below.

Simply put, traces that align directly with the row of the glass fibers will have a different impedance than the trace that experiences alternating bundles of fibers.

Likewise a trace in the vertical direction will see a different amount of glass under it than a horizontal trace due to the differences of the weave density in different directions. One answer is to spread the fibers out during PCB fabrication, but as you might expect, the price of the completed PCB starts going up.

One way to test the impedance of a PCB trace and to see changes along the path, is a high speed Time Domain Reflectometer (TDR). TDR’s are commonly used at slower speeds as in cable testing, [W2AEW] has a very informative video on the whole theory behind it.

High Speed Time Domain Reflectometer

Behind the technology is a fast rise time pulse. I had actually started to write this post as instructions on how to make a fast rise time generator using various techniques after reading Jenny List’s article on pulse edges. During my research I bought a pulse generator that clocked in at 32 picosecond (ps) rise time (sold as 40ps or faster) designed by an engineer named Leo Bodnar. When I received my pulse generator I saw that Leo had used a venerable piece of equipment known as the Tek CSA803/SD24 Communications Signal Analyzer (CSA) which has a 20Ghz bandwidth and a 17.5 ps rise time pulse to characterize my module. I just had to have one of these CSA’s myself and watching eBay got me a good find, though I haven’t told my wife yet. With this new-to-me piece of equipment I set off to test how easily I could see the effects of the glass fiber direction on impedance.

Horizontal vs. Vertical PCB Traces

As can be seen below there is a definite difference in the baseline impedance based upon the direction of the PCB trace. See the video for all of the fun in setting up for these pictures.

You can see a definite and measurable difference in the impedance of the traces based upon the orientation of the trace on the board, in the case of this board the Vertical trace was off by approximately five percent.

There are a couple of techniques that help deal with this effect without the cost of going to a more expensive PCB with a tighter glass weave. My CAD software supports the two main techniques shown below to help automate the process but both can be done manually as well. The first technique entails zig-zagging in a not-so-orthogonal way in an effort to statistically reduce the effects. If there is the option of laying out the PCB in a larger panel then it can be cocked to one side (I have heard 10-11 degrees but it is affected by other variables as well) so that again the sum of signals running down the worst case paths is minimal

Shocking Discovery: Square Corners Probably Don’t Matter

One of the factoids that plague the industry is the concern about what the effect of right angle corners used on PCB traces might have on the impedance of those traces. Other complaints are that the RFI emissions are higher with right angles and that acid can build up in the corners during the fabrication. I will put this board on the spectrum analyzer and check for “EMI spray” in the next video post and if your PCB fab house complains about acid in the corners then I would humbly suggest that one find a different fabricator.

I set out to see if I could detect the effects of corners myself with my new 20Ghz capability. As seen above the effects of right angle corners at 20Gz (.35/17.5ps=20Ghz) with a trace width of 5.27mil (calculated for 50Ω Impedance) on the characteristic impedance are minimal.

Square Corners Mean More Capacitance, but Not Much

At the heart of the debate over square corners vs. angled corners is the slight change in capacitance due to the change in trace width represented by a square corner.

We know the capacitance of the area of the metal since we are talking about 50Ω impedance in general. Per the equations above a 6mil trace would have an additional capacitance of 9.6fF (femtofarad), or 0.0000000096 μF, this is really small. The other thing that minimizes the effect of the corner is just how fast it goes by at the velocities we are talking about, which are sizable fractions of the speed of light. Given that a signal travels 6 inches in 1ns on a standard FR4 PCB, the signal will get through the corner in 30ps. (Which is why I have to use equipment with a 17.5ps rise time to examine it)

More about this can be seen in Eric Bogatin’s post on EDN where he comes up with a nice rule of thumb:

If your rise time is 10ps, don’t worry about corners unless your 50O line widths are wider than 50mils.

If concerned about corners on your design, ascertain what your bandwidth is (35Ghz for 10ps rise time) and your trace features, given that 50mils is really big for a signal trace, it is more like a power trace in most designs.

Just for the Heck of It.

Just for the heck of it I ran the same test only instead of corners I had “hanging VIAs” which admittedly are worse case as they are like little capacitors and antennas hanging off the trace. I wanted to be sure to have something that would show up as an example of worse case when compared to right angle corners and this example did not disappoint.

Conclusion

The point I really wanted to get across is to be cautious when considering rules of thumb type advice. Question the sources of information, and do not be afraid to measure for yourself what you can when you can if in doubt. Above all else ask the question, “How do you know?”.

As these results were all demonstrated in the “time domain”, I will be demonstrating some of the aspects of the “frequency domain” as it relates to high speed design in the next installment.