Semiconductor Engineering sat down to discuss changes in the FD-SOI world and what’s behind them, with James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science; Giorgio Cesana, director of technical marketing at STMicroelectronics; Olivier Vatel, senior vice president and CTO at Screen Semiconductor Solutions; and Carlos Mazure, CTO at Soitec and chairman of the SOI Consortium. What follows are excerpts of that conversation.



L-R: James Lamb, Giorgio Cesana, Olivier Vatel, Carlos Mazure.

SE: We’ve been hearing about FD-SOI for years, but it was always something that was going to be important at some future node. It seems to be really gaining traction now? What’s changed?

Mazure: It takes a while to develop technologies and to bring it to a certain maturity. If you step back, the benefits and potential of FD-SOI were underlined by Chenming Hu of the University of California at Berkeley. He is well known today as the inventor of finFETs, but he brought up a planar version as well as the vertical version. This was early 2000s. At the time, the technology was not there. But since then the technology has improved, which made this path possible. That’s one of the first hurdles we had to overcome. From there we had to get the whole ecosystem moving. It’s not just the substrate that had to move. Leti played a very important role in the development of the initial FD-SOI devices. Soitec was instrumental in developing the FD-SOI substrate. We worked very closely at ST with the IBM Alliance in Albany. At the time, the issue was what part of the specification we needed to meet to make this a reality. Nobody was going to move from a known problem to an unknown solution that may have problems. So there was some very good work done there with ST, Soitec and IBM. When manufacturability became a reality, all ecosystems began to accelerate. This was in the 2010 to 2011 timeframe. That picked up with a partnership between ST and Samsung Foundry. Then came GlobalFoundries. With the foundry piece in place, companies began to adopt the technology—NXP, Sony, Mobileye, Lattice. Today the IP is good enough to make any sort of application possible. We’re looking at a different application space, of course. This is about power-efficient applications. It’s IoT, 5G, automotive and edge computing.

Cesana: We had some opportunities in the past, such as at 28nm, which is already prime time because applications need that. But today, there are even more interesting opportunities. FD-SOI is not in competition with finFETs. Each targets different application areas. FinFET is for where you need very high integration density and ultra-high speeds. It’s perfect for phones, where you need a lot of computing power. It’s widely used in cloud computing and AI. But when we look at the market trends and the new driving applications, we see more and more of a trend with IoT in production. In the past there was this idea that there would be dumb sensors, which just acquire data and transmit everything to the cloud, and the cloud would be where all the computing is done. The main reason for that was the applications had not matured yet, so you concentrate everything in one place. You have companies like Google and Amazon thinking about new applications. But when you develop more ideas about what you can do with this technology, you can move from a centralized to a distributed model. You have computing in the nodes or the edge, and you don’t have to transmit everything. You solve the confidentiality problem. You solve the power problem, because wireless transmission takes much more power than a simple computation on the node itself. If you put computing someplace to centralize it, you need more power. Transmitting one bit takes 4 to 5 picojoules. When you add up all of that, it takes a lot of energy. So now we have more applications that have to be developed at the edge than at the leading nodes, and you need a level of integration density that doesn’t necessarily justify using finFETs, which are expensive. FinFET technology is there when you need to integrate a huge amount of gates, but for midsize applications it’s too much. When you move to those nodes, you’re not just doing digital. You’re developing analog to interface with the sensor. You want to have the RF connectivity. And if you put your analog in one technology, your digital in another and your RF in another, the cost increases. If you want to sell something for $10, you cannot do that with finFETs. That’s why FD-SOI has a huge opportunity. When you look at the different announcements, we see more and more applications. I’m expecting to see a lot of FD-SOI around very soon.

Lamb: For SOI, because it’s not pushing the leading edge of the nodes, there are clear paths forward for lithography. There’s actually a very significant reduction in steps, which helps you to get back some of the extra costs for the (SOI) wafers. You can reduce steps by 20% to 30% from what you would do with a finFET structure to achieve a similar power capability. We can re-use all the learning we’ve done to push the nodes for finFETs down into 16/14/10nm and below. So it’s pretty old-school for producing the lithography you need for SOI at this point. With FD-SOI you have a lower density approach, which means you can do direct printing of small structures without resorting to SADP or SAQP. You can pattern them directly all the way down to 16nm. Now if you want to get denser gates, you have to apply SADP. But as long as there’s isolation room, you can shrink to what you need. Lithography is actually fairly simple for these applications.

Vatel: Screen is incorporating leading-edge technology with finFETs. At the same time, the business opportunity from older fabs is not to buy leading-edge tools. The advancements of FD-SOI and the volume of 22nm are certainly very good business for us. For innovation, there is a very different set of requirements, though. FD-SOI is really driving new uses for older technology. It’s not at the cutting edge like finFETs, but it’s still interesting enough to semiconductor makers.



Fig. 1: FD-SOI wafer and planar transistor. Source: Soitec

SE: Does it require 300mm equipment, or is it mostly 200mm?

Vatel: We launched a full line on 28nm several years ago, and we are seeing the benefits of this. We see a clear demand today for the metal capability at 22nm. It is a very important technology.

Mazure: Today, RF is driving 200mm capacity along with automotive. That’s a different type of SOI and a differen type of market, but all of that is driving FD-SOI capacity. There is a trend to add capacity in 300mm for RF. But there is an emphasis on this being in addition to 200mm, because it’s not going to empty the 200mm fabs. This is additional capacity, and it’s going to continue as 5G becomes the mainstream driver.

SE: 200mm equipment is constrained today. There’s not enough capacity, and there’s demand for more.

Vatel: It’s good for us. There isn’t much of a used market anymore, and we’re not complaining. But there are benefits for moving to 300mm, both for the companies using it and for strategic reasons.

Mazure: 200mm fabs are fully depreciated, so they don’t have to buy new tools. But if you want to keep your fab current and competitive, you need to add 300mm capabilities.

SE: Are backward and forward biasing available for FD-SOI now?

Cesana: Biasing is available in one direction or another. You cannot mix the two on the same logic. But NXP showed that they had some logic using forward bias for speed optimization, and another part of the logic using reverse bias for leakage optimization. It is possible on the same chip, but not on the same logic. Both 28 and 22 use the same technology, where you can not use forward and reverse bias on the same transistors.

SE: Are there enough people who know how to do this?

Mazure: There are some companies that do understand it. But one of the actions that we have at the SOI Consortium is exactly that—to continue developing the momentum with the IP and EDA companies so that the foundation libraries take into account the potential for reverse and forward biasing. From there you can build it into the IP in such a way that for the designer this becomes very transparent. Then we basically overcome the hurdle. Today it is very specialized and you really have to know how to use it. But once this is added at the foundation level, generating your high-level IP is just business as usual.

SE: How does this play out for the materials market?

Lamb: We’re definitely seeing more of our materials being used for SOI chips. But a lot of times those companies are developing finFET technology, too. Ascertaining how much of the materials flow into one stream or the other isn’t easy, but we know our materials are being used in both environments.

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