Your browser does not support the audio element.

When TSMC Chairman Morris Chang appeared at the Presidential Office in November 2017, he was not in the spotlight for a change. Instead, he watched and applauded from his seat in the audience as Douglas Yu, TSMC’s R&D vice president for integrated interconnect and packaging technology, received an award from President Tsai Ing-wen.

It was the Presidential Science Prize, Taiwan’s highest scientific honor, awarded once every two years.

Yu captured the award for developing two advanced IC packaging technologies – InFO (integrated fan-out) and CoWoS (chip-on-wafer on substrate).

“This is InFO,” Yu says, pointing to an iPhone being held by a reporter sitting next to him. “It started with the iPhone 7 and continues to be used in the iPhone 8 and iPhone X. In the future, other phones will start to incorporate this technology.”

Limited Thickness the Difference

In the early years of the iPhone, the device’s processor was the exclusive domain of Samsung. Starting with the A11 processor, however, TSMC secured exclusive orders for two generations of iPhone processors, sending its sales and stock price skyrocketing.

Among the keys driving this success was Yu’s Integrated Interconnect and Packaging Technology Division.

Its completely new InFO packaging technology enabled chips to be mounted directly on top of each other, reducing the package’s thickness and freeing precious smartphone space for the battery or other components.

“Our first-generation InFO was less than a millimeter,” which means a thickness reduction of about 30 percent, Yu says.

As Nicky Lu, the chairman of Etron Technology and former head of the Taiwan Semiconductor Industry Association says of his friend Yu: “It was because of him that TSMC was able to secure three generations of Apple orders.”

The first inkling that Yu’s innovations might one day be possible came at TSMC’s investor conference for the third quarter of 2011 when Chang, without any advance warning, shocked everybody by announcing his company would move into the packaging and testing field.

The first product would be “CoWoS,” which integrates logic computing and memory chips by mounting them on a silicon “interposer” and then placing them directly on a substrate, a process that delivers high-speed computing while reducing heat and saving space.

Chang said at the investor conference that the CoWoS technology would lead to a business model in which TSMC could provide the entire packaged chip.

The news immediately rippled through the global semiconductor industry.

From that point on, the dapper Yu began attending several technology seminars at home and abroad to promote this new home-grown technology.

At the time, this division chief made a deep impression on a CommonWealth Magazine reporter because of his eloquence and occasionally sharp tongue, which was in stark contrast to the typical unobtrusive style of most TSMC executives. His willingness to mix it up quickly became clear.

When Chang announced that the global leader in contract chip manufacturing was getting involved in downstream operations, the market started to worry about the future of dedicated packaging and testing suppliers, such as Taiwan-based Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industry (SPIL).

ASE and SPIL tried to play down the threat, arguing that CoWoS technology could only be used in a “select few” high-end products and would only have a limited impact.

Yu, however, bluntly fired back: “In the future, all high-end products will use this. The market is huge.”

The packaging and testing industry’s discontent slowing simmered before finally erupting at a technology seminar, with an SPIL R&D executive directly attacking Yu after he delivered a speech.

“So what you mean to say is that we’ll be out of a job in the future and don’t need to have anything to do,” the SPIL executive said.

Not long afterwards, Yu suddenly disappeared from view.

“We all wondered why it was that he disappeared. We later heard it was Morris Chang who stepped in and asked Yu to be more low-key,” says an executive at a major packaging and testing provider who spoke on condition of anonymity.

In an interview with CommonWealth at the time, former TSMC co-chief operating officer Chiang Shang-yi explained his company’s move.

“Moore’s Law has started to slow down, but there is a lot of room for improvement in the overall electronic system, in terms of both the printed circuit board and packaging,” Chiang said.

Over the previous few decades, the amazing leaps made because of Moore’s Law – which says the processing power of computers will double every two years at the same cost – had overshadowed advances made to other parts of electronic circuits. Because of that, the packaging and testing sector had concentrated its development on cutting costs and had failed to achieve any technological breakthroughs for a long time.

Chang supported the initiative, redeploying 400 R&D engineers to Yu, who lived up to expectations by developing the CoWoS technology in just two to three years.

But until the production actually went into mass production, there was only one main company placing orders – programmable logic device supplier Xilinx Inc.

Beating Out Samsung

The success of the technology would ultimately be decided by whether TSMC could wrestle away orders for the iPhone processor from Samsung, which had long been Apple’s exclusive processor supplier in large part because of its integrated operations.

The A7 processor Samsung produced in 2013 for the iPhone 5s and wrapped in a black resin consisted of an ultra-thin PoP (package on package) that stacked a 1GB DRAM and the processor together.

Samsung was the world’s only semiconductor vendor at the time that could mass produce both memory chips and processors and had its own captive packaging and testing facility. Contracting the A7 to Samsung meant it could be produced “under one roof,” offering massive cost and integration advantages.

As a result, even though Samsung’s line of Galaxy smartphones were emerging as a growing threat to Apple’s dominance of the high-end smartphone market, Apple had no way to free itself from its dependence on its biggest rival.

TSMC’s CoWoS technology could theoretically cut the processor’s thickness by 70 percent, but customers were generally not interested.

At one point, Chiang had dinner with “a big customer,” who told him that for this technology to be viable, it could cost no more than US$0.01 per square millimeter, a near impossibility considering that the new CoWoS solution’s price was five times that.

But TSMC immediately set its sights on developing an advanced packaging technology that could meet the price without compromising too much on the functions of the CoWoS solutions.

“I made every effort to push, push and push some more,” Yu recalls. He decided on an “addition by subtraction” approach that cut the CoWoS structure to its bare bones to generate a streamlined design.

The result was the InFO packaging technology that enabled TSMC to secure Apple orders and was then first used in the iPhone 7 and iPhone 7 Plus.

And those orders were not for just a single iPhone generation, but also for the premium iPhone X that hit the market late last year and new models set to come out this year. An analyst with a foreign brokerage says there are growing indications that TSMC is increasingly likely to also snag Apple’s orders for 2019 and 2020.

Doing the Impossible

In November 2016, as large quantities of the iPhone 7 with InFO technology were being shipped, TSMC promoted Yu to vice president responsible for the Integrated Interconnect and Packaging Technology Division.

“At the beginning, nobody gave us much of a chance, ” Yu says with a sigh.

Part of that was the problem of costs and fierce competition in the packaging and testing sector. Packaging solutions providers were investing in technologies similar to those being developed by TSMC, and TSMC’s manpower costs were far higher than those of the packaging specialists.

As a result, TSMC needed gross margins of 50 percent to cover those high personnel costs while ASE and SPIL could accept jobs with 20 percent gross margins.

Analysts at foreign brokerages were also initially down on TSMC’s prospects. Mark Li, a senior research analyst at Sanford C. Bernstein, argued that Samsung and Intel had built up far more experience and technology in the field than TSMC. Intel and Samsung, for example, ranked second and third in the world in number of patents for “fan-out wafer level package” technology, while TSMC was not ranked in the top 10.

That pessimism was reasonable, so why was Douglas Yu able to pull off this “mission impossible.”

He gave a surprising answer: “I went all in. I had nothing to lose.”

CoWoS: Thousands of Bad Wafers Later

Yu says that while he was undergoing major changes on the job as he moved into packaging and testing, his family was facing challenges as well and his life hit bottom, but that only further fueled his determination to overcome any challenges that came his way.

TSMC’s InFO and CoWoS are both “wafer level packaging” technology, meaning that the chip is packaged directly on the wafer, enabling a major reduction in the size of the package and an improvement in efficiency.

TSMC was the first major semiconductor foundry to mass produce products using wafer-level packaging technology. But as a company on the cutting edge, it has faced countless technical challenges that demanded solutions, such as the tricky puzzle of wafer warpage.

A senior executive in the packaging sector who has been involved in Apple orders says TSMC’s learning curve has been extremely costly, its production line having damage thousands of very expensive wafers over a five-year period.

“I heard that [TSMC] had trouble improving its yield rate, which didn’t hit 80 percent until last year,” says another source, an executive working for a TSMC customer.

Through Yu’s unflinching determination, TSMC finally began to see light at the end of the tunnel in the packaging field in 2016.

For one thing, new customers for the CoWoS technology emerged in large numbers, validating Yu’s prediction years earlier in his spat with packaging and testing specialists that the newest and most advanced chips must use CoWoS technology. That’s because the CoWoS approach by that time could improve the performance of advanced products three- to six-fold.

That year, graphics giant nVidia introduced its first graphics processing unit (GPU), the GP100, to incorporate CoWoS packaging technology, opening the curtain on the more recent artificial intelligence craze. All of the most advanced, highest priced artificial intelligence chips, such as Google’s TPU 2.0 that powered AlphaGo’s victory over Go champion Ke Jie in May 2017, started to make use of CoWoS solutions.

Even Intel had no choice but to outsource to its Taiwanese rival the production of the Nervana neural network processor it introduced with Facebook at the end of 2017 to challenge nVidia’s dominance in the field.

“Without CoWoS, the huge AI wave would never have appeared so quickly,” Yu says proudly, noting that demand is currently outstripping TSMC’s CoWoS capacity.

Over the past few years, outside observers closely following the competition between TSMC, Samsung and Intel have focused on advances in dream technologies such as the 7-nanometer process and extreme ultraviolet lithography. Ultimately, however, it was the relatively unsung packaging and testing division that made the difference in helping TSMC put some distance between it and its two closest competitors.

Additional Reading

♦ Unveiling TSMC’s Secret Weapon

♦ TSMC Takes on Samsung

♦ Making Every Battle Count