What is Glasgow Interface Explorer?

Glasgow is a tool for exploring digital interfaces. It is designed for embedded developers, reverse engineers, digital archivists, electronics hobbyists, and anyone else who wants to communicate with a wide selection of digital devices while enjoying maximum reliability and minimum hassle. It can be attached to most devices without additional active or passive components, and it provides extensive protection from unexpected conditions and operator error.

The Glasgow hardware can support many digital interfaces because it uses reconfigurable logic. Instead of offering just a small selection of standard hardware supported interfaces, it uses an FPGA to adapt on the fly to the task at hand without compromising performance or reliability, even for unusual, custom or obsolete interfaces.

The Glasgow software is a set of building blocks designed to eliminate incidental complexity. Each interface is packaged into a self-contained applet that can be used directly from the command line or integrated into a more complex system. Using Glasgow does not require any programming knowledge, though it is much more powerful if you know a bit of Python.

Features

Below are a few of the tasks that Glasgow already performs quite well:

Communicating via UART Automatically determining and following the baud rate of the device under test

Initiating transactions via SPI or I²C

Reading and writing 24-series EEPROMs

Reading and writing 25-series Flash memories Determining memory parameters via SFDP

Reading and writing ONFI-compatible Flash memories

Determining memory parameters via ONFI parameter page

Programming and verifying AVR microcontrollers with SPI interface

Automatically determining unknown JTAG pinouts

Playing back JTAG SVF files

Debugging ARC processors via JTAG

Debugging some MIPS processors via EJTAG

Programming and verifying XC9500XL CPLDs via JTAG

Synthesizing sound using a Yamaha OPL chip and playing it in real time on a webpage

Reading raw modulated data from 5.25" and 3.5" floppy drives

...and much more!

Everything above can be done with only a Glasgow revC board, some wires, and – depending on the device under test – external power. No additional frontend circuitry is needed.

Technical Specifications

iCE40HX8K Lattice Semiconductor FPGA (supported by a fully open source FPGA flow)

FX2 HighSpeed USB interface capable of saturating 480 Mbps throughput

Two 8-channel GPIO banks provide 16 highly flexible GPIO

Each GPIO is capable of a theoretical speed up to 100 MHz (actual speed depends on many factors)

Each GPIO has a dedicated level shifter with individual direction control

Each GPIO has a dedicated, software controlled 10 K Ohm Pull-Up/-Down resistor

Each GPIO bank has a dedicated programmable linear voltage regulator, configurable from 1.8 V to 5 V and capable of providing up to 150 mA of power

Each GPIO bank has a dedicated sense ADC capable of monitoring the GPIO bank voltage

All GPIO have ESD protection diodes

An optional set of 14 differential pair GPIO, connected directly to the FPGA without any frontend circuitry, can be used for high speed interfaces

A dedicated SYNC connector

Five user-controllable LEDs connected to the FPGA

Five status LEDs

Legend

(Click to Expand)

Block Diagram

(Click to Expand)

What Software Does Glasgow Use?

Glasgow Interface Explorer is written entirely in Python 3. The interface logic that runs on the FPGA is described using Migen (and is currently being ported to nMigen), which is a Python-based domain specific language. The supporting code that runs on the host PC is written in Python with asyncio. This way, the logic on the FPGA can be assembled on demand for any requested configuration, keeping it as fast and compact as possible, and code can be shared between gateware and software, removing the need to add error-prone "glue" boilerplate.

Glasgow would not be possible without the open source iCE40 FPGA toolchain, which is not only very reliable but also extremely fast. It is so fast that FPGA bitstreams are not cached (beyond what is necessary to avoid rebuilding the bitstream that is already on the device), as it only takes a few seconds to build one from scratch for something like an UART. When developing a new applet, it is rarely necessary to wait for the toolchain.

Implementing reliable, high-performance USB communication is not trivial – packetization, buffering, and USB quirks add up. Glasgow abstracts away USB. On the FPGA, applet gateware writes to or reads from a FIFO; on the host, applet software writes to or reads from a socket-like interface. On a modern PC, Idiomatic Python code can communicate at speeds up to USB 2 bulk bandwidth without additional effort. Moreover, this design is relatively future proof, as it can support different transports, such as Ethernet, without requiring changes to applet code.

Debugging new applets can be hard, especially where bidirectional buses are involved. Glasgow provides a built-in, cycle-accurate logic analyzer that can relate the I/O pin level and direction changes to commands and responses received and sent by the applet. The logic analyzer compresses waveforms and can pause the applet if its buffer is about to overflow.

How Can I Learn More?

Visit the Glasgow GitHub project page, and ask away in the glasgow Freenode IRC channel or on the 1BitSquared Discord server, and follow esden and whitequark on Twitter.