There comes a point when more simply isn’t better, but according to MediaTek, the mobile industry hasn’t reached it yet. The upstart Taiwanese company is punching the throttle on multi-core SoC design, with plans to scale up to 10 cores in a single chip. This new chip is called the Helio X20, and it appears to use a modified version of ARM‘s big.Little protocol to limit power consumption.

big.Little is the power-saving technology ARM has built into its core designs, and it can be implemented in multiple ways. At the simplest level, it provides a way for the operating system to switch workloads from large, power-hungry “big” cores to smaller, power-efficient, and lower-clocked “little” cores. Because this task switching takes time, however, it’s not the preferred method of implementing the capability. The most advanced big.Little implementation involves Global Task Scheduling (GTS) in which the OS is aware of all the cores on the SoC and can intelligently pick the best cores for any given workload.

WCCFTech has details on the new SoC design, which combines multiple clusters of high-performance and budget cores, but then implements two groups of Cortex-A53s. One design runs at 2GHz with the other at 1.4GHz. It’s likely that the 1.4GHz chips do draw substantially less power, since voltage scaling isn’t linear and power consumption in SoCs rises at the square of the increased voltage. But the benefits of a deca-core design are dubious.

Can 10 cores ever make sense?

There’s always been a question over whether big.Little made sense compared with other methods of reducing CPU power consumption. AMD and Intel, for example, have always made use of DVFS (AMD now uses AVFS in its Carrizo APUs). These methods reduce the frequency and operating voltage of the CPU rather than switching workloads from large, heavy-duty CPU cores to small, svelte ones. They also require additional planning to implement and can increase implementation costs — but building more cores also increases die size, and may or may not yield equivalent gains depending on how sophisticated the Global Task Scheduler actually is.

The problem with this approach is that subdividing the segment further may not get you much actual performance, while the difficulty of properly aligning core workload with CPU state gets worse at every stage. MediaTek is implementing this core in 20nm instead of 28nm, which means the company won’t gain some of the power and efficiency improvements that FinFETs are expected to deliver at the 14/16nm nodes. At a certain point, it makes more sense to scale the frequency and voltage of fewer cores rather than continuing to push the envelope with more and more core clusters clocked at different frequencies.

The other problem with this type of core design is that Global Task Scheduling’s ability to improve performance by sharing workloads between the bigger and smaller cores will be intrinsically limited by the SoC’s temperature and power consumption. There’s simply no way to spin up all 10 cores simultaneously, which means workloads will ping-pong between cores based on both the workload characteristics and which CPU cores are hitting thermal trip points.

Finally, there’s just not much software on mobile devices that can take advantage of four cores, to say nothing of ten. Even modern desktops, which at least support a range of professional applications that can use eight to 16 cores, haven’t moved beyond quad-core support for most consumer applications. The additional performance typically doesn’t justify the cost and expense of multi-threading existing code bases.

The other features of the MediaTek Helio x20 are quite competitive, but it’s the CPU specs and capabilities that the company will lead with on marketing. This is what happens when marketing runs the show. We’ve heard before that the Chinese market is crazy for core counts, which means slapping 10 chips in a single die is likely to sell. Whether that results in a better customer experience is another question altogether.