

I am a professional computer engineer, I have known the microprocessor from its start.

I have had the curiosity of having a look at the Apollo guidance computer which has been made public.

I have read the operator's manual documentation, and it's really the weirdest I have ever seen, so weird that it makes my hair raise on my head when I read it (and I have read many technical documentations).

The program of the CM is very weird too; I strongly doubt it piloted anything; it could not even be compiled, that is transformed into machine code to be executed.



If I summarize some of the main problems if the Apollo computer, before I discuss them more in detail, I can cite the following points:



- The Apollo computer uses a technique of switchable memory which is absurd since it doesn't use the full capability of the addressing system, and leads to wasting time and memory which are very limited in the Apollo computer; and switching executable program memory makes no sense, because it means that the instructions which follow the switching instruction will never be executed.



- The Apollo computer doesn't have the mininal basic set of instructions that any processor usually has, and has instead instructions which are weird and impractical to use.



- The Apollo computer does useless things which waste processor time (like saving the contents of the instruction following the call to a subroutine moreover saving its address which is the only thing which should be saved).



- The Apollo computer provides instructions which compute something so weird in the accumulator (main register of a processor) that it's equivalent to destroying its contents, and thus makes these instructions unusable.



- The Apollo computer has instructions which don't require a parameter which should yet be necessary for these instructions to work properly, or conversely which require a parameter which is useless for the way they work.



- The Apollo computer has instructions which are unclear; they don't really specify what they do.



- The Apollo computer is said to be able to do real time (real time allows several tasks to run simultaneously) and yet it doesn't even have the minimum environment which would be necessary for the real time to work (no stack, and no instruction to manage real time).



- The Apollo computer has instructions which uselessly waste processor time (like the "unprogrammed instructions" which count hardware pulses; such instructions have never existed on any processor for the good reason that they make no sense).



- Anything which runs on the processor comes from programmed instructions, so the fact that something would steal time from the computer, like they say, is hilarious...unless a programmer would have programmed something and wouldn't have told the others, LOL!



- The Apollo computer uses the one's complement system (which makes a distinction between +0 and -0, and is less performant than the two's complement system), although this system was already obsolete in the time of Apollo.

The chapter III specifically deals about this subject.



I) Criticism of the operator's manual.

II) Criticism of the CM program.

III) The strange guidance equations

IV) The incoherent choice of the system of binary representation

V) The management of tasks in the computer of Apollo

VI) The memory of the computer of Apollo

exactly the same size and the same top left position

This chapter deals about the core rope memory which supposedly contained the software which allowed the lunar module to land on the moon.Nowadays, the memory of the computer is contained in integrated chips.This one is already quite old, the current ones are smaller and contain more memory, but relatively to the memory which was available in the time of Apollo, it is revolutionary and super concentrated.This type of memory is called "RAM" memory (for "Random access memory"), which means that it is possible both to write into and read from it.But this type of memory also loses its contents when it is powered off.This type of memory is called "ROM" ("Read only memory") or "PROM" (for "Programmable read only memory), and unlike the previous one, it can only be read and not written.But it has the advantage over the previous one not to lose its contents when it is powered off.This type of memory is used when it must contain a fixed program which must always remain in it, and allows the computer to start when it is powered on.It is also possible to plug such chips if the computer must do a given task when powered on, this task being programmed in the chip.The PROM are programmed with a special device; the programmer starts a program which commands the PROM programmer, and the user inputs his program; the burning program then sends the user's program to the PROM programmer which burns the instructions into the PROM, so that it definitively contains these instructions.the programmed PROM will always contains these instructions, whether the computer is on of off (but it can't be dynamically written, unlike a RAM).There also are specials PROM chis called EPROMS (for Erasable PROMS) which can't be written several times, though not dynamically.In order to rewrite an EPROM, its contents must first be erased; in order to do that, the EPROM has a sort of little "window" that the UV light can go through and which allows the UV light to erase the contents of the EPROM.When an EPROM has to be reprogrammed, it is put into a special device which sends UV rays through the window of the EPROM; after some time of exposition, the contents of the EPROM is erased, and it can be programmed again the same way as a normal PROM, with the PROM programmer.Of course, it is not as fast as writing into a RAM, which is immediate, but it allows to reuse several times the EPROM unlike with the ROM, whereas the EPROM can keep its program when it is off like the ROM and unlike the RAM memory.So, it is more economical than using a ROM, if the resident program has to be modified several times.In the fifties, sixties, and seventies (at least the beginning of the seventies), the microchips were not existing.The computers were all big machines which were not affordable to common people and that only industries could afford.The memory of these computers are consisting in arrays of ferrite cores; each core was representing a bit of memory; it gives you an idea of the number of such cores which were needed to have an important amount of memory (though these computers didn't have as much memory as the modern micro-computers).In that time, there was no dead memory which was keeping information when it was not powered because there was no need for it.When a computer was started, the operating system was first read from magnetic tapes, and stored into the core memory reserved for it.Then the users were giving their programs on punch cards (one instruction per punch card, which means that your program had as many punch cards as it had instructions), and the operator was introducing the bunches of punch cards into a special reader which was decoding them and sending them to the processor which was storing the instructions into the core memory.These programs were using data which were also stored and modified in the core memory.Planes might have needed dead memory for the computer if embarked computers had been existing at that time, but the computers were still not compact enough to be embarked on planes; so the planes were using analog calculators which were fit for guiding the planes of that time, even if they could not have been used to manage your budget or play with video games.So, how was the core memory working?The cores were put at the intersection of rows and columns of a matrix of wires; there were two perpendicular wires going through each core.The magnetic field of the core could be modified if each of the wires crossing in it was fed with a half current, for the sum of these two half currents was making a full current which was allowing the magnetic field of that core to be modified.On the other hand, if only one wire was fed with a half current and not the other one, this half current alone was not enough to change the magnetic field of the core.On the schema which is shown, only the central core is crossed with two wires fed with a half current, and it is the only one which will have its magnetic field modified.The other cores have only one wire fed with a half current and the other wire has no current going through it, so their magnetic field will not be modified.This process allows to specifically target the core which is to be modified (or read).When the two crossing wires are fed with a negative current, the ferrite core is polarized negatively, and conversely, when the two crossing wires are fed with a positive current, the ferrite core is polarized positively.The fact that the ferrite core is polarized negatively corresponds to a bit set to zero, and the fact that it is polarized positively corresponds to a bit set to one.When the core is already polarized negatively, and negative currents are sent through the crossing wires, the magnetic field of the core will remain unchanged; a sense wire which goes through the core will then detect nothing; the computer then knows that a zero was stored on this core.On the other hand, when the core is currently polarized positively and negative currents are sent through the crossing wires, the magnetic field of the ferrite core will change, and this change creates a short impulsion through the sense wire; though this impulsion is very short, the electronics is fast enough to detect it; it is the detection of this impulsion which says that the ferrite core was polarized positively before the currents were sent through the wires; the computer then knows that a one was stored in this core.The problem of the reading is that it is always made by sending a negative current through the crossing wires, and thence the core will always be polarized negatively after it has been read, even if it was polarized positively previous to the reading; that means that, if an impulsion has been detected in the sense wire, positive currents must then be sent through the crossing wires so that the core returns to it previous state corresponding to the one it was memorizing (otherwise, next time a zero would be read instead of a one).If may seem a little complicated explained that way, but in fact this process is extremely fast and allows to read the memory with a quite high speed.So the cores are inserted into an array of wires, and these wires are commanded with circuits of which the schema is represented on the right; this circuit can send either a negative current (for reading the cores) or a positive current (for reprogramming the ones of the cores which have been detected to a one); the negative or positive current will only be sent if an enable signal allows it; this enable signal depends on the current memory address which is to be read or rewritten.So, you can see that the principle of the core memory lays on a dynamic change of the magnetic field.When the core memory is switched off, it is always deprogrammed, and cannot hold information; when it is switched on, the cores must first initially be polarized positively or negatively by sending either positive or negative currents, according to the fact that the cores must memorize a one or a zero.And when a memory data is to be modified, the crossing wires of the cores corresponding to the ones of this data must be fed with positive currents (unless they already were positively polarized), and conversely the crossing wires of the cores corresponding to the zeroes of this data must be fed with negative currents (unless they already were negatively polarized).In the normal core memory, you can see that the activation wires passing through the cores have a quite important diameter relatively to the core.Indeed, they must be able to carry a sufficient current to change the magnetic field of the core, and, if they were too thin, they would not be able to stand this current.In the Wikipedia's article, they say that each half current was between 0.4 and 0.8 ampere (two half currents must be sent to change the magnetic field of the core, one is not enough); if it is a single wire which must change the magnetic field of the core, this current must be doubled; it would then be between 0.8 and 1.6 ampere.Concerning the sense wires, they can be thinner, for the impulsion they get is relatively weak.So, how was the "rope core memory" of Apollo working?They were making the sense wires go through cores or over them; when a sense wire was going through a core, it was supposed to represent a one, and when it was going over instead of going through, it was supposed to represent a zero!Up to 64 sense wires could go through a core!I have found a documentation on the site of the NASA explaining how the core rope memory of Apollo and the erasable memory too were working.First I have to give some explanation about the diode and the transistor, for I'll refer to these explanations in what follows.A diode is a device which lets the current pass into one direction and blocks it in the other direction; and in the direction it lets the current pass, the diode behaves like a resistor of almost null value.A transistor is a more sophisticated device which has three electrodes called the base (the electrode on the left), the emitter (the electrode with an arrow) and the collector (the top one).The particularity of a transistor is that a small variation between the base and the emitted yields a bigger variation between the collector and the emitter; this particularity allows to use the transistor as an amplifier.A transistor can also be used to block or allow a current between the collector and the emitter with a command inputted on the base of the transistor.There are two types of transistors:- In the transistors called "NPN" the current goes from the collector to emitter; these transistors are represented with the arrow of the emitter oriented toward the exterior of the transistor.- In the transistors called "PNP" the current goes from the emitter to the collector; these transistors are represented with the arrow of the emitter oriented toward the interior of the transistor.When the transistor is connected so that a current can go from the base to the emitter, the current can go from the collector to the emitter (or from the emitter to the collector in the case of a PNP); the transistor if then unblocked.But, when the transistor is connected so that no current can go from the base to the emitter, the current cannot go from the commector to the emitter (or vice versa in the case of a PNP); the transistor is then blocked.Now this is the the simplified schematics they give for explaining how the core rope memory of Apollo works.In order to test which cores a sense line is passing through, and which cores it is bypassing, it is not possible to activate several cores in the same time.Indeed, if two cores a sense line is passing through are activated simultaneously, the sense line will receive an impulsion, but it will not be possible to know if the sense line is going through the first of these two cores, or the second one, or both, because, whether only the first core generates an impulsion, or the second does, or both do, in all these cases the same impulsion, standing for a 1, will be generated in the sense wire.On the other hand, if the sense wire receives no impulsion, then it can be sure that it is passing through none of these cores, and so that zeroes are programmed on these cores for this sense wire.The only solution to test the bits on a sense line is to activate the cores one at a time (but when a core is activated, all the sense lines can simultaneously be tested for this core).If the only the second core is activated, if a sense line sees an impulsion, then it can be sure it is going through this core; and if it sees no impulsion, it can be sure it is bypassing this core.Likewise,if the only the third core is activated, if a sense line sees an impulsion, then it can be sure it is going through this core; and if it sees no impulsion, it can be sure it is bypassing this core.When successively activating the second core and the third core, the second line receives an impulsion in both cases, and it thence knows with certainly it has a 1 programmed on these two cores.So, how to activate cores independently, so that only one can be activated at a time?The most logical way is to make each activate line pass through a single core, one per core.There are two possible ways:1) the way described on the upper half of the figureA set current (left of the figure) in one direction is first sent into the activate line, changing the magnetic field of the core.Then a reset current (right on the figure) in opposite direction is sent into the activate line to reset the magnetic field of the core back to its original state.This double change of the magnetic field of the core generates an impulsion into a sense line which goes through the core (and, if the sense line bypasses the core, it will see no impulsion).2) The way described on the lower half of the figure.A set current (left of the figure) in one direction is first sent into the activate line, changing the magnetic field of the core.Then a reset current (right on the figure) in opposite direction is sent, not into the activate line, but into a common reset line to reset the magnetic field of the core back to its original state.This double change of the magnetic field of the core also generates an impulsion into a sense line which goes through the core.In this mode, only set currents are sent into the activate lines, and only the common reset line resets the cores.But, curiously, they have not chosen this natural mode to activate the cores.The lines which allow to select which core is activated are not "Activate lines", but "Inhibit lines", and they work in a converse way: They don't allow to activate a core, but to the contrary to prevent the activation of a core.On my examples, the bottom wire going through a core is an inhibit line, the central wire is a common set/reset line which goes through all the cores, and the upper thinner wire is a sense wire.1) The processus of activation of a core is described on the upper half of the figure.A set current (left of the figure) in one direction is first sent into the common set/reset line, changing the magnetic field of the core.Then a reset current (right on the figure) in opposite direction is sent into the common set/reset line, resetting the magnetic field of the core back to its original state.This double change of the magnetic field of the core generates an impulsion into a sense line which goes through the core (and, if the sense line bypasses the core, it will see no impulsion).2) in case that a core must not be activated because it is not currently the tested core, the processus of inhibition of the activation of the core is described on the lower half of the figure.The set current (left of the figure) in one direction is sent into the common set/reset line, but a reset current in opposite direction is simultaneously sent into an inhibit line going through the core.The set current and the reset current are of equal intensity, and, as they are opposed to each other, they are going to cancel each other; because of the reset current going through the inhibit line, the set current of the common set/reset line cannot change the magnetic field of the core, and thence no impulsion will be generated by this core in a sense line passing through this core.The reset current (right on the figure) is then sent into the common set/reset line, but, as the magnetic field has not been changed because of the inhibition, the core will not react to this reset.So, in order to activate a single core, no current must be sent into the inhibit line(s) passing through this core, and, in all the other cores, there must be (at least) an inhibit line that a reset current is passing through.(note too that the fact that currents are sent into two wires must not be compared with the currents sent into two wires in the normal core memory: In the normal core memory, it is two half currents complementing each other, and here it is two full currents cancelling each other).So, the concept of the inhibit lines seems less obvious to use than the one of the activation lines, but it seems to work anyway.Yet this concept creates big problems that we are going to see.I have colored with different colors the four inhibit lines which allow to select or inhibit the cores.You can see that each of these inhibit lines goes through two cores.The third activation line goes through the second and fourth cores.If a reset current is sent into this line only, the set current going through the common set/reset line will activate the first and third cores, for only the second and fourth are inhibited from changing the magnetic field of the core.If we want only the first core to be activated, then reset currents must be sent both through the third and fourth inhibit lines.Notice that these lines both go through the fourth core; that means that two reset currents instead of one will be sent through this core.The process of reading of the bits programmed on the cores for the 16 sense lines is described in this demonstration.Reset currents are first sent into the third and fourth inhibit lines when the set current is sent into the common set/reset line so that only the first core is activated.As only the first sense line is going through the first core, but neither the second sense line nor the 16th sense line (the other sense lines are not specified), only the first sense line has a 1 programmed on this core while the other sense lines have a 0 programmed on this core.So, for the first core, we have the combination "10...0" (starting from the first sense line).Then a reset current is sent through the second and fourth inhibit lines, causing the inhibition of all the cores save the second one, which is the currently tested one.As only the second sense line is going through the second core, it is the only one which will get an impulsion.So, for the second core, we have the combination "01...0".Then a reset current is sent through the first and third inhibit lines, causing the inhibition of all the cores save the third one, which is the currently tested one.As the second and 16th sense lines are going through the third core, it is these two ones which will get an impulsion.So, for the third core, we have the combination "01...1".Then a reset current is sent through the first and second inhibit lines, causing the inhibition of all the cores save the fourth one, which is the currently tested one.As only the first sense line is going through the fourth core, it is the only one which will get an impulsion.So, for the fourth core, we have the combination "10...0".So, by successively activating one core at a time, it is possible to read the bits which have been programmed on the sense wires by making them either go through a core (for a 1) or bypass a core (for a 0).With these 4 cores and 16 sense lines, it is possible to memorize 4*16=64 bits.Notice however that we have had to send two reset currents at each step of the process (and that there is a core which receives two reset currents instead of one).Another solution would be to make each inhibit line go through all the cores save one, so through 3 cores in this simplified example..The first inhibit line goes through the second, third and fourth cores, but not the first one; so sending a reset current into it will inhibit the activation of all the cores save the first one..The second inhibit line goes through the first, third and fourth cores, but not the second one; so sending a reset current into it will inhibit the activation of all the cores save the second one..The third inhibit line goes through the first, second, and fourth cores, but not the third one; so sending a reset current into it will inhibit the activation of all the cores save the third one..The fourth inhibit line goes through the first, second, and third cores, but not the fourth one; so sending a reset current into it will inhibit the activation of all the cores save the fourth one.So now we just have to send one single inhibit current to test each core...but we have to make pass through each core a number of inhibit wires equal to the number of cores minus one (3 in our example of 4 cores).We'll thence have to look for another solution.Another solution is to make pass a single inhibit line through each core:. The first inhibit line will go only through the first core and will only allow to inhibit the first core.. The second inhibit line will go only through the second core and will only allow to inhibit the second core....So, in this solution, only one inhibit line goes through a core, and it solves the number of inhibit lines going through a core.But, when a core is to be activated, all the other cores must be inhibited, which means that reset currents must be sent into all the inhibit lines save the inhibit lines going through the currently tested core.Even if the management of the memory is made with separate units of which they show the schema, that still makes three currents which must be sent to read a core when one would have been enough if activate lines had been used instead of inhibit lines.So, why not use the normal concept of "Activate wires" instead of "Inhibit wires"?In the concept of "Activate wires", only one Set current is sent into an activate line when a core is tested, and only one activate line goes through a core.No problem of multiple lines going through a core and no waste of energy.This shows that using the concept of "Inhibit wires" to alternately activate the cores which are tested makes no sense, and that the concept of "activate lines" is the only reasonable concept which can work.In fact, they could have activated the core which is to be tested the same way as in the conventional core memory: By sending half currents in lines and columns of a matrix of wires, so that the core which is tested is at the intersection of the line and column into which half currents are currently sent.But the fact that they have illogically used "Inhibit lines" instead of "Activate lines" is not the only problem of the ROM card.This schema shows how the impulsion generated by the cores was read.There were commands to activate the reading of the impulsions generated by the cores individually.In order to select the sense line which was to generate an impulsion on the output coil (circled in blue), they were using line selection and module selection commands; for instance, on this schema, the only sense line of the four which can generate its impulsion into the coil is the one framed in light green, because it is the only one connected to both a selected line (represented in dark green) and a selected module (also represented in dark green); the three other ones, framed in light red, cannot generate their impulsion into the coil, for they are connected either to a non-selected line (represented in dark red) or a non-selected module (represented in dark red too), or even to both.I give some explanations about the way the sense current was transmitted to the coil.- I call VR the reference voltage of 14 Volts.- I call R the value of the resistors- I call I1 the intensity which comes from the line selection.- I call I2 the intensity which goes through the diode D4 (which comes from the right).- I call V the voltage of the common point I have circled in red.The intensity which goes to the module selection point is equal to the sum of I1 and I2.So V:- Is equal to R*(I1+I2)- Is also equal to VR-0.7-R*I1- And also equal to VR-0.7-R*I2(0.7 being the voltage between the ends of the diodes)so we have the two equations:R*(I1+I2)=VR-0.7-R*I1R*(I1+I2)=VR-0.7-R*I2Solving these equations gives:I2=(VR-0.7)/(3*R)When the sense line generates a current I'll call i, this current also goes through the resistor which is connected to the module selection point.So, now we have: V=R*(I1+i+I2)And the equations become:R*(I1+I2+i)=VR-0.7-R*I1R*(I1+I2+i)=VR-0.7-R*I2Solving this equation gives this result:I2=(VR-0.7)/(3*R)-i/3So a variation equal to i/3 relatively to the previous value.That means that only one third of the very weak impulsion in the sense line comes to the coil!48 selected sense wires may potentially have a current going through, and, as the current of the selected sense wire is divided by three before coming to the primary of the coil of the amplifier, it makes a too weak current to be amplified.The impulsion detected in the sense line is amplified to be used by a circuit of which the schematics is shown here.We have seen that the impulsion in the coil is only one third of the impulstion in the sense line.Now we are going to see that this very weak impulsion was even incorrectly amplified.This amplifier uses two pairs of transistors; this special assembly is called a "push-pull"; it means that the first coupled pair of transistors (circled in green) amplifies the positive edge of the impulsion (colored in green), and the second coupled pair of transistors (circled in blue) amplifies the other edge of the impulsion (colored in blue).I show here a simple amplifier made with a transistor.The signal to amplify is sent on the base of the transistor (the connection which is on the center of the transistor), and the amplified signal is obtained on the collector of the transistor.On the first pair of the push-pull (transistors circled in green), the collector of the first transistor of the pair is connected on the base of the second transistor; it is the connection I have drawn in red.But, on the second pair of the push-pull (transistors cicled in blue), the collector of the first transistor should also be connected to the base of the second transistor...but it is not the case, the connection between the collector of the first blue transistor and the base of the second blue transistor is missing; I have circled the place at which this missing connection should be visible...and is not.As there is no connection between the two transistors of the second pair of the push-pull, it means that the second edge of the sense impulsion cannot be amplified.This omission is clearly intended as a clue of the fakery.The missing connection between the base and the collector is certainly not accidental, for this mistake exists in two different schemas, one in a document dated 1966, and the other one dated 1972.In an article published in 1967, Hopkins shows the schema of the amplifier, and, on this schema, the bug of the missing correction has been corrected; as the article of Hopkins has been published between the dates of the two documents in which the error exists, it shows that the argument that there might have been a decision of adding this connection or removing it does not hold.Hopkins corrected this mistake to attract the attention, to show that something was abnormal.However, Hopkins left the error of the incorrectly mounted output transistor.About the incorrectly mounted output transistor, I initially thought that the strobe controlling the output was intended as an anomaly.This would have been true on the prototype card, which had up to 64 sense wires passing through the cores.Indeed, as there are 16 bits to simultaneously read, that would make 64/16=4 sense wires per bit.As the sense line selection was allowing to select one in four sense lines, it then means that the selected sense line would have represented one bit of the 16 bits word to read.And the diagram to read a bit of the 16 bits word to read would have looked like this.The sense line selection would have selected one of the four sense lines of the bit, the amplifier would have amplified it, and the output of the amplifier would directly have been a bit of the word.So, for the prototype card, the strobe would indeed have been useless, and its presence an anomaly.But, in the final core rope modules, it is not 64, but 192 wires which could pass through a core, three times more than for the prototype card.That could make 192/16=12 sense lines for a bit.It means that what the sense line selection was selecting was not representing a bit, but one in three possibilities for the bit.For the sense line selection to select a sense line directly corresponding to a bit, it should have been able to select one in 12 lines.Furthermore, as I have previously demonstrated, the sense line selection was reducing the current of the selected sense line to a third before it was coming to the amplifier.For the final core rope module, the diagram for the acquisition of a bit of the 16 bits word would have looked like this.There would have been three sense line selection modules; each of these sense line selection modules would have selected one in 4 sense lines; each output of a sense line selection module would have come into an amplifier which would have amplified it, but only one amplifier's output would have been taken into account to represent the final bit, and the two other amplifier's outputs ignored, although they also were amplifying a selected sense line.So, for the final core cope module, the strobe finally has a meaning: It was allowing to specify if this amplifier's output would be taken into account to represent the read bit, or ignored.But, if the strobe is not finally an anomaly, the output transistor is still incorrectly connected.It is in fact upside down.When a NPN transistor (emitter's arrow oriented outward) is used to validate or invalidate a signal by controlling its base, its emitter is connected to a steady reference, generally the ground; here, it is not the case, for the emitter is connected to the amplifier stage's output, of which the voltage changes when it amplifies a pulse.And, when the transistor's base would be grounded, and the amplifier's stage was not ampliying a pulse, it would have a negative voltage relatively to the emitter connected to the +14V, and it is not good for the transistor.This is the way the output transistor should have been connected, with its emitter connected to the ground.When the base of the transistor is activated, the output transistor would conduct, forcing the collector to the ground, and the final amplifier's output would then not follow the output of the amplifier stage, which means that it would not be selected to output the bit.And, when the base would be grounded, the transistor's collector would then follow the output of the amplifier stage, which means that it would then be selected to output the bit.This simplified schema shows how the three amplifiers would be connected, so that only the output of one of them would be selected to output the bit.The outputs of the amplifiers would be inputted to a NOR gate; a NOR gate outputs a 1 when all its inputs are 0, and a 0 otherwise.For two of the amplifiers, the ones which are not selected, the strobes would be activated, which would force their outputs to 0, and, for the third one, the one which is selected, the strobe would be grounded, allowing its output to follow the output of the amplifier's stage; when there is no pulse, this output would be 1, forcing the bit output to 0.And, when a pulse would occur, the output of the amplifier's stage would be pulled down by the pulse, and the amplifier's output would become 0, which would force the output bit to 1.So, if the missing connection between the base and the collector in the amplifier's stage is restored, and if the output transistor is correctly connected, does it mean that this amplifier would be correctly working?In fact, there still is another problem, though it is less visible.This is the schema of the selection of a sense line, and its amplification, in a patent of core rope memory of a printer, which memorizes the dot matrix for a character to be printed.The cores, which represent lines of the dot matrix, are successively activated, and the sense lines, representing the columns of the dot matrix, are successively selected and amplified to print a dot of the character.About this amplifier, the patent says that it does not only amplify the pulse, but alsoit.A pulse stretcher is an interface which allows to make a pulse longer, in order to exploit it more easily, to leave the time to read it.Now, look: The part I have framed in red on printer's bit amplifier is called a RC circuit (with a resistor and a capacitor), and it allows to convert the pulse on the secondary of the transformer into a temporary permanent current, which then can be read by the reading logic.After the bit was read, the state of the input I have circled in blue was changed, in order to discharge the capacitor, and allow the reading of the next bit.In the AGC's bit amplifier, this circuit is absent, which means that the pulse is not memorized on the secondary of the transformer, and all the transformer does is to transmit the pulse to the amplifier without memorizing it, and, as such, it is useless.If the pulse is not memorized, it cannot be read by the reading logic, for it passes too fast.Now, why would the sense pulse need to be stretched?For the bit interface to correctly acquire the bit from the sense pulse, there are two conditions:1) The sense pulse must already be activated when it is read.2) The sense pulse must still be activated when it is read.If the bit was acquired exactly at the same time as the core is activated, it would not be acquired correctly for the sense pulse would not still be present.That's why the process of the bit reading is made in three steps sequenced by timing:1) Activation of the core2) reading of the sense pulse3) ResetHowever, there is no guarantee that the pulse will still be active when the bit is acquired at the second step, in which case it would be read 0 whereas the pulse actually occurred.That's why the pulse is stretched by the amplifier, so that the amplified pulse is certain to be present when it is acquired at the second step.The reset at the third step cuts the stretched pulse moreover resetting the core.So, how would the interface of a bit have worked, supposing all the flaws I showed would have allowed it to work?There are 12 possible sense lines for a bit, but, for a given address, only one of these sense lines is to be taken into account.Let's suppose the first one has to be taken into account to output the corresponding bit.The first sense line selection module must select the first sense line; as the selection lines are inputted into the three selection modules, the two other selection modules also select the first line, but it is not relevant in fact, for their amplified outputs will not be taken into account.The strobes are programmed so that it is the output of the first amplifier which is taken into account; finally the output bit corresponds to the first of the 12 sense lines associated with this bit.Let's now suppose that it is the second of the 12 sense lines associated with the bit which is to represent the bit.The first sense line selection module must now select its second input, and the strobes are still programmed so that it is the output of the first amplifier which is taken into account; finally the output bit corresponds to the second of the 12 sense lines associated with the bit.Let's now suppose that it is the fifth of the 12 sense lines associated with the bit which is to represent the bit.The second sense line selection module must select its first input, and the strobes must be programmed so that it is the output of the second amplifier which is taken into account; finally the output bit corresponds to the fifth of the 12 sense lines associated with the bit.Let's now suppose that it is the sixth of the 12 sense lines associated wit the bit which is to represent the bit.The second sense line selection module must select its second input, and the strobes must be programmed so that it is the output of the second amplifier which is taken into account; finally the output bit corresponds to the sixth of the 12 sense lines associated with the bit.I don't think I have to give more examples: Selecting a sense line is done by making a double selection: selecting a sense line selection's input, and selecting an amplifier's output.But, is this the best way for a bit's interface to work (ignoring the flaws of the amplifiers)?I have only represented two commands to control the sense line selection block, for there only are four possible combinations to select one in four sense lines.It means that each input is inputted twice in the control of the selection interface; once non inverted, and once inverted.Now, it would be possible to control the sense line selection interface with four independent commands.It would allow to select several sense lines in the sense time, which does not offer the least interest, but it would also allow to select none of them, which means that no current would go from the sense line selection interface to the corresponding amplifier, and this is more interesting on the other hand.This might be interesting, for there would be no reason that a current would run through a sense line, and would be ampified, if the amplifier's output is not taken into account to generate the bit.But, in this case, it would mean that the strobes would be unnecessary.Indeed, since the corresponding amplifiers receive no pulse, their outputs will remain to 1, which means that the outputs of the amplifiers can directly be connected to a NAND gate, without being controlled by a strobe.The amplifier which receives a pulse, will amplify it and will output a 0, which will force the NAND's output to a 1.And, if the selected sense wire gets no pulse (i.e. does not pass through the activated core), the corresponding amplifier will output a 1, which will generate a 0 on the NAND's output, since the outputs of the other amplifiers remain to 1, as they receive no pulse, the output of their sense line selection interface being disabled.In short, it means that, if the sense line selection interfaces could be controlled so that they would select no sense line at all, the strobe which controls the amplifier's output would become useless, and the amplifier could be simplified as I show.But the strobe which controls the amplifier's output is here, and its presence proves that the engineers had excluded the possibility that the sense line selection interfaces could be controlled to select no sense line at all.Now, let's consider again the selection and amplification of the sense lines of the printer's interface (and we can assume it has worked, it has not gone on the moon, it had no reason to cheat).Look how the selection was done: the selection commands (C1 to C5) were inputtted on the middle of resistors bridges, and the sense lines were arriving on the extremities of these resistors bridges; they were connected to the primary of a transformer through diodes; a sense line was selected by activating its command line, while the other command lines were grounded; only the sense line of which the command line was activated had a current running through it, provided that it was going through the currently activated core, and it is its current which was running through the primary of the transformer,, and amplified and stretched by the amplifier which follows.This printer's interface shows how the selection of the sense lines should have been made: There should have been an unique transformer, and as many resistors bridges as sense lines associated to the bit (12), as many command lines as sense lines to select; only one command would have been activated at a time, allowing a current to run through its associated sense line when it was passing through the activated core, and the current of the selected sense line would have run through the primary of the transformer without reduction; all the other 11 sense lines would not have had a current running through them, for their command lines would have been grounded; notice the capacitor connected on the secondary of the transformer, which allows to maintain the pulse after it has disappeared on the primary, and which leaves the time to read it; this capacitor is missing on the memory of Apollo.For instance, if it is the first sense line which is to be read for the bit, only the first command line would be activated, and all the other ones grounded; the current of the first sense line would run through the transformer, entirely, without reduction, and would be correctly amplified and stretched by the unique amplifier of the bit, and the unique amplifier for the bit would have output a memorized bit, without a strobe being necessary.And, likewise, if it is the second sense line which is to be read for the bit, only the second command line would be activated, and all the other ones grounded; the current of the second sense line would entirely run through the transformer, and would be correctly amplified and stretched by the unique amplifier of the bit.So, this is definitively the way the bit's interface should have worked, provided that we keep the logic of using sense lines for programming the bits.On one side, we have three sense line selection modules, reducing to a third the current of the selected sense line, and allowing three currents to run through three selected sense lines, three amplifiers, consuming currents, incorrectly amplifying the pulse, not stretching it, and incorrectly strobed, and, on the other side, we have an unique selected sense line, which is the only one which has a current passing through, which is not reduced before coming to the amplifier, which is correctly amplified and stretched by an unique amplifier which directly outputs the bit.No use to tell you which is the best of the two; If you are not completely stupid, you must be able to figure out!And selecting the sense line for the bit does not require more bits from the address bus for the improved interface than for the AGC interface.Indeed, selecting the command among the 12 possible ones for the improved interface would be made with a circuit called "1 of N decoder"; it is a circuit which accepts a combination of n binary inputs and outputs 2^n outputs(Two n times multipled by itself), of which only one is activated at a time, which corresponds to the binary combination of the inputs; the displayed example shows how to validate one of the four outputs according to the binary combination of the two inputs.Rather than showing a complete schema for a decoder having 4 inputs and 16 outputs, which would be a little overloaded to be legible, I show here an animation which shows how each gate of the decoder would be connected to the four inputs.This decoder would allow to select one of the 12 commands of the improved bit interface from a 4 bit address.It is not necessary to repeat this decoder for the 16 bits, the same decoder could be used for all the bit interfaces.And concerning the bit interface of the AGC, a two bit address would be needed to select one sense line out of 4 ones, and another two bit address would be needed to select one of the three amplifier's outputs, which would also make a four bit address at total.It means that the improved bit interface does not mean more bits to be controlled from the address bus than the AGC bit interface.Moreover, the inhibit lines were not even used correctly; the way they were used, there were two inhibit currents passing through a core.If they had been used correctly, then only one inhibit line would have passed through each core, and would have been activated to inhibit this core, like it was made in the printer's memory, which actually works.Moreover the fact that the inhibition process is incorrect (because of two activated inhibit lines passing through a core), using the inhibit wires like it was made in the memory of Apollo also implies that the inhibit wires also had to be woven to alternately go through or bypass the cores.And we are going to see that it complicates the weaving test.Let's consider the sense wire 2, I indicated with a blue arrow.This wire bypasses the first core (when it is correctly woven), because a 0 is programmed for this sense wire on the first core.So, when a current is sent into the common set line (wire colored in green), and counter-currents are sent into the third and fourth inhibit lines, as these inhibit lines pass through all the cores save the first one, they will prevent all the cores from being activated by the current of the common set line, save the first core which will thus be the only one to be activated.If the sense line 2 bypasses the first core, like it should, it will then show no current, showing that a 0 is programmed for this sense line on the first core; the detection of no current in the sense wire 2 will show it has been correctly woven.Now, let's consider this situation.The sense wire 2 (indicated with a blue arrow), instead of bypassing the first core, passes through it instead, because a gentle weaving hand has made a mistake.The result is that, when the first core is activated (by sending a current into the common set line, and counter-currents into the third and fourth inhibit lines), it will show a current, when it should not.The engineers will then deduce that a gentle weaving hand has made this sense wire pass through the first core, when it should have bypassed it, and will have the faulty sense wire removed and woven again.Now, let's consider this situation instead.The sense wire 2 (indicated with a blue arrow) has been correctly woven, and bypasses the first core like it should.But the third inhibit line (pointed by a pink arrow), instead of passing through the second core, bypasses it.The result is that, when a current is sent through the common set line, and counter-currents through the third and fourth inhibit lines, there will be no activated inhibit line passing through the second core, and thence the second core will be activated in the same time as the first core, when it should not.As the sense wire 2 passes through the second core, and that the second core is incorrectly activated, the sense wire 2 will be activated, not because the first core is activated, but because the second one is.If the engineers think that the inhibit wires are correctly woven, they will deduce that the sense wire 2 has been incorrectly woven, that it passes through the first core when it should bypass it, and will have it rewoven, whereas it is correctly woven in fact, for it does bypass the first core, exactly like it should.So reweaving the sense wire will not solve the situation.So, does this mean that, if the bit interface had looked like this, it could have worked normally, and that it is the way it should have been conceived?There is however a big difference with the printer's memory we have seen: In this printer's memory, the selection is made betweenthe sense lines which can pass through the cores; it means that there will never be more than one sense line that a current is passing through.In this bit's interface, there is only one current passing through the selected sense line of the bit, but there are 16 bits to read for the word to be read, which means that there are 15 other currents which can run through the 15 other selected sense lines corresponding to the 15 other bits (provided of course that they go through the activated core, which can happen).So, if this interface is used, it still means that there may be 16 currents running through selected sense lines (in the original interface of the AGC, it is 48), and 16 is too much, it implies a consistent reduction of current running into each of these selected sense lines (provided of course that they all go through the activated core, which may happen).It means that, although this interface is much more performant than the one of the AGC, it still has a severe deficiency to work correctly.That's why the core rope memories of other computers than the AGC, like the one of the UNIVAC (right on the stereoscopic view), although they show a similarity with the core rope memory of the AGC, work in a completely different way.Indeed, in these memories, the lines, which pass through or bypass the cores, are notlines, butlines instead, and that changes everything.In these memories, the cores have an unique sense wire.Indeed, the text associated with this figure, in the patent of a core rope memory for a computer, is as follows:"When the magnetic easy axis of the magnetic thin-film wire 1 is in the circumferential direction thereof, the magnetic thin-film wires 1 are used as information lines (which function doubly as digit lines and sense lines), and the conductor wires 2 are used as word drive lines."In the memory of the AGC, only one core is activated at a time, and currents can go through several sense lines, and, in the core rope memories which actually work, only one drive line is activated at a time, and several cores may be activated by this drive line at a time, generating a current into each of their unique sense lines.Instead of being read on an unique core, the bits are read on several cores.With the same number of drive lines as sense lines, and the same number of cores, these memories can memorize the same number of bits, for, the same that a sense line programs a bit by passing through or bypassing a core, a drive line also programs a bit by passing through or bypassing a core.So, if the core rope memory of the AGC was working according to the same principle as the core rope memories of other computers, which are proven to work, the schematics would be changed as I show here; the lines passing through or bypassing the cores would be labeled as, and not, and there would be no inhibit lines, which means that the latter would not have to be woven in the cores,I explain here how it would work: The first drive line passes through the first and fourth cores, which means, that, when it is activated, the first and fourth cores would be activated, and their sense lines detecting a current, which would correspond to the four bit word 1001.The second drive line passes through the second and third cores, which means, that, when it is activated, the second and third cores could be activated, and their sense lines detecting a current, which would correspond to the four bit word 0110.Finally the third drive line passes through the third core, which means that, when it is activated, the third core could be activated, and its sense line detecting a current, which would correspond to the four bit word 0010.This demonstration has been made with four cores, but the number of cores for reading a 16 bits word would in fact be extended to 16, in order to read the sixteen bits of the word.So, you can see that this way of working is much better:1) No need of inhibit lines2) Only one current running into a sense line, which means that the current running through it would be consistent enough to be amplified.So, this interface is much better than......this one, which itself is much better than......the one which has been conceived for the AGC.This interface is so bad, it accumulates so many handicaps, that it has absolutely no chance to work, and the engineers knew it, for they wanted it to be extremely bad, and not to work.Now,to come back to the prototype card, there also is a problem of transport of wires visible on this card (which also exists on the final memory module).We have 256 inhibit lines plus the 64 sense lines, which makes a total of 320 wires to control this memory interface.The three connectors I have circled should be able to transport 320 connections, which makes 106.66 connections per connector; and, as a connection can't be fractional, that makes that each connector should have at least 107 pins!The cover of the connectors allows to partially see the pins of the connectors; we can see three of them for each connector; we can measure the gap which separates them, and from it we can evaluate how many pins each connector has.I have here reconstituted the pins of a connector by duplicating the three visible pins over the whole length of the connector; In my reconstitution, the connector has 19 pins; of course, there may be a margin of error, the connector may have a little more pins (or a little less), but we are very far from the 107 pins the connector should have, and even if there are two, or even three rows of pins, we are still far from the required number.Furthermore it is difficult to believe that there are 107 wires in the bundle of wires coming to each connector!The documentation of the NASA says that it was possible to insert 6 rope modules into the housing of the computer of Apollo.And also that each of these modules had 512 cores with 192 sense lines passing through or bypassing the cores, which makes a capacity of 98304 bits, and 98304/16=6,144 16-bits words, or 6K words in shorter.So, with 6 modules of 6K words, we have a total capacity of 6*6K=36K words, the memory that the NASA was claiming the ROM memory of the AGC had.This is the exploded view of the computer of Apollo.In this exploded view, we can see the bottom tray, called tray A, into which could only be plugged short modules, which was excluding the rope modules which are relatively long modules, and, above, the tray B, on which there was a window allowing to plug the rope modules, which had to be easily removed, for they might have to be corrected (unlike the short modules which are hard wired).Here we can see the interior of tray A with the connectors for the short modules.On this view, we can see tray B on top of tray A.Rope modules can be inserted on each side of tray B, but rope modules cannot be inserted on the bottom of the computer, because this bottom is tray A, and is reserved for the short modules; there is no room for the rope modules in tray A.At first view, the tray B seems able to contain six rope modules (three on each side).Now let's see: For the two upper modules, we can see slots to insert them...But, for the lowest one, we can see no slot; without the slots, the lowest module will not be correctly maintained, will be loose.On this photocomposition, I have added the missing slot on the right side for the lowest module that I indicate with an arrow.On this illustration of Tray B alone, we see four connectors at the end of the tray.Someone said that there are already two modules inserted on each side of tray B......But, on this close-up, we can see that:1) These modules only have half the width (red arrow) they should have (green arrow).2) These modules don't touch the frontal plates (orange arrow).3) And on the frontal plates, there is the inscription "RETREAD" written upside down.On this close up of the previous illustration, we see two rope modules; one is already half inserted, and the other one is not inserted.On the one which is not inserted, we can see the inscription "RETREAD", but normally, not upside down.And it is not because this module is itself put upside down, for we can see, by several details I have circled, that this module is not upside down.That means that, when a rope module is inserted, the inscription "RETREAD" should not be upside down.Some have said that what I show as gaps would be shadows...So the black area I have circled in red would be a shadow on the module and not a gap?The shadow cannot come from the bar which is above, for we can see its shadow I have circled in yellow, and which is not even black, but grey!This shadow could only come from the frontal plate; but, for the frontal plate to create this shadow, the light source should come from the front of the tray, along the arrow I have drawn in red.But, if the light really had that direction, then the parts I have circled in orange on the right of the tray would not be shaded, and they are.Even if the light was coming from the right side, these parts would not be shaded; for these parts to be shaded, the light has to come from the rear of the tray......And, in this case, the frontal plate could not create the shadow we see!The Apollo believers have also told me that we could not see the edge of the module; this is only true at the beginning at the module; but, farther, at the place I indicate with a yellow arrow, this edge is visible.I here show a close-up of the part I indicated with a yellow arrow on the previous figure.We can clearly see the edge of the rope module I indicate with a yellow arrow.So, the modules which are already inserted would have been inserted upside down, and would not have the normal width, only the half of it?On a video, we seem to see six white connectors on the back of Tray B, which would show that six rope modules can be inserted, but first these connectors are misplaced.....And, second, on the left side of Tray B we can see only two slots to insert rope modules.....And, third, we see a rope module before Tray B, and it is obvious that it is not physically possible to put three of these modules on each side of Tray B; Tray B is not high enough.Notice too that we see no slots on the central plate.Now, the main point is that the rope modules of the computer had 512 cores and 192 sense lines, theoretically giving a capacity memory of 6K words.Now let's see if this rope module was really working with 192 sense lines and 512 cores!We don't see very well the cores of the rope module everywhere, but we see them quite well on the bottom right of the rope module.It is possible to count the cores of the rope module; there are 8 rows of 32 cores, which makes a total of 256 cores, and not 512.Where are the 256 other cores?And, if the sense wires are too thin to be directly counted, we have an indirect way to count them.Each sense line is indeed individually connected to a couple diode&resistor which allows to select it for reading (or not select it); these couples diode&resistor are indicated with an arrow on the top of the module and they are visible enough to be counted: There are 96 of them.There should be 192 of them, so the 96 other couples diode&resistor must be on the bottom of the module!We can see the diodes of the couples; I have circled one of them.Now, if we compare some couples of diode&resistor on the top of the module and on its bottom, we can see that they are different, when they should normally be identical!They are longer on the top than on the bottom; yet they should normally have the same length!In fact, if they are different, it is because the resistors I have framed in red on the top of the module are missing on the bottom of the module; and, without these resistors, the sense lines connected to the couples diode&resistor of the bottom cannot be selected, and thence not used.Only the 96 sense lines connected to the couples diode&resistor of the top of the rope module can be used.Someone has suggested that the other 256 cores and 96 diode&resistor couples would be on the other side of the rope module.Let's focus on the connector of the Rope module.We can see the connector wholly, which shows that the module is placed under the connector; that means that the module is placed on the bottom of its case; there is no place to put core modules on the other side of the module, because a second layer of core modules could not be too close to the first layer, there should be a minimal separation between the two, and that would exclude placing the rope module too close to the bottom of its case.And on the diode&resistor couples of the lower part of the module, we can see the diodes of the couples; it is the resistors which are missing, making the couples of the lower part inoperative.Only the sense lines are connected to diodes, the command wires are not.They would not have put diodes on the count of the 96 other sense lines which have no use, they would have put nothing; putting these diodes means that the lower part of the modules was supposed to contain the 96 other diode&resistor couples, but the latter have been made inoperative by removing the resistors.There are no diode&resistor couples on the other side.So, now, this rope module has only half the normal number of cores, and half the normal number of sense lines which are usable...and, consequently, its capacity memory falls down to the fourth of its advertised memory, so 1.5K instead of 6K words.So we now have four rope modules with a capacity memory of 1.5K words only, which makes a total capacity of 6K words; we are far from its advertised memory of 36K words; and eve, if six rope modules can be inserted, and that these six modules only have 1.5K words, it still makes only 9K words instead of 36K.And the manual way the memory was woven makes no sense either: Rely on workers not to make any error!The weavers had to make wires pass through cores or bypass them 16384 times (for a memory card).That makes 16384 occasions to make an error!And if really they had made all the memory cards to memorize the announced 36384 words of memory, it would have made 589824 occasions to make an error!Well, or course, after the female workers had woven the memory, they certainly had a process to check if there was no error, but, if there was one, the card had to return to the factory to be corrected, and the corrections were awfully difficult (a faulty wire had to be completely removed and woven again - provided that they were localizing the faulty wire correctly and not confusing it with a correctly woven one!).And, if there were several corrections made in the ROM program, making corrections in the woven memory was a real nightmare!So There is absolutely no doubt that the core rope memory of Apollo was a joke and never intended to work.So, when they baptized the core rope memory "LOL", it was not really meaning "Little Old Lady"......But what it generally stands for, that is "Laughing Out Loud".It was clearly meaning this memory was a joke, and that it could not work.Now some claim that the expression "Laughing Out Lout", abbreviated "LOL", has specially been created for Internet and was not existing before; so the engineers of the NASA could not have used it to baptize the core rope memory.Nothing is more wrong:The expression "Laugh Out Loud" is far from being recent.An old cartoon "Laugh Out Loud cats" can testify of it; this cartoon was created around 1912, which proves that the expression "Laugh Out Loud" is far from being new.And it is very probable that this expression is even older than that.The creators of internet did not create the expression "laughing out Loud", they just used an expression which was already existing.This is the simplified schematics of the erasable memory.The brick which is inside the loops of current represents the arrays of cores.If no core rope memory has ever been used apart for Apollo (at least the way it was designed for Apollo), such is not the case of the normal erasable core memory which can perfectly work.So, if the ROM memory of Apollo could not work, we could at least have expected that the RAM memory would have worked...But they have managed to make even the erasable memory not work!I have represented in red the path of the write current; the current turns clockwise in the loop; this makes it go up in the block of the cores.And I have represented in blue the path of the read current (the sense line); the current turns also clockwise, but, as it is on the left of the wite loop, this makes it go down in the block of the cores.Now, what's abnormal is that the write current loop and the read current loop have a common part: it is the same wire which allows both to change the magnetic field of a core and also to sense the impulsion which is generated by the change of magnetic field of a core.This is absolutely impossible: The wire which allows to generate the change of magnetic field of the core by sending a current into it cannot also get the impulsion generated by the change of the magnetic field; this change of magnetic field has to be detected in another wire, called sense wire; the wire generating the impulsion and the one reading it cannot be the same, NO WAY!And what makes it still more absurd is that the current of the write loop and the current of the read loop go in converse direction in their common part!You might have thought that it was incoherent enough for the fakers to be satisfied?Oh no, they had to add some more salt!This is the schematics of the regulated pulse current driver which allows to read the sense pulse.This interface contains two transistors (T2, T3) mounted in current regulator.The current regulation is based on the fact that, when a current runs through a diode, it generates a difference of voltage of 0.7 volts on the ends of the diode.When there is a pulse coming on the base of T1, T1 gets activated and the current can pass between the collector and the emitter of T1.Because of the double diode connected to the base of T2, the voltage on the base of T2 is then equal to 14-1.4 volts (2x0.7=1.4); the voltage on the emitter of the PNP transistor T2 is equal to the voltage on the base of T2 plus 0.7 volts, so 14-0.7 volts; this would generate a regulated current of 0.7/R through the resistor R.If T2 is activated, the current can go through its emitter to its collector, and also go through the double diode connected to the base of T3; the voltage on the base of T3 is then equal to 1.4 volts (2x0.7 volts).If the transistor T2 is activated, the voltages on its emitter and its collector should be equal, but the double diodes D1&D2 force the voltage of the emitter to 13.3 volts, and the doubles diodes D3&D4 force the voltage of the collector to 1.4 volts!It can't work, this interface is aberrant.So, as incredible as it may seem, neither the ROM memory nor the RAM memory of Apollo could work.They both appear as a complete joke.But have no qualms for Apollo, Otto is here to manage the situation.And, between the man and the computer, there was the DSKY unit, that is a display coupled with a keyboard.You might have thought that this unit was correctly working?NOPE!This schema shows how the display was commanded.Each relay which is activated (the spirals) allows to light a segment of the display.There are two commands to select a segment:- A word command which selects the digit that the segment belongs to.- And a line command which selects the segment in this digit.In order to light a segment, its line and word commands must be activated.When the line command is activated, the transistors I have circled in red are activated by the line command.A current then runs from their collectors toward relays, I have circled in green; but in order for this current to be running through the relays, it also must run through the transistor I have circled in orange, which one is activated by the word selection command.But, why are there two transistors, and two relays, when one would be enough?The argument is that it creates a redundancy: If one transistor fails to light the segment through its own connection, the other one can through its own connection.So, there are two transistors to light each segment, so that it still can work if a transistor fails.But, if the first transistor of the pair, the one I have circled in red, fails open, it will not light the segment (when both the line and word commands of the segment are activated), but it will not allow to the next transistor to light the segment, for the failed transistor also allows to activate the next transistor.So, in spite of the presence of the second transistor, the segment will not be lit.The redundancy does not play its role.Now, if the transistor fails shorted, it will permanently light the segment, even when the line command is not activated (but the word command is), even if the next transistor works correctly.Once again, the redundancy does not play its role.And; if the second transistor of the pair, the one I have circled in red, fails shorted, it will also permanently light the segment, even if the line command is not activated, even if the first transistor works correctly.Not only the redundancy does not play its role, but it even makes things worse, for there is more chance that one transistor in two would get shorted than a transistor alone.If they had wanted to make a true redundancy, they would have made it the way I show here:- If any transistor fails open, the other pair of transistor can still correctly light the segment, when the line command is activated.- And, if a transistor gets shorted, the other transistor of the pair, which still works correctly, will prevent it from permanently litghting the segment.Now we have a true redundancy which makes that, if a transistor fails (but only one), the segment can still be correctly commanded, i.e. lit if the line command is activated, and not in the converse case.This schema shows how the DSKY unit was connected.But there are several problems in what is shown.First the collector of the transistor I have circled in red is not connected to a plus reference.So the relay matrix which follows will not be able to work correctly.And secondly, on the input of the NOR gate of the key code inputs, there is a feedthrough capacitor that we might wonder what it is doing here!I have added a connection to a plus reference on the transistor connected to the display ligtht selection which is necessary for the display light to work correctly.But the problems of connection of the keyboard are not the only problems.The AGC was using an electroluminescent display on a dark background.Your modern computers use modern displays like the one I show; in fact the displays you currently use are even more advanced than the one I show, for they are extra-flat, but I'll use this one which is more demonstrative.On this type of display, a beam sweeps a screen; the width and the height of the sweeping can be adjusted, and also its intensity; consequently, the size and the luminosity of the digits which appear on the display may vary.But the the computer of Apollo was not using this technology at all for its display.It was using instead a much simpler technology, which had the advantage of being easier to command and much faster, which was important given its feeble power.The display was constituted of a series of "7-Segment" which could represent the digits to display.This animation shows how a 7-Segment works: A 7-Segment is contituted of seven luminous segments (Hence its name); when a digit must appear, the segments which represent it at best are lit.There is a special circuit which makes the conversion between a binary digit and the corresponding commands which must be sent to the 7-Segment to light the segments which represent it; this animation shows how this converter works.A digit represented by a 7-Segment may be On......Or it may be off......But it can't be half on.A segment is either lit or off, but it can't be half lit.So a 7-Segment has two particularities that it is important to note for what follows:- Its size is physically determined, and absolutely cannot change- Its luminosity is also unique and cannot change (i.e. cannot become dimmer).An electroluminescent display always uses a dark background, otherwise the symbols would not be clearly visible when they are lit; the symbols are faintly visible even when they are not lit.In the mission Apollo 11, "Buzz Aldrin" (or rather the actor who pretends to be him) makes a demonstration of the AGC in the command module.Everybody has admired this sequence, supposedly showing that the AGC was perfectly working.Yet, it contains plenty of hints that it is fake.In this sequence, we can see the electroluminescent segments all, or almost all, become suddenly lit.the verb 35 allows to make the light test which allows to temporarily all the light indicators and the electromuninescent segments.In the virtual AGC, before the light test is started, the display looks like this; this is what we see in the sequence of the command module before the astronauts type "ENTR".And, in the virtual AGC, after the light test has been started, the display looks like this; this might be what we see in the sequence of the command module after the astronaut has pressed "ENTR", though we cannot clearly read the display, because it is too blurry.Before the astronaut presses the "ENTR" key, at the beginning of the video, the verb seems to display the value "35" which must have been typed by the astronaut before the video starts.So, it is logical that, when he presses the "ENTR" key, the light test starts and displays something which looks like what we see.Yet, there are some problems.First, when the segments appear lit, instead of appearing all lit in the same time like they should, they appear progressively instead like this slowed animation shows; this whole sequence spans over a half second; it may not seem much, but, for a computer, even a slow computer like the AGC, it is enormous.If the AGC needs a half second to light some digits, then we may wonder about its capacity to guide the spaceship!Furthermore, whereas the buttons appear all lit on the left, during this sequence half of them go off to go on again a little later; where is the coherence in this?Likewise, when the light test is stopped, the electroluminescent segments should go off all in the same time; but they also go off progressively instead, in a span of a half second too like it is visible on this slowed down animation.And there is also another problem.On the keyboard of the unit, there was a key labeled "STBY" (for "StandBy", circled in red).Out of the standby mode, this key allows to proceed when an internal routine requests data, and tell it to continue its process, either with the entered data, or eventually no provided data at all. During the light test, there currently is no command to proceed with, since the "PROG" light is not on, and it goes on when an internal routine wants to take control fo the unit.So the astronaut has no reason to type the STBY key at that moment.Yet, just before typing the next command sequence, I have caught the astronaut needlessly typing the "STBY" key.Here is the image I captured on which he types this key.Now, we are going to get interested in the final sequence of the demonstration.This is an excerpt of this sequence.We see the astronaut type a command, and then data for this command.What is this command exactly?The astronaut first presses the "Verb" key.Then the astronaut pressed the "3" key.Then the astronaut pressed the "7" key.Finally the astronaut presses the "Entr" key, to finish the command, and take it into account.What is this sequence exactly?According to the documentation of the DSKY, the sequence, Verb, 3, 7, and Enter corresponds to a change Major Mode sequence: its effect is to blank the noun display register, and to make the Verb display register flash; a two character major mode has then to be typed and the Enter key to be typed again. As the two digits of the new major code are typed, they successively appear in the noun display register.I have circled in red the verb display register, and in green the noun display register.Then the astronaut presses the 0 key, which corresponds to the first digit of the new major code; after having been typed, it appears in the leftmost digit of the noun display register.Then the astronaut presses the 1 key, which corresponds to the second digit of the new major code; after having been typed, it appears in the rightmost digit of the noun display register.Finally the astronaut presses the "Entr" key to take into account the new major code; you can see that the two digits of the new major mode appear in the noun display register, which shows they have been correctly typed.When the computer activity indicator (circled in red) turns off, it means the computer has finished handling the command; at that moment, the documentation says that the new major code should be displayed in the Major Mode display register, that is the first data register (circled in green); but you can see that there is nothing in this data register, it is blank!A new hint that this demonstration is fake.And there is a last hint that the sequence is fake.At the start of the light test, a lamp, on the left of the AGC (circled with red), goes on.At the end of the sequence, the astronaut lifts up his hand to press a button to switch this lamp off.Yet, even before the astronaut lifts up this hand, as this slowed animation shows, the lamp automatically goes off, which means that the astronaut does not need to switch it off any more.Yet, he does not stop lifting up his hand, and uselessly presses the button to switch the lamp off.However, unlike the previous hints, this one does not show an incorrect behavior of the AGC, but just an illogical maneuver of the astronaut.So, this demonstration contains a succession of hints which proves it fake.You can notice that, in this demonstration, the background of the display appears dark.Yet, on this photo of Eldon Hall typing on the AGC's keyboard, we can see that the background of the display of the AGC is unexpectedly clear, clearer than the rest of the DSKY unit; and we can see dark symbols on it.Then someone showed me this photo of the AGC shown in the computer history museum which looks like the one shown on the previous photo.But, the background of the display is light instead of being dark.And we can see no 7-Segment symbols on it, even faintly.If it was an electroluminescent display, the display's background would be darker, and we could faintly guess the symbols on it.It rather looks like a liquid crystal display.The liquid crystal displays started to appear only in 1971.In the start of the Apollo missions, they were still not existing, but, at the end of the missions, they were starting to appear, though their technology was not still ripe.This first version of LCD was displaying white digits on a black background.Later versions of LCD display displayed black digits on a clear background.The first clear backgrounds were yellow, for the yellow was actually a filter in front of the display to absorb damaging Ultra Violet light and prolong the life of the liquid crystal material.However the technology of the LCD was not still well mastered in the beginning of the seventies.The slow response speed of early liquid crystals, and concerns about the life and temperature stability of the liquid crystal material held up its wide acceptance till the mid 1970s.That means that, if they had used a LCD display in the final missions, there was a high risk that symbols of the display could disappear, or become illegible; this was not acceptable in the Apollo missions, in which the safety of the display was so vital.In fact, the only advantage of the LCD display over the electroluminescent one at that time was its lesser power consumption; but it was at the price of safety!The documentation of the AGC written by Eldon Hall, and dated 1972, clearly states that the AGC was using an electroluminescent display; nowhere it is made mention of a LCD display.When I said to the Apollo believers that I was doubting that the displays shown on these photos had ever displayed anything, they showed me a photo and an animated demonstration with this type of display actually displaying something, and it is then that I understood the trick.I was first shown this photo with a display which looks like the one which is exposed at the museum.It has intrigued me at first, and then I have found interesting things on it, that I going to explain.First, if we compare this DSKY with the one of the video in the command module, it is absolutely obvious that the displays are very different: On the video of the command module, the background is definitively much darker than the rest of the AGC, and, on the photo the Apollo believers showed me, it is the converse.So what?Would have they changed the technology of the DSKY meanwhile?Now, the lit segments could be fake, they could be pasted over the display.Of course, you are going to tell me: Prove it!There are several clues which show that this photo is staged, and I am going to give them.First clue: Let's focus on the part of the display I have circled.See the horizontal bar of the '+' sign: It touches the '0' digit on its right; On an electroluminescent display, the digits are well separated and don't touch each other!Second clue: On the left of the DSKY, we see the cable which connects it to the computer.Let's focus on the part I have circled.The cable should go to the connector of the DSKY on its back; instead it goes to its front, and gets narrower; the way it is connected is totally abnormal.Third, and most interesting clue: See the indicator I have circled.This indicator is the "TEMP" indicator, and is the indicator which indicates that the temperature of the stable member of the IMU (the gyros) is out of bounds.The IMU is essential to the spaceship, for it allows its guidance; if it was stopping working, the spaceship would be left without guidance.And don't think that the ground could guide the spaceship instead, for the ground also needs the informations of the IMU to calculate the position and orientation of the spaceship, which informations are transmitted via the MSFN.You might say: It does not prove that it could also happen during a lunar mission, for the AGC could have been running for a long time when this photo has been taken; I can't know how long it has been running when this photo has been taken.Oh yes, I know, and I am going to explain how I know it!The AGC had two timers counting the time, called TIME1 and TIME2; both were 14 bits counters.The first one, TIME1, was triggered by a 10ms clock signal, and so was counting hundredths of second.As it had 14 bits, it could count up to 2^14-1=16383; at the next clock pulse after it had reached its maximum, it was reset to zero and, in the same time, was triggering the timer TIME2; so the timer TIME2 was triggered every 16384 hundredths of second, or 163.84 seconds; it was also counting up to 16383.The two timers were equivalent to a 28 bits timer which could count up to 16384*16384-1=268435455 hundredths of second, or 2684354.55 seconds.Expressed in hours, it was making : 2684354.55/3600=745.65 hours; and in days it was making: 745.65/24=31.07 days, so just a little more than a month.It is way over the longest of the lunar missions.There were two ways of displaying these timers.The verb 16 allows to monitor data, that is to display data which is selected by the noun.The nouns 36 and 65 correspond to the display of the timers.The virtual AGC shows how the noun 36 was displaying the timers on three lines:- The first line displays the hours.- The second line displays the minutes- The third line displays the hundredths of second.The virtual AGC is not clear about the way the noun 65 displays the timers; by reading it, one could think that the noun 65 displays the timers the same way as the noun 36.But, in that case, what we see on the photo would be wrong, for we only see two data lines on the display.But, what we see on the display is not incorrect, for the noun 65 displays the timers differently from the noun 36, as I have checked in the original documentation of the AGC.- The first line displays the hours under the form XXX.XX; in fact it does not display the decimal point, it just displays the double timer as hundredths of hours; it represents the integer division of the double timer by 3600, and it can go up to 74565.- The second line displays the seconds under the form XXX.XX; in fact it does not display the decimal point either, it just displays the double timer as hundredths of second; but, as five digits are not enough to display the double timer, the second line displays the value of the double timer modulo 100000, that is the remainder of the division of the double timer by 100000.it can go up to 99999.So, what we see on the display is compatible with what I said.There is a correlation between the two displayed lines that I am going to explain, and that we can check.the value 133 displayed on the first line corresponds to a number of hundredths of hours; to obtain the corresponding value in hundredths of second, we multiply it by 3600, which gives: 133*3600=478800 hundredths of second; but, as it changes every 3600 hundredths of second, the current value of the double timer is comprised between this value, and this value+3599, so between 478800 and 478800+3599= 482399; expressed in modulo 100000, that would make for the second line a value comprised between 78800 and 82399; now the second line displays 78812, and is thus in the expected range; thence the two lines are compatible; I would have expected otherwise, but I have to admit the compatibility of the two displayed lines.But, it at least proves something: the AGC has been running for 1.33 hours; the fractional part 33 does not represent minutes, it represents 0.33 hour; in order to know how much it represents in minutes, we must multiply the fractional part by the number of minutes in a hour, so 60*0.33=19.8 minutes, we can round it up to 20 minutes.So, we now have the proof that the AGC has been running for only one hour and twenty minutes when this photo was taken, and, in a so short time, the IMU already has temperature problems.So, now think: if the IMU already overheats after having worked for only a little more than a hour in an environment which is more open than in the spaceship, what will it give when it has to work for several days continuously in the more closed environment of the spaceship?We have every reason to think that it has much chance to get out of order and to leave the spaceship without guidance!The Apollo fans have also shown me an animated demonstration of this special DSKY unit.On it, we can see the digits change, so it cannot be, like I have suggested, something (like fluorescent tape) just pasted over the screen.However, if we compare the display on this animation with the display in the video of the command module, we can see that the legibility of the digits is much much better in the video of the command module, because of a better contrast provided by a dark screen instead of a light one.In fact, if we look close, the display on this DSKY unit does not look like electroluminescent segments at all; the contrast is very bad (it is always very good for an electroluminescent display), the segments are not clean, and, like on the photo. the horizontal bars of the '+' signs touch the next digit.It absolutely does not look like an electroluminescent display.But, on the other side, it looks like an image projected from a projector.The animation was projected from a projector aiming at the display of the DSKY.Of course, I don't say it was this projector, and it certainly was not.And if the display does not have the good quality for an electroluminescent display (i.e. not dark enough)......It had good reflective properties like a projector screen.These reflective properties were allowing it to reflect the image projected from a projector, what a black screen could not have done (you have never seen a black projector screen, have you?).Now, what elements do I have to support this theory?At a given moment, during the sequence, we see them move back the DSKY unit a little.This stereoscopic view shows on the left the unit before they moved it back, and on the right the unit after they moved it back. (You can also see that the unit has moved back if you consider the holes on the top of the device which is on the right of the unit).But why did they move it back for?It was not to put the unit more into evidence, because, before, it was closer and entirely visible, so better placed for the demo at the beginning of the sequence than in the end.So there had to be another reason, and I looked for that reason.Finally I found that reason when I noticed a flare which appears on the bottom of the image at the beginning of the demonstration.This flare is obviously created by the projector's beam, which allows us to know that the projector was placed under the image.And so that there is no ambiguity, that this flare is not just a white spot, we can see this flare move on the image during the demonstration.So, they moved back the unit a little so to obtain a better orientation for the projector's beam which would avoid this flare; and effectively we don't see this flare any more after they moved back the unit.The fact of moving back the unit also allows to avoid the reflection of the projector's beam on the operator's hand: the photo on the left shows an image of the demonstration before the unit is moved, and the photo on the right an image after the unit is moved.The hand has approximately the same orientation on both images.On these close-ups, we can see that the ring that the operator wears is brighter on the first image (i.e. before the unit is moved) than on the second one (i.e. after the unit is moved), despite the fact that there is a finger over the ring which should shade it.On the first image we can't see the relief of the ring, whereas we can on the second one.There are other elements of evidence that the display we see is projected from a projector.By examining the sampled images one by one, I noticed a variation of the display between two sampled images.This is not very visible on this global animation......But it is much more visible on this animation made with two windows of the display oftaken on the two consecutive sampled images.You can clearly see that the "35" floats (not only in position, but also in size) on the display (notice the variation of the top of the digits relatively to the window which is above); this could not happen with an electroluminescent display on which the segments always keep the same physical size which cannot vary, and it undeniably proves that the display is projected.In the middle of the light test, the digits of the verb and the noun (the two pairs of digits over the three data lines) suddenly go dimmer to go bright again (while the luminosity of the other digits does not change); this also cannot happen on an electroluminescent display on which the segments of the digits can be on or off, but not half on.This also undeniably proves that the display is projected.You may say; OK, but the operator has to press on the keys at the good moment, because, if he was not synchronized with what is displayed, it would show!Yes, but the operator knew in advance what he had to type, the scenario was prepared in advance.There could be a slight shift between what the operator types and the display, but this problem was solved like I explain it here on this slowed down animation: The operator has to type a '6' in the sequence; he is a little in advance over the projected display; so he puts his finger before the '6' and waits for the 6 to appear on the display, as soon as the projected '6' appears, he finishes pressing the key; it just takes some fractions of seconds, so the viewer notices nothing, and thinks that it is the fact that the operator pressed the '6' which made the '6' appear, when it simply was in the projected sequence.In order to well catch what the operator does at the moment that the '6' appears on the display, I have sampled the video faster than I usually do, that is 20 images per second instead of 10 images per second.I show here on this stereoscopic view two consecutive images of the sampled sequence; on the first one (left), the '6' has already appeared on the display; the operator immediately reacts by actually pressing the '6' key; but, even if he is very fast, there is still a little lag in his reaction, and that is why we see him press the '6' key in the next image (right).It is not very visible in the stereoscopic view I have shown, but it is much more visible on this animation alternating the image on which the '6' appears on the display (labeled "BEFORE" in green) with the image on which the operator presses the key (labeled "AFTER" in red).If it really was the AGC displaying the '6', it could not appear on the display before the operator has pressed the key.On this image extracted from the sequence, the operator uses a special technique to improve the synchronization between what he types and the display.Instead of using just one finger like he normally should, he uses two crossed fingers; he starts typing with the finger which is under; if the display changes, he then removes his hand, like what we see on the image, so that we can see the finger he used to type the key; but, if he is a little early on the display, he then uses his second finger, the one above, and makes believe he used that one to press the key.In fact, it explains why the DSKY had this type of display.It was effectively not a liquid crystal display, it was a display which had good reflective properties to display an image projected from a projector, so that the DSKY unit did not have to be a living unit and anything displayed on it could be simulated by projecting an image on it!Now, the fakers gave several clues that this sequence is staged.1)There is the "TEMP" indicator which goes on, like on the photo, after the AGC has run for hardly more than a hour and a half (since the first timer line displays 152, which represents 1.52 hours, so in fact one hour and 31 minutes), leaving serious doubts on the viability of the IMU.2) There is also the "KEY REL" indicator which briefly goes on and off when the operator presses the '3' key instead of the "KEY REL" key (which is just on the right of the '3' key) which is related to this indicator.Notice that this indicator looks like a hand with the forefinger stretched up.3) And there is even a new clue which was not even on the photo!At a moment, they make display the timers with the verb 16 and the noun 65, like I explained before.The upper data line (the hundredths of hours) displays "00152", and the lower data line (Hundredths of seconds module 100000) displays "45723".152 hundredths of hours corresponds to 152*3600=547200 hundredths of seconds.That means that the lower data line should display at least 47200 (between 47200 and 47200+3599=50799)...And it displays only 45723, so less than the minimal value it should display!And don't invoke a problem of refresh time of this display, for the difference corresponds to almost 15 seconds!So, this time, unlike in the photo, there is no correspondence between the two data lines of the timer, and we have a fakery clue we did not have in the photo!And, since I make a comparison between the two displays, look at the impressive difference of contrast between the two displays!The contrast is way worse on the animated sequence than on the photo.It is absolutely obvious that it is not produced the same way on the photo as on the animated sequence.On the photo, the display is not projected, it very probably hard pasted on the screen (may be with some kind of fluorescent tape, or a special pen).A presentation of the Apollo Guidance Computer has been made in 1965 by the NASA: "A computer for Apollo".It seems a serious demonstration, but in surface only.If we scratch the surface, plenty of anomalies appear.This presentation successively features Eldon Hall, Ramon Alonso, Albert Hopkins, and an engineering manager of Raytheon.Eldon Hall first makes a presentation of how the spacecraft is guided.He explains how the alignment with one star allows to make the guidance of the spacecraft.By moving his hands, he illustrates how the angle between the star and the earth decreases as the spacecraft gets away from the earth.But he omits to say that this angle also changes if the spacecraft moves laterally without getting away from the earth.In fact it is not possible to make the guidance by using only one star; we are in a three-dimensional system, and