What is PHDL?

Motivation

is an open source hardware description language that models text-based schematics for Printed Circuit Boards.

PHDL was created because we believe that graphical schematic capture is a terribly inefficient way to do initial PC board design entry. This is partly because of the the use of high pin-count devices and wide signal busses in modern PC board design, requiring schematics to be spread across many pages. Doing so largely eliminates much of designer's ability to visually see and verify connectivity (which has always been the claimed advantage of graphical design tools for PCB's). That is, flipping between multiple pages of schematics to verify connectivity between device pins really has no advantage over flipping between multiple pages of HDL code to verify connectivity between device pins. In fact, it may have a disadvantage since the latter can be done using a text editor or software development IDE such as Eclipse rather than a graphical tool!

Further, graphical schematic capture tools are usually proprietary, non-portable, and rely on closed file formats to represent the user's design. Finally, they lack all of the productivity-improving features that have made HDL's the method of choice for the design of IC's and FPGA-based digital designs over the past 30+ years.

The PCB Design Process

As shown below, PCB design consists of two basic steps: (1) using a schematic editor to graphically draw the connectivity of the PCB components, and (2) completing the physical PCB layout using a physical design tool such as PADS or Eagle.

PHDL is designed to replace only step (1) above by providing an HDL (hardware description language) based tool to increase designer productivity for doing the initial design entry. The result of creating and then compiling a PHDL design is a netlist which is then imported into the physical design tool for the physical layout step.

Ways that PHDL simplifies schematic capture:

Generates massive buses in a single line of code

Re-uses device definitions easily

Ports to several layout tools including PADS and Eagle

Instances several devices easily

Re-maps nets effortlessly

Updates

3/7/2012 - Updated documentation.

11/25/2011 - Fixed a nasty bug with the "Contact Us" page.

Who are We?

was developed in the Brigham Young University Configurable Computing Lab under the supervision of Dr. Brent Nelson by Brad Riching and Richard Black.