Circuit-Level Requirements

In order to benchmark the 2D FETs at the circuit level and understand the energy-delay tradeoff, we choose delay and energy per operation as circuit level figure-of-merits (FOMs). We estimate these circuit level metrics for a simplified version of critical path in CMOS logic, with a CMOS inverter chain and balanced 2D FETs for both p- and n-type transistors. The first-order equations for delay and energy per operation can be written as ref. 10:

$${\tau }_{CP}=\frac{{C}_{node}{V}_{DD}}{{I}_{ON}}\cdot {L}_{D};\quad {E}_{tot}={C}_{tot}{V}_{DD}^{2}(\alpha +{L}_{D}\frac{{I}_{OFF}}{{I}_{ON}})$$ (1)

where τ CP is the delay of the critical path with a logic depth L D and the total capacitance of each node C node . Total energy (E tot ) per operation can be written as sum of dynamic and leakage energy. Here, α, and C tot denote the activity factor and the total capacitance of the logic design respectively.

Further, we normalize the total energy and delay by the capacitance of the chip, which is reasonable for the sub-10 nm technology nodes, when the total capacitance is dominated by interconnect capacitances instead of intrinsic device capacitance, given as:

$$N{\tau }_{CP}=\frac{{V}_{DD}}{{I}_{ON}}\cdot {L}_{D};\quad N{E}_{tot}={V}_{DD}^{2}(\alpha +{L}_{D}\frac{{I}_{OFF}}{{I}_{ON}});\quad NE\tau ={E}_{tot}\cdot {\tau }_{CP}$$ (2)

here Nτ CP , and NE tot denote the normalized delay and total energy per operation respectively, while the energy-delay product (NEτ) signifies that energy and speed are equally weighed for an optimized logic design.

As shown in Fig. 1, we extend the circuit-level high performance logic roadmap for sub-5 nm technology nodes by extrapolating scaling of normalized delay and energy-delay product from Intel 22 nm1 to Intel 14 nm technology nodes2 with reported 15% boost in ON current (for same supply voltage) and required 50% reduction in the energy-delay product. Thus, the scaling of normalized delay by 0.87x and normalized energy-delay product by 0.78x results in total capacitance scaling of around 0.8x with each technology node. Figure 1 shows that extended Intel HP requirements seems most reasonable in comparison to ITRS HP requirements while III-V ITRS HP requirements are quite ambitious.

Figure 1 High-performance logic roadmap, (a) Normalized delay (Nτ CP ) and, (b) Normalized energy-delay product (NEτ) with technology nodes for α = 0.1, and L D = 10 (HP logic). Full size image

Technology Requirements

To achieve area scaling of 0.5x with each technology node, the technology parameters such as contacted gate pitch (C GP ) and metal pitch (MP) are scaled by 0.7x with each technology generation. To scale C GP , gate length (L G ) scaling has been the primary driver for past technology generations. But, due to process constraints, scaling of C GP below 25 nm is not forseen11. Therefore, for future technology nodes it is imperative to scale gate lengths in sub-10 nm to relax constraints on spacer thickness and contact openings. Alternatively, technology options such as monolithic 3D integration are sought to further scale the area per function12. The technology parameters listed in Table 1 (till N2) are taken from III-V ITRS HP roadmap13.

Table 1 III–V ITRS 2013 HP Roadmap extended for gate lengths below 5 nm. Full size table

Device-Level Figure-of-Merits

We consider a double-gate monolayer 2D material based FET as shown in Fig. 2a. The electrical characteristics of 2D material based FETs are calculated using the framework described in methods section. The effect of different transport effective mass and channel lengths on ON current (I ON ) is shown in Fig. 2b. We can clearly see that a smaller effective mass 2D material is the preferred choice for high performance logic. Smaller transport mass 2D materials with anisotropic properties can offer higher carrier injection velocity and higher inversion charge density, resulting in higher on-state current provided we can maintain good electrostatistics with gate length scaling. To get physical insights in electrostatics of shorter gate length devices, we study the effect of transport effective mass on sub-threshold slope (S.S.) behavior for different gate lengths as shown in Fig. 2c. We break-down Fig. 2c into two regions: 1) At lower effective masses S.S. degrades due to direct S/D tunneling (due to material property); 2) At higher effective masses where the increase in S.S. with downscaling of gate lengths is attributed to 2D electrostatistics.

Figure 2 Device Simulations, (a) Double-gate monolayer 2D material based FET with L S = L D = 15 nm, and n + doping of source/drain = 4 × 1013 cm −2, and for a fixed transverse effective mass (\({m}_{y}^{\ast }\)) effect of transport direction effective mass (\({m}_{x}^{\ast }\)) and gate length (L G ) on, (b) ON current including effect of scattering and contact resistances, and, (c) Extracted subthreshold slope near OFF state. Full size image

Circuit-Level Figure-of-Merits

Figure 3 shows the combined effect of sub-threshold and super-threshold behavior on delay and energy-delay product for a given I OFF of 100 nA/μm. We observe that till N3, 2D materials with smaller transport effective mass outperform the 2D materials with higher ones. It can be also seen that monolayer BP (\({m}_{x}^{\ast }\) = 0.15 m 0 , \({m}_{y}^{\ast }\) = 1.2 m 0 ) FET can meet both extended Intel HP and III-V ITRS 2013 HP delay and energy-delay requirements for N7, and N5.

Figure 3 Performance of DG monolayer 2D FET at different technology nodes (a) Normalized delay and (b) Energy-delay product, showing the effect of gate length scaling of a smaller effective mass material such as monolayer black phosphorus (BP) (\({m}_{x}^{\ast }\) = 0.15 m 0 , \({m}_{y}^{\ast }\) = 1.2 m 0 ) w.r.t. III–V ITRS 2013 HP and Extended Intel HP requirements. Full size image

Proposed Device Structures

To further enable the HP logic roadmap with ML BP FETs, we need to improve electrostatistics for sub-10 nm channel lengths with novel device designs. We propose device designs which address improving both 2D electrostatistics and direct source-to-drain (S/D) tunneling.

Improving 2-D Electrostatistics

We introduce a low-k interfacial layer (IL) between ML BP and High-k dielectric to reduce fringing fields due to the gate stack at shorter gate lengths14. As shown in Fig. 4a, by reducing fringing fields we improve both the gate control (i.e. slope of gate capacitance with gate voltage) and effective gate capacitance in ON state. Further, Fig. 4b shows that the performance of ML BP FETs at L G = 7.4 nm improves by more than 50% for the same effective-oxide-thickness (EOT) and physical thickness of the gate oxide (T OX ). For effective-oxide-thicknesses above 0.5 nm, we consider low-κ IL (SiO 2 ) to be between 0.4–0.6 nm and High-κ dielectric (HfO 2 , ZrO 2 , La 2 O 3 ) to be 1–1.5 nm thick. To meet both extended Intel HP and III-V ITRS 2013 HP delay requirement with the device structure having low-k IL, we can relax EOT requirements of the N3 technology node. Further, to see prospects of such gate stack with gate length scaling, we consider equivalent direct S/D tunneling probability i.e. ~exp (−L G · \({\sqrt{m}}_{x}^{\ast }\)) as shown in Fig. 4c. It shows that to achieve reasonable 2D electrostatistics below 4.5 nm gate length, we require EOT scaling below 0.5 nm irrespective of the direct S/D tunneling.

Figure 4 Effect of an interfacial layer (IL) with High-k dielectric, (a) On effective gate capacitance with gate voltage, (b) On performance (delay) of monolayer BP for N3 technology node i.e. L G = 7.4 nm in two different cases (i) with different EOT, and (ii) with varying physical oxide thickness for same EOT, (c) On the scalability of such gate-stack for different EOT considering equivalent direct source/drain tunneling. Full size image

Reducing Direct Source-to-Drain Tunneling

We consider different device concepts (as shown in Fig. 5a) which employ depletion at the source/drain extension-to-channel junction in OFF state, resulting in larger tunneling lengths by modifying the potential profile at the junctions. Although, underlap (UL) and junctionless (JL) 2D material based FETs have been shown to improve direct source-to-drain tunneling at scaled gate lengths15, such designs alone can’t provide required performance below 5 nm gate lengths as shown in Fig. 5b. To achieve the required performance for sub-5 nm gate lengths, we propose extended back-gate device architecture in conjunction with UL/JL FET, which makes it possible to meet the performance requirements till N0.7 (L G = 2.7 nm) for a fixed V DD , and EOT. It is important to note that due to back-gate overlap in the extended back-gate architecture, an extra parasitic capacitance component as gate overlap capacitance comes in picture which may affect the total capacitance scaling, thus delay and energy-delay scaling. Nevertheless, Fig. 5c shows the need to scale V DD to meet energy-delay requirement although the performance (delay) requirement is met till N0.7 for a fixed V DD .

Figure 5 Reducing direct S/D tunneling for N2 and beyond (a) Device structures showing extended back-gate (BG) with underlap (ULFET) and extended BG with junctionless doping profile. (JLFET) (b) Effect of different combination of device structures on performance of monolayer BP FET for N2 and beyond for fixed EOT and supply voltage, showing the need of extended back-gate with UL/JLFET for L G = 4.5 nm and beyond, (c) Delay and energy-delay product for extended BG UL/JFET (L UN = 2,3,4 nm for N1.5, N1, and N0.7 respectively) showing that although we meet the performance requirement for N1 and N0.7, the energy-delay product doesn’t scale. Full size image

Energy-Delay Optimization

As shown in Fig. 6a, it is very challenging to meet both energy-delay and delay requirement even for smaller supply voltages for N1.5 and beyond. On the other hand, we see that the EOT requirement for N1.5 can be relaxed as shown in Fig. 6b, while Fig. 6c shows that we need to scale EOT below 0.5 nm to meet N1 requirements which scales the supply voltage. As EOTs below 0.5 nm become challenging to achieve using High-k dielectric with IL layer; it requires the advent of two-dimensional oxides with higher dielectric constant, and higher tunneling barrier with ML BP.

Figure 6 Supply voltage for optimum energy delay product, (a) Effect of supply voltage on energy and delay for fixed EOT = 0.5 nm, and L G = 3.5, and 2.7 nm. (b) Effect of EOT scaling on energy-delay Vs delay plot for L G = 4.5 nm, (c) For L G = 3.5 nm, and L G = 2.7 nm. Full size image

Effect of contact resistance and scattering

Lastly, to understand the limit on different contact resistances and different ballitsic ratios, we first optimize the device structure consisting of High-κ with IL and extended back-gate with underlap for technology node N3. The device parameters are taken from Table 1 and the optimized L UN comes out to be 1 nm. As shown in Fig. 7a, both I ON and Nτ CP degrades by increasing contact resistance (R C ). We notice the upper limit of contact resistance to be 125 Ω-μm considering no scattering in the channel. Further, Fig. 7b,c show that for R C , ranging between 60 to 100 Ω-μm, we need to have ballisticity in the channel material between 85% to 60% respectively.