Micron has taped out its first 4th Generation 3D NAND memory devices with its new replacement gate (RG) architecture. The tape out confirms that the company is on track to produce commercial 4th Gen 3D NAND memory in calendar 2020, but Micron warns that memory using the new architecture will only be used for select applications and therefore its 3D NAND cost reductions next year will be minimal.

Micron’s 4th Gen 3D NAND uses up to 128 active layers and continues to use a CMOS under the array design approach. The new type of 3D NAND memory changes floating gate technology (that has been used by Intel and Micron for years) for gate replacement technology in an attempt to lower die size and costs while improving performance as well as enabling easier transitions to next-generation nodes. The technology was developed solely by Micron without any input from Intel, so it is likely tailored for applications that Micron wants to target the most (likely high ASPs, such as mobile, consumer, etc.).

The tape out of Micron’s 4th Gen 128-layer 3D NAND indicates that the company’s new design is more than just a concept. At the same time, Micron does not have plans to transit all of its product lines to its initial RG process technology, so its company-wide cost per-bit will not drop significantly next year. Nonetheless, the firm promises that it will see meaningful cost reductions in FY2021 (starts in late September, 2020) after its subsequent RG node is broadly deployed.

Right now, Micron is ramping up production of 96-layer 3D NAND and next year that will be used across the vast majority of its product lines. The 128-layer 3D NAND hardware will not bring significant per-bit costs declines immediately, but over time. A succeeding node (Micron’s 5th Gen 3D NAND?) is likely to feature at least 128 layers and if used widely, it will predictably lower the company’s per-bit costs substantially compared to today.

Sanjay Mehrotra, CEO and president of Micron, said the following:

“We achieved our first yielding dies using replacement gate or “RG” for short. This milestone further reduces the risk for our RG transition. As a reminder, our first RG node will be 128 layers and will be used for a select set of products. We don’t expect RG to deliver meaningful cost reductions until FY2021 when our second-generation RG node is broadly deployed. Consequently, we are expecting minimal cost reductions in NAND in FY2020. Our RG production deployment approach will optimize the ROI of our NAND capital investments.”

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Sources: Micron