Last month the CXL Specification 1.0 was released as a future cache coherent interconnect that uses the PCIe 5.0 physical infrastructure but aimed to provide a breakthrough in utility as well as cache coherency. At the time, the to-be-defined consortium consisted of Intel and eight other founding members. Since the announcement, membership has grown from that initial nine to thirty three, including some important names in the industry.

The Future Is In Interconnect

In August 2018, in coverage of AMD’s Infinity Fabric interconnect, I stated that the battle of the future would be on the front of the interconnect. Specifically relating to CPUs at the time, I said:

After core counts, the next battle will be on the interconnect. Low power, scalable, and high performance: process node scaling will mean nothing if the interconnect becomes 90% of the total chip power.

Fast forward a year later, and interconnect is still the hot topic when it comes to future design. Not only from CPU-to-CPU, but CPU-to-Device, and Device-to-Device, the ubiquity of the interconnect and the utility that each one offers is gearing up to be a battlefield. For non-coherent interconnects, at a system level, then PCIe is still the top player, but companies involved are looking to cache coherent options, such as CCIX, GenZ, and now CXL.

Compute Express Link, known as CXL, was launched last month. A fanfare was made as the standard had been building inside Intel for almost four years, and was now set to be an open standard built upon PCIe 5.0 infrastructure, allowing devices using CXL to have the same physical connection interface. The nine initial promotors of the CXL specification included industry heavy hitters: Alibaba, DellEMC, Facebook, Google, HPE, Huawei, Intel, and Microsoft, indicating that CXL is expecting to be a big part of the chip-to-chip portfolio for these companies, and it even has the support of the GenZ consortium. An official ‘CXL consortium’ has not been registered as of yet, however it is expected to be incorporated this year, with these nine companies at the helm.

Part of the announcement last month into the CXL 1.0 specification was to encourage new participants into the CXL standard. It has been designed as an open standard, and thus companies are willing to propose adjustments to future versions of the standard as well as build upon it without any licensing fees. We’re expecting the CXL technical specifications to be open in due course, as the technology is built upon.

One of the key elements to the announcement was the founders. Nine sizeable companies, each with interests in servers and accelerators, is more than the founding members when PCIe (5) or USB (7) started. There were some key names missing, however some of them have now signed up. The full list reads as follows:

Achronix Semiconductor Corp

*Alibaba Group

Arm

Ayar Labs

BlackFore Technologies LTD

Cadence Design Systems

*Cisco Systems

*DellEMC

DriveScale Inc.

Eidetic Communications Inc

*Facebook

Faraday Technology Company

Fastwel Group Ltd

GigaIO

*Google

*Hewlett Packard Enterprise

*Huawei

Inspur

*Intel

InterOperability Laboratory

Lenovo

Mellanox Technologies

Memsule Inc.

Microchip Technology Inc

*Microsoft

Mobiveil, Inc

Norel Systems LTD

Northwest Logic

Numascale AS

PLDA, Inc

SerialTek

SK Hynix

Synopsis

*Founding Members

The new highlights of this list include Arm, Cadence, Lenovo, Mellanox, SK Hynix, and Synopsis. Each of these companies has a high impact factor in the future of computing, either from a fundamental technical standpoint, implementation, or product line. It is interesting to note that Mellanox is a member, but NVIDIA isn’t, given that NVIDIA recently acquired the company. NVIDIA has its own NVLINK technology, however Mellanox’s product portfolio one suspects has to be open to new standards more than NVIDIA’s. Having SK Hynix as a member could be interesting for future memory offerings, and Arm as a member means that we could see any of Arm’s licensees perhaps looking into CXL technologies in the future.

As CXL 1.0 relies on PCIe 5.0, we’re going to have to wait until PCIe 5.0 comes to market before we see anything CXL related. However, a handy diagram from Intel at the CXL launch is a key one to remember regarding potential future CXL support. Intel recently held an Interconnect Day where CXL was explained in more detail. Unfortunately we were unable to attend, however we do have the slides and the notes, and will be going over them in due course.

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