Characteristics

Performance Efficiency: 3.34 CoreMark/MHz* and 1.25 /1.50 /1.89 DMIPS/MHz**

Arm Cortex-M3 Implementation Data***

180ULL

(7-track, typical 1.8v, 25°C) 90LP

(7-track, typical 1.2v, 25°C)

40LP

(9-track, typical 1.1v, 25°C)

Dynamic power 141 µW/MHz

31 µW/MHz

11 µW/MHz

Floor planned area

0.35 mm2

0.09 mm2

0.02 mm2



* See: EEMBC Benchmark Score Viewer

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K&R) v2.1 of Dhryston.

*** Minimum configuration with full ISA support and Interrupt Controller, includes 1 IRQ + NMI, excludes ETM, MPU and debug.