The International Solid-State Circuits Conference (ISSCC) is a yearly engineering conference where engineers from various companies gather to show off the latest and greatest circuit designs and breakthroughs. Several companies we regularly cover give presentations at ISSCC, and it’s not unusual for Intel or AMD to make technical announcements at the event.

This year, Intel is talking up its 14nm breakthroughs and highlighting its expectations for future sub-14nm scaling. The company’s path to a full 14nm ramp-up can be best characterized as “bumpy, but effective.” Intel’s 14nm shipments were delayed by 6-9 months depending on which product family you’re talking about, but the company did manage to hit superior process node characteristics compared to Samsung or TSMC. Gate lengths, pitches, and particularly SRAM scaling all offer more improvements and better characteristics.

Intel is predicting that it can continue to offer these improvements through to at least 10nm, with equivalent scaling and costs on track for that node. Tellingly, Intel has offered no timeline for when it might ship 10nm hardware. If Intel keeps to previous roadmaps, we’ll see 10nm hardware shipping in late 2016 or early 2017.

At 10nm and below, the path forward will become increasingly murky. What Intel has proposed is essentially a shift towards other types of cost-saving technologies and process adoptions rather than relying on strict lithography improvement. Intel also noted that it had learned from its 14nm implementation and expected a much faster ramp at 10nm — up to 50% faster, which would correct the abnormally long rollout time we saw at 14nm.

Next-generation manufacturing technologies under wraps

We’ve talked before about the near-term technologies that Intel might adapt for future nodes, from Extreme Ultraviolet lithography (EUV) to III-V wafers, to materials like carbon nanotubes, graphene, and nanowires. Intel isn’t saying much about which options it’s selecting for 10nm yet, but some of the companies 2014 presentations shed some light on this.

We know that Intel was investigating III-V materials several years ago, and reports from late last year suggest that EUV won’t be ready for the 14nm node. Full power sources remain frustratingly far away — noted lithography expert Chris Mack put together a presentation recently, illustrating that claims of a 100W machine (considered a minimum for volume EUV production) have been made since 2007 — literally eight years. EUV, once declared “necessary” for 45nm continues to operate in “Real Soon Now” mode.

EUV continues to nudge forward, with ASML reporting it has reached 4% conversion efficiency and is testing an 80W light source in house, but even TSMC, which recently took delivery of two advanced machines, is only planning a sub-10nm introduction.

Intel may be keeping its next-generation materials and lithography plans quiet, but the company does intend to push the envelope in other ways. 2.5D and 3D integration will be critical to the development of next-generation SoCs and the future of high-speed, low-power interfaces like those used in its MCDRAM interface.MCDRAM is a specialized application of the Hyper Memory Cube technology that Micron has been working on, and will debut in the Xeon Phi.

I’m going to be honest and admit that the specifics of an announcement like this are over my head, but the figure that stands out is the 5.9pJ/b 10Gb/s link. As we’ve discussed before, lowering the amount of energy consumed per data transfer is vital to the development of future exascale systems, and Intel’s claimed 5.9pJ/b is significantly better than existing rates. It’s not clear if this project is directly related to any of the company’s Xeon Phi work, but there’s going to be a certain amount of overlap between exascale computing projects and the development of low-power interfaces.

Overall, Intel is putting an optimistic face on its ability to continue scaling and hit performance and cost targets, with or without EUV. The company’s problems with 14nm may explain its more cautious approach to 10nm now, but its emphasis on integration and the use of 2.5D and 3D scaling seem to suggest that Santa Clara is taking the emphasis off material engineering and planning to use other forms of advancement to push the envelope at the 10nm node.