Hao Jun Liu

EECS Department

University of California, Berkeley

Technical Report No. UCB/EECS-2014-43

May 1, 2014

Field Programmable Gate Arrays (FPGAs) are effective in satisfying different computing requirements such as high performance computing, digital signal processing and embedded computing. Academic research efforts cover architecture optimization, design space exploration, circuit level design and new CAD algorithms. However, actual FPGA devices in common use are all commercial. In this work, we designed and implemented an open source FPGA with toolflow support. We named the project Archipelago and designed the architecture with two goals. First, it explores the quality of the physical implementation result that is produced by a standard ASIC design flow in a modern ASIC process. Second, it enables other people to use and extend the project at will. The outcome of this project is a parameterizable and user expandable FPGA with toolflow support. We verified its functionality. The performance of the work is good enough for real world work loads. A 64 Bit counter can run up to 364MHz on average on three different FPGA instances. The result is comparable to a commercial FPGA implemented in a similar process technology.

Advisor: John Wawrzynek

BibTeX citation:

@mastersthesis{Liu:EECS-2014-43, Author = {Liu, Hao Jun}, Title = {Archipelago - An Open Source FPGA with Toolflow Support}, School = {EECS Department, University of California, Berkeley}, Year = {2014}, Month = {May}, URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.html}, Number = {UCB/EECS-2014-43}, Abstract = {Field Programmable Gate Arrays (FPGAs) are effective in satisfying different computing requirements such as high performance computing, digital signal processing and embedded computing. Academic research efforts cover architecture optimization, design space exploration, circuit level design and new CAD algorithms. However, actual FPGA devices in common use are all commercial. In this work, we designed and implemented an open source FPGA with toolflow support. We named the project Archipelago and designed the architecture with two goals. First, it explores the quality of the physical implementation result that is produced by a standard ASIC design flow in a modern ASIC process. Second, it enables other people to use and extend the project at will. The outcome of this project is a parameterizable and user expandable FPGA with toolflow support. We verified its functionality. The performance of the work is good enough for real world work loads. A 64 Bit counter can run up to 364MHz on average on three different FPGA instances. The result is comparable to a commercial FPGA implemented in a similar process technology.} }

EndNote citation:

%0 Thesis %A Liu, Hao Jun %T Archipelago - An Open Source FPGA with Toolflow Support %I EECS Department, University of California, Berkeley %D 2014 %8 May 1 %@ UCB/EECS-2014-43 %U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-43.html %F Liu:EECS-2014-43