It’s pretty easy to go from talking about the earliest 24-layer 3D NAND to talking about the next-generation 32-layer 3D NAND, and then to progress through 48, 64, and more layers, but the amazing scale of a 96-layer part doesn’t really sink in when you just talk about numbers.

That’s why The Memory Guy was so charmed when Western Digital Corp. (WDC) invited me in for a briefing that gave me a more solid idea of how significant of a number 96 really is. The company brought along a plastic model that replicated the structure of its 96-layer BiCS NAND chip using clear plastic which was dramatically lighted from the inside.

WDC’s model was constructed using standard plastic sheeting, probably 1/8″ thick (~3mm), one sheet to represent the conductive polysilicon and one to represent the insulating silicon dioxide for each layer. Naturally, there are more than 96 layers in 96-layer NAND since there are source select transistors at the bottom and drain select transistors at the top. This adds a little bit to the layer count.

Another layer in the middle of the stack represented the break between the upper string and the lower string in this string-stacked design. In the end it became a pretty tall (and heavy) artistic replication of a very tiny sliver of a 96-layer chip.

The photo below provides a closer look without anyone blocking the view!

You can click on this picture to expand it and see a little more detail of how it was put together.

Each plastic sheet was drilled, and when the model was assembled plastic pipes and rods were inserted into the holes. This isn’t really the approach used to build BiCS NAND, though. When WDC makes a 3D NAND chip all of the holes are etched simultaneously through all layers and then materials are coated onto the walls of the holes. (Making hundreds of millions of silicon chips requires a significantly different process than is used to construct a 1-off model of a small portion of the array in plastic!)

Although I didn’t count the number of columns in this model, it appears to be a 4×8 grid, or 32 columns. A typical 3D NAND chip will have around 2 billion holes, or roughly 70 million times as many, and its layers will be around 60nm thick. Since this model is about a meter tall, then the underlying silicon wafer that was not included in the model, to be in proportion, would measure about 52 meters tall, or about the height of a 15-story building. All of these NAND layers really don’t make the silicon wafer that much thicker.

While this elaborate plastic model provides a very tangible understanding of the complexity of 3D NAND, it fades in comparison with a video that WDC’s Luca Fasoli showed during the same briefing, and which Western Digital graciously allowed me to post on this blog.

When presenting this video Fasoli admitted that it gave him vertigo. We think you’ll understand why!

Click the button to run this 45-second wonder and sit back to watch. It’s even better if you select the full-screen view.

Memory makers are already talking about producing 3D NAND with hundreds of layers, and perhaps in future years they will be able to produce 3D NAND with thousands of layers. Should that happen we can look back on this post in amusement. For now, though, we can look at 96 layer NAND in amazement!

Many thanks for the support of my friends at Western Digital for providing a copy of the video and allowing me to post it here.

If you would like to watch the full briefing, it can be viewed in Peter Foskett’s Tech Field Day video of the event.