OpenCores, the largest and most popular Gateware development community with over 300K members and 1200+ projects, is moving to GitLab. This is excellent news all around: as a catalyst for accelerating IP core development and for introducing GitLab to innovative uses in the scientific and electronic design communities.

About OpenCores and gateware

OpenCores is a repository of reusable units of logic, open to use as building blocks for the electronics design community. These units are most commonly known as Intellectual Property (IP) cores, and are described (coded), in Hardware Description Language (HDL) for the most part.

In the semiconductor industry, these are the basic constituents of advanced digital designs, collectively known as gateware: A layer in the electronics development chain positioned in between hardware (such as a Printed Circuit Board – PCB – or a packaged chip), and firmware (a set of decoded and executed instructions for a microprocessor).

The reference community for free and open source gateware IP cores

The OpenCores portal hosts the source code for a multitude of digital gateware projects. In its 20 years of web history, it has evolved into a platform that enables its user community to discover, showcase, and manage such projects, including revision control for source code.

The target devices for gateware have historically been FPGA (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits), which allow building a vast range of hardware digital electronics appliances. These are often described as SoC (System on a Chip).

In recent years, the portal has been particularly focused on hosting FPGA applications, with the intention to enlarge the pool of available cores based on emerging hardware description methods, such as HLS (High-level synthesis).

OpenCores is also the place where digital designers meet to showcase, promote, and talk about their passion and work. They do this through forums, news feeds, and much more!

Stewarded by Oliscience, supported by partners

Oliscience (open logic interconnects science) act as the stewards of the OpenCores community and its portal. Oliscience is an initiative originated from the CERN-Nikhef Business Incubation Centre (CERN-BIC@Nikhef), and is supported by Nikhef, the Dutch National Institute for Subatomic Physics, and ASTRON, the Netherlands Institute for Radio Astronomy.

As part of the stewardship charter, Oliscience is committed to maintaining and supporting the OpenCores portal. This mission involves globally promoting its community, fostering the use of open standards and practices, actively developing the portal infrastructure and content, and more. The Wishbone bus, used throughout OpenCores designs, is one of the most well-known examples.

Leading change and embracing the DevOps culture for Gateware development

Moore's law is slowing down, and the semiconductor industry is starting to experience a new resurgence. With a wave of new opportunities arising, FPGA is one of the key technologies that play a crucial role in the future of computing architectures.

The barrier to entry for becoming a gateway developer is fairly higher than learning a new programming language as a software developer. As such, the digital electronics industry is continually striving to simplify the approach to programmable logic.

Open Source IP Cores play a significant role in this goal. They unlock a vast knowledge pool that enables new gateware developers to start hacking on new projects straight away. They can use existing solutions to draw knowledge very quickly.

IP Cores strive for quality, and quality calls for a structured way to assess the content of a code bundle. This is where Continuous Verification (CV) comes into play.

In the context of programmable logic, CV is a workflow in which Gateware defined in a HDL runs against standardized testbenches and benchmarked to assess and rank its quality. Full coverage for test cases and failure corner cases is guaranteed.

Accelerating digital design with GitLab

The OpenCores community leaders have strong ties to CERN and the European Space Agency. Both are leading research organizations committed to supporting their respective scientific communities, which use GitLab for internal development.

Both organizations and the electronics industry in general are particularly interested in a better assessment of the quality of gateware products, as their usage in industrial and commercial applications continues to increase at an accelerated rate. When you launch a satellite into space, you can't just press the reset button if there is a bug!

While talking to those teams, and hearing the preliminary exploration of implementing CV practices into gateware design, GitLab's integral CI/CD features seemed a natural fit to pioneer the adoption of a DevOps approach to digital design.

Source control was also a feature that would enable engineers to share and collaborate on their code in the public space. In summary, the benefits of a single application for the entire DevOps cycle, with the ultimate goal of reducing the gateware design cycle time made the decision easy.

The next objective for the OpenCores team is to implement a CV process in the OpenCores portal, starting with FPGA and until ASICs. It's an ambitious one, which requires ambitious partners.

Andrea Borga, Oliscience CEO mentions:

we have a very strong scientific background, and we love to make experiments… all the time! Exploring new ideas, and striving for impeccable execution are embedded in our engineering way of thinking. You need innovative and ambitious partners to achieve equally innovative and ambitious goals. This is why we do what we do, and why we firmly believe GitLab's vision and spirit strongly align with our own. This is how we chose to go with them.

GitLab is thrilled to start working with the OpenCores team, to contribute to that goal and welcoming them to a community that leading Open Source projects such as Drupal, GNOME, KDE, Debian, Freedesktop and many more are already a part of.

Cover image by Fritzchens Fritz, licensed under CC0 1.0