https://icfp-fhpc17aec.hotcrp.com/

This year FHPC provides authors the opportunity to submit for evaluation any artifacts that accompany their papers. The dissemination of artifacts promotes reproducibility, and enables authors to build on top of each others’ work, while it can also help to more unambiguously resolve questions about cases not considered by the original authors.

For the purpose of FHPC, we plan to reward selected artifacts with additional presentation time in a dedicated slot during the workshop – for example for demonstrating (i) reproducibility of results or (ii) practical usage of the framework (visualization, demos, etc).

The artifact-evaluation committee (AEC) will accept any artifact that authors wish to submit. Obviously, the better the artifact is packaged, the more likely the AEC can actually work with it. We ask the authors to provide provide the title of the FHPC paper submission, together with three files:

a .pdf file that provides detailed instructions to the reviewers about how to install the artifact and what to look for in the evaluations

an archive .zip or .tar.gz containing the artifact

the submitted FHPC’17 paper (.pdf file)

The AE process is thought to encourage an open and constructive communication (by means HotCRP) between (anonymous) reviewers and authors.

Submission of an artifact does not contain tacit permission to make its content public. AEC members will be instructed that they may not publicise any part of your artifact during or after completing evaluation, nor retain any part of it after evaluation. Thus, you are free to include models, data files, proprietary binaries, and similar items in your artifact. The AEC organisers strongly encourage you to anonymise any data files that you submit.

(extended from 26th of May 2017)

Thursday Sept. 7th, 2017.

Please see ICFP 2017 web site at: https://icfp17.sigplan.org/

https://sites.google.com/site/fhpcworkshops/

The 6th ACM SIGPLAN Workshop on Functional High-Performance Computing workshop aims at bringing together researchers exploring uses of functional (or more generally, declarative or high-level) programming technology in application domains where high performance is essential. The aim of the meeting is to enable sharing of results, experiences, and novel ideas about how high-level, declarative specifications of computationally challenging problems can serve as maintainable and portable code that approaches (or even exceeds) the performance of machine-oriented (low-level) imperative implementations.

All aspects of performance critical programming and parallel programming are in-scope for the workshop, irrespective of hardware target. This includes both traditional large-scale scientific computing (HPC), as well as work targeting single node systems with SMPs, GPUs, FPGAs, or embedded processors. FHPC 2017 seeks to encourage a range of submissions, focusing on work in progress and facilitating early exchange of ideas and open discussion on innovative and/or emerging results. Experience reports are also welcome.