In this tutorial we will see how to design and test a VHDL component. We will start with a very simple block and gradually add features to it. We will also simulate it and test its output with Matlab. Over the process we will see: How to start with a simple block and gradually add features and improvementsHow to add a test bench (simulation)Adding parameters to a VHDL componentSaving the component data output to files (from simulation)Importing the files to Matlab in order to:Verify the results, andAnalyze the results (in this case, using FFT).The tutorial comprises three chapters, and it is divided into three entries of this blog. Make sure that you haven't missed to visit part 2 and part 3 of the tutorial!For this tutorial it is assumed that you already have basic knowledge of the VHDL language and know how to use simulation tools (We will use the Xilinx's Vivado built in simulator, but you can easily adapt the tutorial to other tools you may be familiar with).Chapter 1 - …