Andes Signed over 60 RISC-V IP License Contracts in the First Half of 2019 Serving Multiple Applications throughout Many Countries Worldwide

HSINCHU, TAIWAN – August 6, 2019 – Andes Technology Corporation, a leading supplier of outstanding efficiency, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced it achieved a record of 60 licensing agreements for its new family of RISC-V processors during the first half of 2019. After working in the CPU IP field for many years, Andes Technology joined the RISC-V Foundation as a founding member in 2016, while keeping innovating new high-quality RISC-V products. Now the design wins are going into a wide range of applications, including artificial intelligence designs, where RISC-V plays an important role. Other applications adopting RISC-V include ADAS, blockchain, communications, IoT security platform, FPGA, IoT, data center server applications, and solid-state storage devices.

In 2019, Andes launched more series of new RISC-V cores. It includes the innovative 32-bit A25MP and 64-bit AX25MP, multi-core processors supporting up to four CPU cores that provide efficient cache coherence among private level-1 caches. The A25MP and AX25MP also support Linux with complete DSP instruction set. In addition, Andes’ new 32-bit D25F is a low-power, high-performance core with DSP instruction set that serves DSP applications without Linux. Andes’ 32-bit A25 and 64-bit AX25 which support Linux and floating-point operations have also been upgraded to support the DSP instruction set. Andes’ popular 32-bit N22 provides flexible configurability and high efficiency. With its short 2-stage pipeline it achieves impressive performance of 3.95 CoreMark/MHz that makes it suitable in entry-level MCU applications such as small IoT and wearable devices. With years of experience in developing and supplying CPU IP, Andes Technology has accurately grasped the real needs of customers for RISC-V core processors and has achieved the greatest competitive advantage.

Because of features such as open-source ISA, compact, modular and extensible, RISC-V’s market potential has aroused widespread attention and future development. In China, with government support, many RISC-V enthusiasts are actively involved in developing a wide range of RISC-V applications. This RISC-V boom has accelerated industry acceptance and has generated a flourishing hardware and software RISC-V ecosystem. Andes’ customers have achieved significant technology advancements, such as integrating large numbers of CPU cores on a single chip for efficient multiplexed calculations in applications such as AI.

In the first half of 2019, Andes launched the RISC-V FreeStart program offering its commercial-grade CPU N22 RISC-V core with no upfront license fee. The fast and easy FreeStart authorization process has achieved record responses from the industry and academic institutions, and it will help proliferate the number and variety of RISC-V applications.

"The growth of the RISC-V market is only in its infancy,” stated Andes Technology President Frankwell Jyh-Ming Lin. “Our customers' applications are very diverse and include AI, IoT, ADAS, Netcom and consumer electronics. Customers choose Andes RISC-V solutions because of the technical support of its RISC-V products line, friendly interface and excellent products and solutions. Andes will continue to invest in developing RISC-V related products and environment, and work together with customers and partners to win new business opportunities.”

“Andes supports the technical and marketing committees of the RISC-V Foundation,” declared Andes CTO and Executive Vice President, Charlie Hong-Men Su. “In addition to contributing to the core technology and cooperating with the world's major companies to develop the RISC-V architecture, Andes leads the latest trends in RISC-V technology. Andes’ advantage is that designers can customize the RISC-V IP product to optimize the CPU IP and expand the function for further enhancement of the overall performance. Custom instruction extensions are easily added using Andes Custom Extension™ (ACE). In addition, Andes’s RISC-V customers can also avail themselves of Andes technology including StackSafe™ for hardware stack protection, CoDense™ for code size compression, PowerBrake for power management and the professional software development environment AndeSight™ IDE for acceleration SoC development.”

About Andes RISC-V Contributions

In addition to expanding its product line and application areas, Andes also actively participates in the RISC-V communities and promotes its diverse marketing activities. Andes has taken part in more than 30 industry events that promoting RISC-V technology around the world in the first half of 2019. RISC-V CON in Shanghai, Shenzhen, Beijing and Hsinchu is an annual series of RISC-V workshops. The attendees engaged with one another and conduct in-depth discussions with speakers. Andes also participated in other activities including the RISC-V Foundation RISC-V Workshop organized in Hsinchu and Zurich and the RISC-V one-day seminar in nine cities in the US and China. Andes joined TSMC OIP (Open Innovation Platform) Forum in Europe to speak about RISC-V applications implemented in TSMC processes. These activities promote potential customers' understanding of the RISC-V architecture and accelerate the expansion of the RISC-V ecosystem. RISC-V CON's series of activities will be held in Silicon Valley on October 15 and in Beijing on November 14 during the second half of 2019. The speaker partners include major RISC-V technology industry contributors, such as the expert from Amazon. RISC-V CON continues to bring the latest RISC-V trends to its expanding audience.





