Hi,

as part of porting coreboot to the HiFive Unleashed board, I would like to initialize the DDR RAM controller directly, rather than calling into FSBL. Section 20.3 of the FU540-C000 manual describes the sequence of that need to be performed, but it leaves out the values for the configuration registers at 0x100B0000-0x100B0424, 0x100B5200-0x100B52F8, and 0x100B4000-0x100B51FC, asking to “contact SiFive directly to determine the complete register settings for your application.”

I would like to know a set of register values that work on the HiFive Unleashed board, or a redistributable C/header file with these values, that could be included in a free software project such as coreboot.