The advisory says :

They are talking about level 2 page table, super page, paravirtualized guest and Xen invariants. We have to understand these notions.

Memory management, page table and super page

As stated in the advisory, only x86 guests are concerned. This paragraph describes the Memory Management Unit (MMU) of this architecture. The aim of the MMU is to translate virtual addresses (also named linear addresses) into physical addresses. This is done by using the well known segmentation and paging mechanisms.

While segmentation has already been described in the last post about the XSA-105 , paging is a little bit more complex and occurs right after the segmentation process.

There are three paging modes, which mainly differ in the sizes of the linear addresses that can be translated, the size of the physical address and the page size. We are going to talk only about the IA-32e mode, which is only available in Intel 64 architecture.

Basically, paging has a base table physical address in the CR3 register, the CPU takes some bits in the linear address to be converted which determines an entry in the current table and this entry gives the base physical address of the next table.

As you can see there are 4 levels of page table, which differ in their names in Xen, Linux and Intel terminology:

Xen Linux Intel L4 PGD PML4E L3 PUD PDPTE L2 PMD PDE L1 PTE PTE

We've tried to be consistent in the used terminology, however the three terminology can still be written within this blogpost.