With great help by user Michael Karcher we found the following details poking through the V6366 controller's innards:

# ports 102 (outside of V6366, the decoded I/O select line is called VDCS) Bit 5: 00: Plasma panel active 20: External monitor active 3d4 CRTC index port 3d5 CRTC data port (6845 compatible, except for "interlace & skew" register) 3d8 Mode control register 3d9 Color control register 3da status register 3dd index register 3de data register 3df 01: enable HGC graphics 02: page upper 32k HGC memory at B8000 and and enable B1000 to B7FFF 80: software protect, set to enable writing to 3dd and 3de # indexed registers: 20: no effect 21: number of 8-pixel-units clocked into the flat panel per line 22: vertical scroll (default: 0f). higher values scroll up 23: bit 0-6: hsync pulse delta for panel, in characters 24: bit 0-2: columns per character 00 6 pixels per character (doesn't sync!) 01 7 pixels per character (doesn't sync!) 02 8 pixels per character 03 9 pixels per character 04 10 pixels per character 05 blank screen 06 blank screen 07 same as 2 bit 3: 00 one attribute byte per character 08 three attribute bytes per character replaces every second pair of character with attribute bytes of unknown usage potentially for 16 bit character sets bit 4: (no effect in text mode) 00: standard CGA graphics mode 10: 16 colors 640 pixels, forces 16-bit memory interface bit 5: (no effect in text mode) 00: keep AD14 low 20: output RA1 as AD14 (needed for 640x400x2 or hercules graphics mode) bit 6-7: no effect 25: bit 0: clock select (external oscillator mode only) 00 14.318 MHz clock (X0) 01 18.000 MHz clock (X1) bit 1: oscillator mode 00 external oscillator, X1 is input for the second externally generated frequency 02 internal oscillator, X1 is crystal drive output bit 2: ? bit 3: ? bit 4: memory width 00: 16 bit 10: 8 bit bit 5: memory type 00: DRAM 20: SRAM bit 6: status register layout? 00: CGA status register at 3da 40: MDA status register at 3da bit 7: VSYNC? 00: CGA style VSYNC 80: MDA style VSYNC 26: bits 0,3,4: 19: set AD14 hi to select second 16k as video RAM bit 6: 00: pull down A15/GPE to limit addressable range to 16kB CGA memory 40: pull up A15/GPE to enable access to 16k RAM at BC00 27: bit 0: clock? 00: flickering 01: normal bit 1: hatching 00: no hatching rendered as black: black, green, red, brown rendered as white: blue, cyan, magenta, light grey intensity ignored 01: hatching bit 2: ? bit 3: ? bit 4: ? bit 5: ? bit 6-7: number of panel output bits 00: 1 bit serial 40: 2 bit parallel 80: 4 bit parallel (normal) C0: 8 bit parallel 28: bit 0-1: 00 screen off 01 normal 02 screen displayed twice with 40 columns each 03 garbled screen bit 3: ? bit 4: 00 panel shift clock polarity normal 10 panel shift clock polarity flipped (doesn't sync) bit 5: 00 vsync polarity normal 20 vsync polarity flipped bit 6: 00 hsync polarity flipped 40 hsync polarity normal bit 7: 00 hsync enabled during vsync? 80 hsync disabled during vsync? 29: bit 0-4: width of column 51 (plus the initial 8 pxiels) first 8 columns following are white, the rest black bit 6: 00 port 3df reads as c1 40 true readout of port 3df bit 7: 00 normal operation 80 system hangs with screen off 30--37: CRTC override values for text mode (3D8 bit 1 clear) 30: overrides CRTC 00 horizontal total 31: hsync delta, added to CRTC reg 02 32: vsync delta, added to CRTC reg 07 33: overrides CRTC 03 sync pulse width 34: overrides CRTC 04 vertical total 35: overrides CRTC 05 vertical total adjust 36: overrides CRTC 09 maximum total scanline address 37: bit 0-3: cursor position adjustment bit 4: similar to bit 3? bit 5-6: 00 no re-scan 20 re-scan every other line 40 re-scan overy other line (or 3/4 lines?) 60 re-scan every line (default for 640x400 panels) bit 7: 00 bits 0-3 adjust CRTC 0A and CRTC 0B ??? 80 bits 0-3 adjust only CRTC 0B ??? 38--3f: CRTC override values for graphics mode (3D8 bit 1 set) same as 30-37 # detection sequence (performed by TULIP diagnostics) out(0x3df, 0x80) out(0x3dd, 0x29) out(0x3de, 0x20) res = in(0x3df) out(0x3df, 0x03) return (res == 0xc1) # known machines with this chip # known register settings ## TULIP computer in "color emulation mode" The card imitates a CGA card, but outputs a MDA/Hercules video signal. All other modes do not alter power-on configuration of the V6366. 00: 00 00 03 60 03 60 02 60 08: 02 60 03 40 03 40 01 00 10: 04 00 07 60 07 60 06 60 18: 06 60 07 40 07 40 05 00 20: 00 00 00 00 03 95 00 2B 28: 01 20 00 00 00 00 00 00 30: 61 F8 FD 0F 19 06 0D 1B 38: 35 FF FD 07 79 02 01 2C Corresponding 6845 initialisation (real MDA values): 00: 61 50 52 0F 19 06 19 19 08: 02 0D 0B 0C 00 00 00 00 ## Schneider PC 7640 with Plasma 20: 00 4F 0F 1F 02 31 00 8B 28: 41 00 00 00 00 00 00 00 30: 59 DC FC 0A 19 00 07 60 38: 2C EE F0 0A 67 00 01 67 ## Schneider PC 7640 with external CGA screen 20: 00 00 00 00 02 30 00 08 28: 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 38: 00 00 00 00 00 00 00 07 ## Schneider PC 7640 CRTC initial values (80x25 text mode) 00: 71 50 5A 0A 1F 06 19 1C 08: 02 07 06 07 00 00 00 00 ## Schneider default palette The first 32 indexed registers provide color mapping for the flat panel. They are two entries (16 bits) per color. The palette setup function is at address F000:8997 in the BIOS. It always maps black to 00/00 and (bright) white to 01/00. Colors 1 to 7 are mapped to a rotation of the combinations 03/60, 02/60, 03/00, 03/20, 03/40, 02/40 and 01/00 (by default, in this order). Colors 8 to 14 are mapped to a rotation of 00/00, 03/60, 02/60, 03/00, 03/20, 03/40, 02/40 (by default, in this order). The rotation of the dark colors is determined by bits 0..2 of 40:C4, and the rotation of the bright colors is determined by bits 4..6 of 40:C4. 00: 00 00 03 60 02 60 03 00 08: 03 20 03 40 02 40 01 00 10: 00 00 03 60 02 60 03 00 18: 03 20 03 40 02 40 01 00 ## dither patterns TODO

It turns out the V6366 has a register compatible variant: the V6363 works the same way but does not support output to LCD panel. It is used in a TULIP graphics card from which register values were taken for guesses.

The following code then enables the 640x400 graphics mode:

mov dx, 3df mov al, 80 out dx, al ; unlock extended registers mov dx, 03dd mov ax, 073f out dx, ax ; set 3f to 07 (extra flags for graphics mode, undouble lines) mov ax, 033e out dx, ax ; set 3e to 03 (maximum scan line override for graphics mode) mov ax, 2224 out dx, ax ; set 24 to 22 (640x400 mode with two extra banks at bc00:0000) mov ax, 4026 out dx, ax ; set 26 to 40 (map high 16k display RAM to bc00:0000)

Then enable mode 6. To undo this, restore all registers to their initial values. The memory layout in this mode is like the default CGA 640x200 memory layout, except two extra memory banks appear at BC00:0000 with the same layout as the normal memory banks. It appears that lines are read in sets of four from these memory banks with lines coming in turn from segment B800 , BA00 , bC00 , and BE00 .

We have also found how to enable an 80x50 text mode:

mov ax, 3 int 10 ; enter mode 3 mov dx, 3df mov al, 80 out dx, al ; unlock extended registers dec dx dec dx ; set dx = 3dd (V6366 registers) mov ax, 0037 out dx, ax ; set 37 to 00 (extra flags for text mode, undouble lines) mov ax, 3334 out dx, ax ; set 34 to 33 (vertical total override) mov dx, 3d4 ; select CRTC registers mov ax, 3206 out dx, ax ; set CRTC 06 to 32 mov ax, 3407 out dx, ax ; set CRTC 07 to 34 ret

The font ROM on the PC7640 contains both an 8x16 and an 8x8 font, but is wired such that the VDCS line (selects the external monitor) also selects the 8x8 font. In addition, the use of an 8x16 font is only achieved through an external flip-flop toggled with every scan line. None of these details are apparent from the circuit diagrams as the relevant address lines have been wired up with bodge wires to some spare flip flops.

Thus the 80x50 mode is barely usable.

As a demonstration, I am now going to try and add this graphics mode to Fractint to get some sample output.