To demonstrate the unique ability to run very large enterprise HPC clusters and workloads, Univa leveraged AWS to deploy 1,015,022 cores in a single Univa Grid Engine cluster to showcase the advantages of running large-scale electronic design automation (EDA) workloads in the cloud. The cluster was built in approximately 2.5 hours using Navops Launch automation and comprised more than 55,000 AWS instances in 3 availability zones, 16 different instance types and leveraged AWS Spot Fleet technology to maximize the rate at which Amazon EC2 hosts were launched while enabling capacity and costs to be managed according to policy.

It is no secret that many large organizations have an insatiable appetite for computing power. With large clusters, the challenge is not just building the cluster – rather it is building it quickly and reliably using full automation. Navops Launch can provision and manage both virtual and bare-metal environments and includes a cloud-specific adapter for Amazon EC2. Navops Launch policy automation enables organizations to dynamically create, scale, and tear-down cloud-based infrastructure in response to changing workload demand.

Million core clusters are not entirely new, but clusters at this scale are rarer than one might think. Only four clusters on the global Top500 feature more than 1,000,000 cores, and all of these owe their large core counts to GPUs or many-core processor designs. To put things in perspective, the recently announced ORNL Summit Supercomputer (regarded as the world’s largest) has 202,750 Power9 cores (excluding cores on the Nvidia Volta GPUs). Conventional processor core counts are more representative of the scale of the provisioning and workload management challenges in fields like Electronic Design and Automation (EDA), Life Sciences or Financial Services.

Whether in life sciences, deep learning, or semiconductor design, building quality products and getting to market fast often demands extensive computer simulation. Enterprises compete in-part based on the scale, performance, and cost-efficiency of their high-performance computing (HPC) environments.

In chip design, device validation and regression testing are massively compute-intensive operations. Modern VLSI and system on a chip (SoC) designs are comprised of millions of gates, and any minor design change requires that millions of digital and analog simulations be re-run to ensure that the device continues to function and has not “regressed”. With tape out costs in the range of 10-15 million dollars[1], organizations cannot afford to make a mistake in device design and verification.

Owing to the cyclical nature of chip design projects where large clusters are often needed for a short time, cloud environments are becoming a compelling environment for EDA workloads. With advances in cloud offerings and more cloud-friendly licensing models from software vendors, the barriers to running in the cloud are falling away.

Users that want to get started with Univa Grid Engine and Navops Launch on AWS can try the software on the AWS Marketplace or learn more by visiting the Univa Grid Engine AWS Marketplace resource page. You can also visit univa.com for additional information

For those attending ISC High Performance 2018 in Frankfurt Germany, you are welcome to join our breakfast briefing HPC in the Cloud co-hosted by Univa, Nvidia and Amazon Web Services on June 27th, 2018 at 8:00 AM. During this session you will learn about real-world cases and obtain practical advice for migrating HPC applications to the cloud. You can also visit Univa at booth D-1021 or AWS at booth A-1351 during ISC.

[1] 2017 Estimate based on 7nm process technology – https://www.quora.com/How-much-does-an-integrated-circuit-chip-tape-out-cost