GCC 5 Release Series

Changes, New Features, and Fixes

Caveats

The default mode for C is now -std=gnu11 instead of -std=gnu89 .

instead of . The C++ runtime library (libstdc++) uses a new ABI by default (see below).

The Graphite framework for loop optimizations no longer requires the CLooG library, only ISL version 0.14 (recommended) or 0.12.2. The installation manual contains more information about requirements to build GCC.

The non-standard C++0x type traits has_trivial_default_constructor , has_trivial_copy_constructor and has_trivial_copy_assign have been deprecated and will be removed in a future version. The standard C++11 traits is_trivially_default_constructible , is_trivially_copy_constructible and is_trivially_copy_assignable should be used instead.

, and have been deprecated and will be removed in a future version. The standard C++11 traits , and should be used instead. On AVR, support has been added for the devices ATtiny4/5/9/10/20/40. This requires Binutils 2.25 or newer.

The AVR port uses a new scheme to describe supported devices: For each supported device the compiler provides a device-specific spec file. If the compiler is used together with AVR-LibC, this requires at least GCC 5.2 and a version of AVR-LibC which implements feature #44574.

General Optimizer Improvements

Inter-procedural optimization improvements: An Identical Code Folding (ICF) pass (controlled via -fipa-icf ) has been added. Compared to the identical code folding performed by the Gold linker this pass does not require function sections. It also performs merging before inlining, so inter-procedural optimizations are aware of the code re-use. On the other hand not all unifications performed by a linker are doable by GCC which must honor aliasing information. During link-time optimization of Firefox, this pass unifies about 31000 functions, that is 14% overall. The devirtualization pass was significantly improved by adding better support for speculative devirtualization and dynamic type detection. About 50% of virtual calls in Firefox are now speculatively devirtualized during link-time optimization. A new comdat localization pass allows the linker to eliminate more dead code in presence of C++ inline functions. Virtual tables are now optimized. Local aliases are used to reduce dynamic linking time of C++ virtual tables on ELF targets and data alignment has been reduced to limit data segment bloat. A new -fno-semantic-interposition option can be used to improve code quality of shared libraries where interposition of exported symbols is not allowed. Write-only variables are now detected and optimized out. With profile feedback the function inliner can now bypass --param inline-insns-auto and --param inline-insns-single limits for hot calls. The IPA reference pass was significantly sped up making it feasible to enable -fipa-reference with -fprofile-generate . This also solves a bottleneck seen when building Chromium with link-time optimization. The symbol table and call-graph API was reworked to C++ and simplified. The interprocedural propagation of constants now also propagates alignments of pointer parameters. This for example means that the vectorizer often does not need to generate loop prologues and epilogues to make up for potential misalignments.

Link-time optimization improvements: One Definition Rule based merging of C++ types has been implemented. Type merging enables better devirtualization and alias analysis. Streaming extra information needed to merge types adds about 2-6% of memory size and object size increase. This can be controlled by -flto-odr-type-merging . Command-line optimization and target options are now streamed on a per-function basis and honored by the link-time optimizer. This change makes link-time optimization a more transparent replacement of per-file optimizations. It is now possible to build projects that require different optimization settings for different translation units (such as -ffast-math , -mavx , or -finline ). Contrary to earlier GCC releases, the optimization and target options passed on the link command line are ignored. Note that this applies only to those command-line options that can be passed to optimize and target attributes. Command-line options affecting global code generation (such as -fpic ), warnings (such as -Wodr ), optimizations affecting the way static variables are optimized (such as -fcommon ), debug output (such as -g ), and --param parameters can be applied only to the whole link-time optimization unit. In these cases, it is recommended to consistently use the same options at both compile time and link time. GCC bootstrap now uses slim LTO object files. Memory usage and link times were improved. Tree merging was sped up, memory usage of GIMPLE declarations and types was reduced, and, support for on-demand streaming of variable constructors was added.

Feedback directed optimization improvements: A new auto-FDO mode uses profiles collected by low overhead profiling tools (perf) instead of more expensive program instrumentation (via -fprofile-generate ). SPEC2006 benchmarks on x86-64 improve by 4.7% with auto-FDO and by 7.3% with traditional feedback directed optimization. Profile precision was improved in presence of C++ inline and extern inline functions. The new gcov-tool utility allows manipulating profiles. Profiles are now more tolerant to source file changes (this can be controlled by --param profile-func-internal-id ).

Register allocation improvements: A new local register allocator (LRA) sub-pass, controlled by -flra-remat , implements control-flow sensitive global register rematerialization. Instead of spilling and restoring a register value, it is recalculated if it is profitable. The sub-pass improved SPEC2000 generated code by 1% and 0.5% correspondingly on ARM and x86-64. Reuse of the PIC hard register, instead of using a fixed register, was implemented on x86/x86-64 targets. This improves generated PIC code performance as more hard registers can be used. Shared libraries can significantly benefit from this optimization. Currently it is switched on only for x86/x86-64 targets. As RA infrastructure is already implemented for PIC register reuse, other targets might follow this in the future. A simple form of inter-procedural RA was implemented. When it is known that a called function does not use caller-saved registers, save/restore code is not generated around the call for such registers. This optimization can be controlled by -fipa-ra LRA is now much more effective at generating spills of general registers into vector registers instead of memory on architectures (e.g., modern Intel processors) where this is profitable.

UndefinedBehaviorSanitizer gained a few new sanitization options: -fsanitize=float-divide-by-zero : detect floating-point division by zero; -fsanitize=float-cast-overflow : check that the result of floating-point type to integer conversions do not overflow; -fsanitize=bounds : enable instrumentation of array bounds and detect out-of-bounds accesses; -fsanitize=alignment : enable alignment checking, detect various misaligned objects; -fsanitize=object-size : enable object size checking, detect various out-of-bounds accesses. -fsanitize=vptr : enable checking of C++ member function calls, member accesses and some conversions between pointers to base and derived classes, detect if the referenced object does not have the correct dynamic type.

Pointer Bounds Checker, a bounds violation detector, has been added and can be enabled via -fcheck-pointer-bounds . Memory accesses are instrumented with run-time checks of used pointers against their bounds to detect pointer bounds violations (overflows). The Pointer Bounds Checker is available on x86/x86-64 GNU/Linux targets with a new ISA extension Intel MPX support. See the Pointer Bounds Checker Wiki page for more details.

New Languages and Language specific improvements

OpenMP 4.0 specification offloading features are now supported by the C, C++, and Fortran compilers. Generic changes: Infrastructure (suitable for any vendor). Testsuite which covers offloading from the OpenMP 4.0 Examples document. Specific for upcoming Intel Xeon Phi products: Run-time library. Card emulator.

Specific for upcoming Intel Xeon Phi products: GCC 5 includes a preliminary implementation of the OpenACC 2.0a specification. OpenACC is intended for programming accelerator devices such as GPUs. See the OpenACC wiki page for more information.

C family

The default setting of the -fdiagnostics-color= command-line option is now configurable when building GCC using configuration option --with-diagnostics-color= . The possible values are: never , always , auto and auto-if-env . The new default auto uses color only when the standard error is a terminal. The default in GCC 4.9 was auto-if-env , which is equivalent to auto if there is a non-empty GCC_COLORS environment variable, and never otherwise. As in GCC 4.9, an empty GCC_COLORS variable in the environment will always disable colors, no matter what the default is or what command-line options are used.

command-line option is now configurable when building GCC using configuration option . The possible values are: , , and . The new default uses color only when the standard error is a terminal. The default in GCC 4.9 was , which is equivalent to if there is a non-empty environment variable, and otherwise. As in GCC 4.9, an empty variable in the environment will always disable colors, no matter what the default is or what command-line options are used. A new command-line option -Wswitch-bool has been added for the C and C++ compilers, which warns whenever a switch statement has an index of boolean type.

has been added for the C and C++ compilers, which warns whenever a statement has an index of boolean type. A new command-line option -Wlogical-not-parentheses has been added for the C and C++ compilers, which warns about "logical not" used on the left hand side operand of a comparison.

has been added for the C and C++ compilers, which warns about "logical not" used on the left hand side operand of a comparison. A new command-line option -Wsizeof-array-argument has been added for the C and C++ compilers, which warns when the sizeof operator is applied to a parameter that has been declared as an array in a function definition.

has been added for the C and C++ compilers, which warns when the operator is applied to a parameter that has been declared as an array in a function definition. A new command-line option -Wbool-compare has been added for the C and C++ compilers, which warns about boolean expressions compared with an integer value different from true / false .

has been added for the C and C++ compilers, which warns about boolean expressions compared with an integer value different from / . Full support for Cilk Plus has been added to the GCC compiler. Cilk Plus is an extension to the C and C++ languages to support data and task parallelism.

A new attribute no_reorder prevents reordering of selected symbols against other such symbols or inline assembler. This enables to link-time optimize the Linux kernel without having to resort to -fno-toplevel-reorder that disables several optimizations.

prevents reordering of selected symbols against other such symbols or inline assembler. This enables to link-time optimize the Linux kernel without having to resort to that disables several optimizations. New preprocessor constructs, __has_include and __has_include_next , to test the availability of headers have been added.

This demonstrates a way to include the header <optional> only if it is available:

#ifdef __has_include # if __has_include(<optional>) # include <optional> # define have_optional 1 # elif __has_include(<experimental/optional>) # include <experimental/optional> # define have_optional 1 # define experimental_optional # else # define have_optional 0 # endif #endif The header search paths for __has_include and __has_include_next are equivalent to those of the standard directive #include and the extension #include_next respectively.

and , to test the availability of headers have been added. This demonstrates a way to include the header only if it is available: The header search paths for and are equivalent to those of the standard directive and the extension respectively. A new built-in function-like macro to determine the existence of an attribute, __has_attribute , has been added. The equivalent built-in macro __has_cpp_attribute was added to C++ to support Feature-testing recommendations for C++. The macro __has_attribute is added to all C-like languages as an extension: int #ifdef __has_attribute # if __has_attribute(__noinline__) __attribute__((__noinline__)) # endif #endif foo(int x); If an attribute exists, a nonzero constant integer is returned. For standardized C++ attributes a date is returned, otherwise the constant returned is 1. Both __has_attribute and __has_cpp_attribute will add underscores to an attribute name if necessary to resolve the name. For C++11 and onwards the attribute may be scoped.

, has been added. The equivalent built-in macro was added to C++ to support Feature-testing recommendations for C++. The macro is added to all C-like languages as an extension: If an attribute exists, a nonzero constant integer is returned. For standardized C++ attributes a date is returned, otherwise the constant returned is 1. Both and will add underscores to an attribute name if necessary to resolve the name. For C++11 and onwards the attribute may be scoped. A new set of built-in functions for arithmetics with overflow checking has been added: __builtin_add_overflow , __builtin_sub_overflow and __builtin_mul_overflow and for compatibility with clang also other variants. These builtins have two integral arguments (which don't need to have the same type), the arguments are extended to infinite precision signed type, + , - or * is performed on those, and the result is stored in an integer variable pointed to by the last argument. If the stored value is equal to the infinite precision result, the built-in functions return false , otherwise true . The type of the integer variable that will hold the result can be different from the types of the first two arguments. The following snippet demonstrates how this can be used in computing the size for the calloc function: void * calloc (size_t x, size_t y) { size_t sz; if (__builtin_mul_overflow (x, y, &sz)) return NULL; void *ret = malloc (sz); if (ret) memset (res, 0, sz); return ret; } On e.g. i?86 or x86-64 the above will result in a mul instruction followed by a jump on overflow.

, and and for compatibility with clang also other variants. These builtins have two integral arguments (which don't need to have the same type), the arguments are extended to infinite precision signed type, , or is performed on those, and the result is stored in an integer variable pointed to by the last argument. If the stored value is equal to the infinite precision result, the built-in functions return , otherwise . The type of the integer variable that will hold the result can be different from the types of the first two arguments. The following snippet demonstrates how this can be used in computing the size for the function: On e.g. i?86 or x86-64 the above will result in a instruction followed by a jump on overflow. The option -fextended-identifiers is now enabled by default for C++, and for C99 and later C versions. Various bugs in the implementation of extended identifiers have been fixed.

C

The default mode has been changed to -std=gnu11 .

. A new command-line option -Wc90-c99-compat has been added to warn about features not present in ISO C90, but present in ISO C99.

has been added to warn about features not present in ISO C90, but present in ISO C99. A new command-line option -Wc99-c11-compat has been added to warn about features not present in ISO C99, but present in ISO C11.

has been added to warn about features not present in ISO C99, but present in ISO C11. It is possible to disable warnings about conversions between pointers that have incompatible types via a new warning option -Wno-incompatible-pointer-types ; warnings about implicit incompatible integer to pointer and pointer to integer conversions via a new warning option -Wno-int-conversion ; and warnings about qualifiers on pointers being discarded via a new warning option -Wno-discarded-qualifiers .

; warnings about implicit incompatible integer to pointer and pointer to integer conversions via a new warning option ; and warnings about qualifiers on pointers being discarded via a new warning option . To allow proper use of const qualifiers with multidimensional arrays, GCC will not warn about incompatible pointer types anymore for conversions between pointers to arrays with and without const qualifier (except when using -pedantic ). Instead, a new warning is emitted only if the const qualifier is lost. This can be controlled with a new warning option -Wno-discarded-array-qualifiers .

). Instead, a new warning is emitted only if the const qualifier is lost. This can be controlled with a new warning option . The C front end now generates more precise caret diagnostics.

The -pg command-line option now only affects the current file in an LTO build.

C++

G++ now supports C++14 variable templates.

-Wnon-virtual-dtor doesn't warn anymore for final classes.

doesn't warn anymore for classes. Excessive template instantiation depth is now a fatal error. This prevents excessive diagnostics that usually do not help to identify the problem.

G++ and libstdc++ now implement the feature-testing macros from Feature-testing recommendations for C++.

G++ now allows typename in a template template parameter. template<template<typename> typename X> struct D; // OK

in a template template parameter. G++ now supports C++14 aggregates with non-static data member initializers. struct A { int i, j = i; }; A a = { 42 }; // a.j is also 42

G++ now supports C++14 extended constexpr . constexpr int f (int i) { int j = 0; for (; i > 0; --i) ++j; return j; } constexpr int i = f(42); // i is 42

. G++ now supports the C++14 sized deallocation functions. void operator delete (void *, std::size_t) noexcept; void operator delete[] (void *, std::size_t) noexcept;

A new One Definition Rule violation warning (controlled by -Wodr ) detects mismatches in type definitions and virtual table contents during link-time optimization.

) detects mismatches in type definitions and virtual table contents during link-time optimization. New warnings -Wsuggest-final-types and -Wsuggest-final-methods help developers to annotate programs with final specifiers (or anonymous namespaces) to improve code generation. These warnings can be used at compile time, but they are more useful in combination with link-time optimization.

and help developers to annotate programs with specifiers (or anonymous namespaces) to improve code generation. These warnings can be used at compile time, but they are more useful in combination with link-time optimization. G++ no longer supports N3639 variable length arrays, as they were removed from the C++14 working paper prior to ratification. GNU VLAs are still supported, so VLA support is now the same in C++14 mode as in C++98 and C++11 modes.

G++ now allows passing a non-trivially-copyable class via C varargs, which is conditionally-supported with implementation-defined semantics in the standard. This uses the same calling convention as a normal value parameter.

G++ now defaults to -fabi-version=9 and -fabi-compat-version=2 . So various mangling bugs are fixed, but G++ will still emit aliases with the old, wrong mangling where feasible. -Wabi=2 will warn about differences between ABI version 2 and the current setting.

and . So various mangling bugs are fixed, but G++ will still emit aliases with the old, wrong mangling where feasible. will warn about differences between ABI version 2 and the current setting. G++ 5.2 fixes the alignment of std::nullptr_t . Most code is likely to be unaffected, but -Wabi=8 will warn about a non-static data member with type std::nullptr_t which changes position due to this change.

Runtime Library (libstdc++)

A Dual ABI is provided by the library. A new ABI is enabled by default. The old ABI is still supported and can be used by defining the macro _GLIBCXX_USE_CXX11_ABI to 0 before including any C++ standard library headers.

to before including any C++ standard library headers. A new implementation of std::string is enabled by default, using the small string optimization instead of copy-on-write reference counting.

is enabled by default, using the small string optimization instead of copy-on-write reference counting. A new implementation of std::list is enabled by default, with an O(1) size() function;

is enabled by default, with an O(1) function; Full support for C++11, including the following new features: std::deque and std::vector<bool> meet the allocator-aware container requirements; movable and swappable iostream classes; support for std::align and std::aligned_union ; type traits std::is_trivially_copyable , std::is_trivially_constructible , std::is_trivially_assignable etc.; I/O manipulators std::put_time , std::get_time , std::hexfloat and std::defaultfloat ; generic locale-aware std::isblank ; locale facets for Unicode conversion; atomic operations for std::shared_ptr ; std::notify_all_at_thread_exit() and functions for making futures ready at thread exit.

Support for the C++11 hexfloat manipulator changes how the num_put facet formats floating point types when ios_base::fixed|ios_base::scientific is set in a stream's fmtflags . This change affects all language modes, even though the C++98 standard gave no special meaning to that combination of flags. To prevent the use of hexadecimal notation for floating point types use str.unsetf(std::ios_base::floatfield) to clear the relevant bits in str.flags() .

manipulator changes how the facet formats floating point types when is set in a stream's . This change affects all language modes, even though the C++98 standard gave no special meaning to that combination of flags. To prevent the use of hexadecimal notation for floating point types use to clear the relevant bits in . Full experimental support for C++14, including the following new features: std::is_final type trait; heterogeneous comparison lookup in associative containers. global functions cbegin , cend , rbegin , rend , crbegin , and crend for range access to containers, arrays and initializer lists.

Improved experimental support for the Library Fundamentals TS, including: class std::experimental::any ; function template std::experimental::apply ; function template std::experimental::sample ; function template std::experimental::search and related searcher types; variable templates for type traits; function template std::experimental::not_fn .

New random number distributions logistic_distribution and uniform_on_sphere_distribution as extensions.

and as extensions. GDB Xmethods for containers and std::unique_ptr .

Fortran

Compatibility notice: The version of the module files (.mod) has been incremented. For free-form source files -Werror=line-truncation is now enabled by default. Note that comments exceeding the line length are not diagnosed. (For fixed-form source code, the same warning is available but turned off by default, such that excess characters are ignored. -ffree-line-length-n and -ffixed-line-length-n can be used to modify the default line lengths of 132 and 72 columns, respectively.) The -Wtabs option is now more sensible: with -Wtabs the compiler warns if it encounters tabs and with -Wno-tabs this warning is turned off. Before, -Wno-tabs warned and -Wtabs disabled the warning. As before, this warning is also enabled by -Wall , -pedantic and the f95 , f2003 , f2008 and f2008ts options of -std= .

Incomplete support for colorizing diagnostics emitted by gfortran has been added. The option -fdiagnostics-color controls when color is used in diagnostics. The default value of this option can be configured when building GCC. The GCC_COLORS environment variable can be used to customize the colors or disable coloring completely. Sample diagnostics output:

$ gfortran -fdiagnostics-color=always -Wuse-without-only test.f90 test.f90:6:1: 0 continue 1 Error: Zero is not a valid statement label at (1) test.f90:9:6: USE foo 1 Warning: USE statement at (1) has no ONLY qualifier [-Wuse-without-only]

controls when color is used in diagnostics. The default value of this option can be configured when building GCC. The environment variable can be used to customize the colors or disable coloring completely. Sample diagnostics output: The -Wuse-without-only option has been added to warn when a USE statement has no ONLY qualifier and thus implicitly imports all public entities of the used module.

option has been added to warn when a statement has no qualifier and thus implicitly imports all public entities of the used module. Formatted READ and WRITE statements now work correctly in locale-aware programs. For more information and potential caveats, see Section 5.3 Thread-safety of the runtime library in the manual.

and statements now work correctly in locale-aware programs. For more information and potential caveats, see Section 5.3 Thread-safety of the runtime library in the manual. Fortran 2003: The intrinsic IEEE modules ( IEEE_FEATURES , IEEE_EXCEPTIONS and IEEE_ARITHMETIC ) are now supported.

Fortran 2008: Coarrays: Full experimental support of Fortran 2008's coarrays with -fcoarray=lib except for allocatable/pointer components of derived-type coarrays. GCC currently only ships with a single-image library ( libcaf_single ), but multi-image support based on MPI and GASNet is provided by the libraries of the OpenCoarrays project.

TS18508 Additional Parallel Features in Fortran: Support for the collective intrinsic subroutines CO_MAX , CO_MIN , CO_SUM , CO_BROADCAST and CO_REDUCE has been added, including -fcoarray=lib support. Support for the new atomic intrinsics has been added, including -fcoarray=lib support.

Fortran 2015: Support for IMPLICIT NONE (external, type) . ERROR STOP is now permitted in pure procedures.



Go

GCC 5 provides a complete implementation of the Go 1.4.2 release.

Building GCC 5 with Go enabled will install two new programs: go and gofmt.

libgccjit

New in GCC 5 is the ability to build GCC as a shared library for embedding in other processes (such as interpreters), suitable for Just-In-Time compilation to machine code.

The shared library has a C API and a C++ wrapper API providing some "syntactic sugar". There are also bindings available from 3rd parties for Python and for D.

For example, this library can be used by interpreters for compiling functions from bytecode to machine code.

The library can also be used for ahead-of-time compilation, enabling GCC to be plugged into a pre-existing front end. An example of using this to build a compiler for an esoteric language we'll refer to as "brainf" can be seen here.

libgccjit is licensed under the GPLv3 (or at your option, any later version)

It should be regarded as experimental at this time.

New Targets and Target Specific Improvements

Reporting stack usage

The BFIN, FT32, H8300, IQ2000 and M32C targets now support the -fstack-usage option.

AArch64

Code generation for the ARM Cortex-A57 processor has been improved. A more accurate instruction scheduling model for the processor is now used, and a number of compiler tuning parameters have been set to offer increased performance when compiling with -mcpu=cortex-a57 or -mtune=cortex-a57 .

or . A workaround for the ARM Cortex-A53 erratum 835769 has been added and can be enabled by giving the -mfix-cortex-a53-835769 option. Alternatively it can be enabled by default by configuring GCC with the --enable-fix-cortex-a53-835769 option.

option. Alternatively it can be enabled by default by configuring GCC with the option. The optional cryptographic extensions to the ARMv8-A architecture are no longer enabled by default when specifying the -mcpu=cortex-a53 , -mcpu=cortex-a57 or -mcpu=cortex-a57.cortex-a53 options. To enable these extensions add +crypto to the value of -mcpu or -march e.g. -mcpu=cortex-a53+crypto .

, or options. To enable these extensions add to the value of or e.g. . Support has been added for the following processors (GCC identifiers in parentheses): ARM Cortex-A72 ( cortex-a72 ) and initial support for its big.LITTLE combination with the ARM Cortex-A53 ( cortex-a72.cortex-a53 ), Cavium ThunderX ( thunderx ), Applied Micro X-Gene 1 ( xgene1 ), and Samsung Exynos M1 ( exynos-m1 ). The GCC identifiers can be used as arguments to the -mcpu or -mtune options, for example: -mcpu=xgene1 or -mtune=cortex-a72.cortex-a53 . Using -mcpu=cortex-a72 requires a version of GNU binutils that has support for the Cortex-A72.

) and initial support for its big.LITTLE combination with the ARM Cortex-A53 ( ), Cavium ThunderX ( ), Applied Micro X-Gene 1 ( ), and Samsung Exynos M1 ( ). The GCC identifiers can be used as arguments to the or options, for example: or . Using requires a version of GNU binutils that has support for the Cortex-A72. The transitional options -mlra and -mno-lra have been removed. The AArch64 backend now uses the local register allocator (LRA) only.

ARM

Thumb-1 assembly code is now generated in unified syntax. The new option -masm-syntax-unified specifies whether inline assembly code is using unified syntax. By default the option is off which means non-unified syntax is used. However this is subject to change in future releases. Eventually the non-unified syntax will be deprecated.

specifies whether inline assembly code is using unified syntax. By default the option is off which means non-unified syntax is used. However this is subject to change in future releases. Eventually the non-unified syntax will be deprecated. It is now a configure-time error to use the --with-cpu configure option with either of --with-tune or --with-arch .

configure option with either of or . Code generation for the ARM Cortex-A57 processor has been improved. A more accurate instruction scheduling model for the processor is now used, and a number of compiler tuning parameters have been set to offer increased performance when compiling with -mcpu=cortex-a57 or -mtune=cortex-a57 .

or . Support has been added for the following processors (GCC identifiers in parentheses): ARM Cortex-A17 ( cortex-a17 ) and initial support for its big.LITTLE combination with the ARM Cortex-A7 ( cortex-a17.cortex-a7 ), ARM Cortex-A72 ( cortex-a72 ) and initial support for its big.LITTLE combination with the ARM Cortex-A53 ( cortex-a72.cortex-a53 ), ARM Cortex-M7 ( cortex-m7 ), Applied Micro X-Gene 1 ( xgene1 ), and Samsung Exynos M1 ( exynos-m1 ). The GCC identifiers can be used as arguments to the -mcpu or -mtune options, for example: -mcpu=xgene1 or -mtune=cortex-a72.cortex-a53 . Using -mcpu=cortex-a72 requires a version of GNU binutils that has support for the Cortex-A72.

) and initial support for its big.LITTLE combination with the ARM Cortex-A7 ( ), ARM Cortex-A72 ( ) and initial support for its big.LITTLE combination with the ARM Cortex-A53 ( ), ARM Cortex-M7 ( ), Applied Micro X-Gene 1 ( ), and Samsung Exynos M1 ( ). The GCC identifiers can be used as arguments to the or options, for example: or . Using requires a version of GNU binutils that has support for the Cortex-A72. The deprecated option -mwords-little-endian has been removed.

has been removed. The options -mapcs , -mapcs-frame , -mtpcs-frame and -mtpcs-leaf-frame which are only applicable to the old ABI have been deprecated.

, , and which are only applicable to the old ABI have been deprecated. The transitional options -mlra and -mno-lra have been removed. The ARM backend now uses the local register allocator (LRA) only.

AVR

The compiler no more supports individual devices like ATmega8 . Specifying, say, -mmcu=atmega8 triggers the usage of the device-specific spec file specs-atmega8 which is part of the installation and describes options for the sub-processes like compiler proper, assembler and linker. You can add support for a new device -mmcu= mydevice as follows: In an empty directory / someplace , create a new directory device-specs . Copy a device spec file from the installed device-specs folder, follow the comments in that file and then save it as / someplace /device-specs/specs- mydevice . Add -B / someplace -mmcu= mydevice to the compiler's command-line options. Notice that / someplace must specify an absolute path and that mydevice must not start with " avr ". Provided you have a device-specific library lib mydevice .a available, you can put it at / someplace , dito for a device-specific startup file crt mydevice .o . The contents of the device spec files depend on the compiler's configuration, in particular on --with-avrlibc=no and whether or not it is configured for RTEMS.

. Specifying, say, triggers the usage of the device-specific spec file which is part of the installation and describes options for the sub-processes like compiler proper, assembler and linker. You can add support for a new device as follows: The contents of the device spec files depend on the compiler's configuration, in particular on and whether or not it is configured for RTEMS. A new command-line option -nodevicelib has been added. It prevents the compiler from linking against AVR-LibC's device-specific library lib device .a .

has been added. It prevents the compiler from linking against AVR-LibC's device-specific library . The following three command-line options have been added: -mrmw Set if the device supports the read-modify-write instructions LAC , LAS , LAT and XCH . -mn-flash=size Specify the flash size of the device in units of 64 KiB, rounded up to the next integer as needed. This option affects the availability of the AVR address-spaces. -mskip-bug Set if the device is affected by the respective silicon bug. In general, you don't need to set these options by hand. The new device-specific spec file will set them as needed.

IA-32/x86-64

New ISA extensions support AVX-512{BW,DQ,VL,IFMA,VBMI} of Intel's CPU codenamed Skylake Server was added to GCC. That includes inline assembly support, new intrinsics, and basic autovectorization. These new AVX-512 extensions are available via the following GCC switches: AVX-512 Vector Length EVEX feature: -mavx512vl , AVX-512 Byte and Word instructions: -mavx512bw , AVX-512 Dword and Qword instructions: -mavx512dq , AVX-512 FMA-52 instructions: -mavx512ifma and for AVX-512 Vector Bit Manipulation Instructions: -mavx512vbmi .

, AVX-512 Byte and Word instructions: , AVX-512 Dword and Qword instructions: , AVX-512 FMA-52 instructions: and for AVX-512 Vector Bit Manipulation Instructions: . New ISA extensions support Intel MPX was added to GCC. This new extension is available via the -mmpx compiler switch. Intel MPX is a set of processor features which, with compiler, run-time library and OS support, brings increased robustness to software by run-time checking pointer references against their bounds. In GCC Intel MPX is supported by Pointer Bounds Checker and libmpx run-time libraries.

compiler switch. Intel MPX is a set of processor features which, with compiler, run-time library and OS support, brings increased robustness to software by run-time checking pointer references against their bounds. In GCC Intel MPX is supported by Pointer Bounds Checker and libmpx run-time libraries. The new -mrecord-mcount option for -pg generates a Linux kernel style table of pointers to mcount or __fentry__ calls at the beginning of functions. The new -mnop-mcount option in addition also generates nops in place of the __fentry__ or mcount call, so that a call per function can be later patched in. This can be used for low overhead tracing or hot code patching.

option for generates a Linux kernel style table of pointers to or calls at the beginning of functions. The new option in addition also generates nops in place of the or call, so that a call per function can be later patched in. This can be used for low overhead tracing or hot code patching. The new -malign-data option controls how GCC aligns variables. -malign-data=compat uses increased alignment compatible with GCC 4.8 and earlier, -malign-data=abi uses alignment as specified by the psABI, and -malign-data=cacheline uses increased alignment to match the cache line size. -malign-data=compat is the default.

option controls how GCC aligns variables. uses increased alignment compatible with GCC 4.8 and earlier, uses alignment as specified by the psABI, and uses increased alignment to match the cache line size. is the default. The new -mskip-rax-setup option skips setting up the RAX register when SSE is disabled and there are no variable arguments passed in vector registers. This can be used to optimize the Linux kernel.

MIPS

MIPS Releases 3 and 5 are now directly supported. Use the command-line options -mips32r3 , -mips64r3 , -mips32r5 and -mips64r5 to enable code-generation for these processors.

, , and to enable code-generation for these processors. The Imagination P5600 processor is now supported using the -march=p5600 command-line option.

command-line option. The Cavium Octeon3 processor is now supported using the -march=octeon3 command-line option.

command-line option. MIPS Release 6 is now supported using the -mips32r6 and -mips64r6 command-line options.

and command-line options. The o32 ABI has been modified and extended. The o32 64-bit floating-point register support is now obsolete and has been removed. It has been replaced by three ABI extensions FPXX, FP64A, and FP64. The meaning of the -mfp64 command-line option has changed. It is now used to enable the FP64A and FP64 ABI extensions. The FPXX extension requires that code generated to access double-precision values use even-numbered registers. Code that adheres to this extension is link-compatible with all other o32 double-precision ABI variants and will execute correctly in all hardware FPU modes. The command-line options -mabi=32 -mfpxx can be used to enable this extension. MIPS II is the minimum processor required. The o32 FP64A extension requires that floating-point registers be 64-bit and odd-numbered single-precision registers are not allowed. Code that adheres to the o32 FP64A variant is link-compatible with all other o32 double-precision ABI variants. The command-line options -mabi=32 -mfp64 -mno-odd-spreg can be used to enable this extension. MIPS32R2 is the minimum processor required. The o32 FP64 extension also requires that floating-point registers be 64-bit, but permits the use of single-precision registers. Code that adheres to the o32 FP64 variant is link-compatible with o32 FPXX and o32 FP64A variants only, i.e. it is not compatible with the original o32 double-precision ABI. The command-line options -mabi=32 -mfp64 -modd-spreg can be used to enable this extension. MIPS32R2 is the minimum processor required. The new ABI variants can be enabled by default using the configure time options --with-fp-32=[32|xx|64] and --with(out)-odd-sp-reg-32 . It is strongly recommended that all vendors begin to set o32 FPXX as the default ABI. This will be required to run the generated code on MIPSR5 cores in conjunction with future MIPS SIMD (MSA) code and MIPSR6 cores.

command-line option has changed. It is now used to enable the FP64A and FP64 ABI extensions. The new ABI variants can be enabled by default using the configure time options and . It is strongly recommended that all vendors begin to set o32 FPXX as the default ABI. This will be required to run the generated code on MIPSR5 cores in conjunction with future MIPS SIMD (MSA) code and MIPSR6 cores. GCC will now pass all floating-point options to the assembler if GNU binutils 2.25 is used. As a result, any inline assembly code that uses hard-float instructions should be amended to include a .set directive to override the global assembler options when compiling for soft-float targets.

NDS32

The variadic function ABI implementation is now compatible with past Andes toolchains where the caller uses registers to pass arguments and the callee is in charge of pushing them on stack.

The options -mforce-fp-as-gp , -mforbid-fp-as-gp , and -mex9 have been removed since they are not yet available in the nds32 port of GNU binutils.

, , and have been removed since they are not yet available in the nds32 port of GNU binutils. A new option -mcmodel=[small|medium|large] supports varied code models on code generation. The -mgp-direct option became meaningless and can be discarded.

RX

A new command line option -mno-allow-string-insns can be used to disable the generation of the SCMPU , SMOVU , SMOVB , SMOVF , SUNTIL , SWHILE and RMPA instructions. An erratum released by Renesas shows that it is unsafe to use these instructions on addresses within the I/O space of the processor. The new option can be used when the programmer is concerned that the I/O space might be accessed. The default is still to enable these instructions.

SH

The compiler will now pass the appropriate --isa= option to the assembler.

option to the assembler. The default handling for the GBR has been changed from call clobbered to call preserved. The old behavior can be reinstated by specifying the option -fcall-used-gbr .

has been changed from call clobbered to call preserved. The old behavior can be reinstated by specifying the option . Support for the SH4A fpchg instruction has been added which will be utilized when switching between single and double precision FPU modes.

instruction has been added which will be utilized when switching between single and double precision FPU modes. The compiler no longer uses the __fpscr_values array for switching between single and double FPU precision modes on non-SH4A targets. Instead mode switching will now be performed by storing, modifying and reloading the FPSCR , so that other FPSCR bits are preserved across mode switches. The __fpscr_values array that is defined in libgcc is still present for backwards compatibility, but it will not be referenced by compiler generated code anymore.

array for switching between single and double FPU precision modes on non-SH4A targets. Instead mode switching will now be performed by storing, modifying and reloading the , so that other bits are preserved across mode switches. The array that is defined in libgcc is still present for backwards compatibility, but it will not be referenced by compiler generated code anymore. New builtin functions __builtin_sh_get_fpscr and __builtin_sh_set_fpscr have been added. The __builtin_sh_set_fpscr function will mask the specified bits in such a way that the SZ , PR and FR mode bits will be preserved, while changing the other bits. These new functions do not reference the __fpscr_values array. The old functions __set_fpscr and __get_fpscr in libgcc which access the __fpscr_values array are still present for backwards compatibility, but their usage is highly discouraged.

and have been added. The function will mask the specified bits in such a way that the , and mode bits will be preserved, while changing the other bits. These new functions do not reference the array. The old functions and in libgcc which access the array are still present for backwards compatibility, but their usage is highly discouraged. Some improvements to code generated for __atomic built-in functions.

built-in functions. When compiling for SH2E the compiler will no longer force the usage of delay slots for conditional branch instructions bt and bf . The old behavior can be reinstated (e.g. to work around a hardware bug in the original SH7055) by specifying the new option -mcbranch-force-delay-slot .

Operating Systems

AIX

GCC now supports stabs debugging continuation lines to allow long stabs debug information without overflow that generates AIX linker errors.

DragonFly BSD

GCC now supports the DragonFly BSD operating system.

FreeBSD

GCC now supports the FreeBSD operating system for the arm port through the arm*-*-freebsd* target triplets.

VxWorks MILS

GCC now supports the MILS (Multiple Independent Levels of Security) variant of WindRiver's VxWorks operating system for PowerPC targets.

Other significant improvements

The gcc-ar , gcc-nm , gcc-ranlib wrappers now understand a -B option to set the compiler to use.

When the new command-line option -freport-bug is used, GCC automatically generates a developer-friendly reproducer whenever an internal compiler error is encountered.

GCC 5.2

This is the list of problem reports (PRs) from GCC's bug tracking system that are known to be fixed in the 5.2 release. This list might not be complete (that is, it is possible that some PRs that have been fixed are not listed here).

Target Specific Changes

IA-32/x86-64

Support for new AMD instructions monitorx and mwaitx has been added. This includes new intrinsic and built-in support. It is enabled through option -mmwaitx . The instructions monitorx and mwaitx implement the same functionality as the old monitor and mwait instructions. In addition mwaitx adds a configurable timer. The timer value is received as third argument and stored in register %ebx .

S/390, System z, IBM z Systems

Support for the IBM z13 processor has been added. When using the -march=z13 option, the compiler will generate code making use of the new instructions and registers introduced with the vector extension facility. The -mtune=z13 option enables z13 specific instruction scheduling without making use of new instructions.

Compiling code with -march=z13 reduces the default alignment of vector types bigger than 8 bytes to 8. This is an ABI change and care must be taken when linking modules compiled with different arch levels which interchange variables containing vector type values. For newly compiled code the GNU linker will emit a warning.

option, the compiler will generate code making use of the new instructions and registers introduced with the vector extension facility. The option enables z13 specific instruction scheduling without making use of new instructions. Compiling code with reduces the default alignment of vector types bigger than 8 bytes to 8. This is an ABI change and care must be taken when linking modules compiled with different arch levels which interchange variables containing vector type values. For newly compiled code the GNU linker will emit a warning. The -mzvector option enables a C/C++ language extension. This extension provides a new keyword vector which can be used to define vector type variables. (Note: This is not available when enforcing strict standard compliance e.g. with -std=c99 . Either enable GNU extensions with e.g. -std=gnu99 or use __vector instead of vector .)

Additionally a set of overloaded builtins is provided which is partially compatible to the PowerPC Altivec builtins. In order to make use of these builtins the vecintrin.h header file needs to be included.

GCC 5.3

This is the list of problem reports (PRs) from GCC's bug tracking system that are known to be fixed in the 5.3 release. This list might not be complete (that is, it is possible that some PRs that have been fixed are not listed here).

Target Specific Changes

IA-32/x86-64

GCC now supports the Intel CPU named Skylake with AVX-512 extensions through -march=skylake-avx512 . The switch enables the following ISA extensions: AVX-512F, AVX512VL, AVX-512CD, AVX-512BW, AVX-512DQ.

S/390, System z, IBM z Systems

With this version of GCC IBM z Systems support has been added to the GO runtime environment. GCC 5.3 has proven to be able to compile larger GO applications on IBM z Systems.

GCC 5.4

This is the list of problem reports (PRs) from GCC's bug tracking system that are known to be fixed in the 5.4 release. This list might not be complete (that is, it is possible that some PRs that have been fixed are not listed here).

GCC 5.5

This is the list of problem reports (PRs) from GCC's bug tracking system that are known to be fixed in the 5.5 release. This list might not be complete (that is, it is possible that some PRs that have been fixed are not listed here).

Target Specific Changes

IA-32/x86-64

Support for the deprecated pcommit instruction has been removed.