* [PATCH 00/89] drm/vc4: Support BCM2711 Display Pipeline @ 2020-02-24 9:06 Maxime Ripard 2020-02-24 9:06 ` [PATCH 01/89] dt-bindings: i2c: brcmstb: Convert the BRCMSTB binding to a schema Maxime Ripard ` (89 more replies) 0 siblings, 90 replies; 161+ messages in thread From: Maxime Ripard @ 2020-02-24 9:06 UTC (permalink / raw) To: Nicolas Saenz Julienne, Eric Anholt Cc: Tim Gover, Dave Stevenson, linux-kernel, dri-devel, bcm-kernel-feedback-list, linux-rpi-kernel, Phil Elwell, linux-arm-kernel, Maxime Ripard Hi everyone, Here's a (pretty long) series to introduce support in the VC4 DRM driver for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4). The main differences are that there's two HDMI controllers and that there's more pixelvalve now. Those pixelvalve come with a mux in the HVS that still have only 3 FIFOs. Both of those differences are breaking a bunch of expectations in the driver, so we first need a good bunch of cleanup and reworks to introduce support for the new controllers. Similarly, the HDMI controller has all its registers shuffled and split in multiple controllers now, so we need a bunch of changes to support this as well. Only the HDMI support is enabled for now (even though the DPI output has been tested too). There's a couple of rough edges still that should be addressed in the next versions: - Dual output doesn't work - The transposer (and thus writeback) doesn't work either and conflicts with the output mux too. Let me know if you have any comments Maxime Dave Stevenson (2): drm/vc4: drv: Add support for the BCM2711 HVS5 drm/vc4: plane: Improve LBM usage Maxime Ripard (87): dt-bindings: i2c: brcmstb: Convert the BRCMSTB binding to a schema dt-bindings: i2c: brcmstb: Add BCM2711 BSC/AUTO-I2C binding i2c: brcmstb: Support BCM2711 HDMI BSC controllers i2c: brcmstb: Allow to compile it on BCM2835 clk: Return error code when of provider pointer is NULL dt-bindings: clock: Add a binding for the RPi Firmware clocks clk: bcm: rpi: Allow the driver to be probed by DT clk: bcm: rpi: Statically init clk_init_data clk: bcm: rpi: Use clk_hw_register for pllb_arm clk: bcm: rpi: Remove global pllb_arm clock pointer clk: bcm: rpi: Make sure pllb_arm is removed clk: bcm: rpi: Remove pllb_arm_lookup global pointer clk: bcm: rpi: Switch to clk_hw_register_clkdev clk: bcm: rpi: Make sure the clkdev lookup is removed clk: bcm: rpi: Create a data structure for the clocks clk: bcm: rpi: Add clock id to data clk: bcm: rpi: Pass the clocks data to the firmware function clk: bcm: rpi: Rename is_prepared function clk: bcm: rpi: Split pllb clock hooks clk: bcm: rpi: Make the PLLB registration function return a clk_hw clk: bcm: rpi: Add DT provider for the clocks clk: bcm: rpi: Discover the firmware clocks ARM: dts: bcm2711: Add firmware clocks node reset: Move reset-simple header out of drivers/reset reset: simple: Add reset callback dt-bindings: clock: Add BCM2711 DVP binding clk: bcm: Add BCM2711 DVP driver ARM: dts: bcm2711: Add HDMI DVP dt-bindings: display: Convert VC4 bindings to schemas dt-bindings: display: vc4: dpi: Add missing clock-names property dt-bindings: display: vc4: dsi: Add missing clock properties dt-bindings: display: vc4: hdmi: Add missing clock-names property dt-bindings: display: vc4: Document BCM2711 VC5 drm/vc4: drv: Add include guards drm/vc4: drv: Support BCM2711 drm/vc4: plane: Move planes creation to its own function drm/vc4: plane: Move additional planes creation to driver drm/vc4: plane: Register all the planes at once drm/vc4: plane: Create overlays for any CRTC drm/vc4: plane: Create more planes drm/vc4: crtc: Rename SoC data structures drm/vc4: crtc: Move crtc state to common header drm/vc4: crtc: Deal with different number of pixel per clock drm/vc4: crtc: Use a shared interrupt drm/vc4: crtc: Turn static const variable into a define drm/vc4: crtc: Move the cob allocation outside of bind drm/vc4: crtc: Rename HVS channel to output drm/vc4: crtc: Use local chan variable drm/vc4: crtc: Enable and disable the PV in atomic_enable / disable drm/vc4: crtc: Assign output to channel automatically drm/vc4: crtc: Add FIFO depth to vc4_crtc_data drm/vc4: crtc: Add function to compute FIFO level bits drm/vc4: crtc: Rename HDMI encoder type to HDMI0 drm/vc4: crtc: Add HDMI1 encoder type drm/vc4: crtc: Remove redundant call to drm_crtc_enable_color_mgmt drm/vc4: crtc: Disable color management for HVS5 dt-bindings: display: vc4: pv: Add BCM2711 pixel valves drm/vc4: crtc: Add BCM2711 pixelvalves drm/vc4: hdmi: Use debugfs private field drm/vc4: hdmi: Move structure to header drm/vc4: hdmi: rework connectors and encoders drm/vc4: hdmi: Remove DDC argument to connector_init drm/vc4: hdmi: Rename hdmi to vc4_hdmi drm/vc4: hdmi: Move accessors to vc4_hdmi drm/vc4: hdmi: Use local vc4_hdmi directly drm/vc4: hdmi: Add container_of macros for encoders and connectors drm/vc4: hdmi: Pass vc4_hdmi to CEC code drm/vc4: hdmi: Remove vc4_dev hdmi pointer drm/vc4: hdmi: Remove vc4_hdmi_connector drm/vc4: hdmi: Introduce resource init and variant drm/vc4: hdmi: Implement a register layout abstraction drm/vc4: hdmi: Add reset callback drm/vc4: hdmi: Add PHY init and disable function drm/vc4: hdmi: Add PHY RNG enable / disable function drm/vc4: hdmi: Add a CSC setup callback drm/vc4: hdmi: Add a set_timings callback drm/vc4: hdmi: Add HDMI ID drm/vc4: hdmi: Deal with multiple debugfs files drm/vc4: hdmi: Add an audio support flag drm/vc4: hdmi: Move CEC init to its own function drm/vc4: hdmi: Add CEC support flag drm/vc4: hdmi: Remove unused CEC_CLOCK_DIV define drm/vc4: hdmi: Rename drm_encoder pointer in mode_valid drm/vc4: hdmi: Adjust HSM clock rate depending on pixel rate drm/vc4: hdmi: Support the BCM2711 HDMI controllers dt-bindings: display: vc4: hdmi: Add BCM2711 HDMI controllers bindings ARM: dts: bcm2711: Enable the display pipeline Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml | 47 ++- Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml | 39 ++- Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt | 174 +--------- Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml | 72 ++++- Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml | 84 ++++- Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml | 180 ++++++++++- Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 37 ++- Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 45 ++- Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml | 37 ++- Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml | 42 ++- Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 35 ++- Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml | 44 ++- Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml | 97 +++++- Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt | 26 +- MAINTAINERS | 4 +- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 40 ++- arch/arm/boot/dts/bcm2711.dtsi | 132 +++++++- drivers/clk/bcm/Kconfig | 1 +- drivers/clk/bcm/Makefile | 1 +- drivers/clk/bcm/clk-bcm2711-dvp.c | 113 ++++++- drivers/clk/bcm/clk-raspberrypi.c | 271 ++++++++++---- drivers/clk/clk.c | 14 +- drivers/gpu/drm/vc4/Makefile | 1 +- drivers/gpu/drm/vc4/vc4_crtc.c | 328 ++++++++++------- drivers/gpu/drm/vc4/vc4_drv.c | 5 +- drivers/gpu/drm/vc4/vc4_drv.h | 56 ++- drivers/gpu/drm/vc4/vc4_hdmi.c | 1364 ++++++++++++++++++++++++++++++++++++++++++------------------------------ drivers/gpu/drm/vc4/vc4_hdmi.h | 175 +++++++++- drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 509 +++++++++++++++++++++++++++- drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 445 +++++++++++++++++++++++- drivers/gpu/drm/vc4/vc4_hvs.c | 17 +- drivers/gpu/drm/vc4/vc4_kms.c | 175 ++++++++- drivers/gpu/drm/vc4/vc4_plane.c | 271 ++++++++++---- drivers/gpu/drm/vc4/vc4_regs.h | 173 ++++----- drivers/i2c/busses/Kconfig | 2 +- drivers/i2c/busses/i2c-brcmstb.c | 33 ++- drivers/reset/reset-simple.c | 24 +- drivers/reset/reset-simple.h | 41 +-- drivers/reset/reset-socfpga.c | 3 +- drivers/reset/reset-sunxi.c | 3 +- drivers/reset/reset-uniphier-glue.c | 3 +- include/linux/reset/reset-simple.h | 45 ++- include/soc/bcm2835/raspberrypi-firmware.h | 5 +- 43 files changed, 4020 insertions(+), 1193 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/brcm,bcm2711-dvp.yaml create mode 100644 Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml delete mode 100644 Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml create mode 100644 Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-brcmstb.txt create mode 100644 drivers/clk/bcm/clk-bcm2711-dvp.c create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi.h create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_phy.c create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h delete mode 100644 drivers/reset/reset-simple.h create mode 100644 include/linux/reset/reset-simple.h base-commit: fca8fce14e6ce96f4d22783ab8ddea09c0f4de34 -- git-series 0.9.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 161+ messages in thread

* [PATCH 73/89] drm/vc4: hdmi: Implement a register layout abstraction 2020-02-24 9:06 [PATCH 00/89] drm/vc4: Support BCM2711 Display Pipeline Maxime Ripard ` (71 preceding siblings ...) 2020-02-24 9:07 ` [PATCH 72/89] drm/vc4: hdmi: Introduce resource init and variant Maxime Ripard @ 2020-02-24 9:07 ` Maxime Ripard 2020-02-24 9:07 ` [PATCH 74/89] drm/vc4: hdmi: Add reset callback Maxime Ripard ` (16 subsequent siblings) 89 siblings, 0 replies; 161+ messages in thread From: Maxime Ripard @ 2020-02-24 9:07 UTC (permalink / raw) To: Nicolas Saenz Julienne, Eric Anholt Cc: Tim Gover, Dave Stevenson, linux-kernel, dri-devel, bcm-kernel-feedback-list, linux-rpi-kernel, Phil Elwell, linux-arm-kernel, Maxime Ripard The HDMI controllers found in the BCM2711 have most of the registers reorganized in multiple registers areas and at different offsets than previously found. The logic however remains pretty much the same, so it doesn't really make sense to create a whole new driver and we should share the code as much as possible. Let's implement some indirection to wrap around a register and depending on the variant will lookup the associated register on that particular variant. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/gpu/drm/vc4/vc4_hdmi.c | 354 ++++++++++++++--------------- drivers/gpu/drm/vc4/vc4_hdmi.h | 13 +- drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 244 ++++++++++++++++++++- drivers/gpu/drm/vc4/vc4_regs.h | 92 +-------- 4 files changed, 432 insertions(+), 271 deletions(-) create mode 100644 drivers/gpu/drm/vc4/vc4_hdmi_regs.h diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index a982ce8b901d..0e8cf0eb1891 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -49,62 +49,13 @@ #include "media/cec.h" #include "vc4_drv.h" #include "vc4_hdmi.h" +#include "vc4_hdmi_regs.h" #include "vc4_regs.h" #define HSM_CLOCK_FREQ 163682864 #define CEC_CLOCK_FREQ 40000 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) -static const struct debugfs_reg32 hdmi_regs[] = { - VC4_REG32(VC4_HDMI_CORE_REV), - VC4_REG32(VC4_HDMI_SW_RESET_CONTROL), - VC4_REG32(VC4_HDMI_HOTPLUG_INT), - VC4_REG32(VC4_HDMI_HOTPLUG), - VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP), - VC4_REG32(VC4_HDMI_MAI_CONFIG), - VC4_REG32(VC4_HDMI_MAI_FORMAT), - VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG), - VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG), - VC4_REG32(VC4_HDMI_HORZA), - VC4_REG32(VC4_HDMI_HORZB), - VC4_REG32(VC4_HDMI_FIFO_CTL), - VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL), - VC4_REG32(VC4_HDMI_VERTA0), - VC4_REG32(VC4_HDMI_VERTA1), - VC4_REG32(VC4_HDMI_VERTB0), - VC4_REG32(VC4_HDMI_VERTB1), - VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL), - VC4_REG32(VC4_HDMI_TX_PHY_CTL0), - - VC4_REG32(VC4_HDMI_CEC_CNTRL_1), - VC4_REG32(VC4_HDMI_CEC_CNTRL_2), - VC4_REG32(VC4_HDMI_CEC_CNTRL_3), - VC4_REG32(VC4_HDMI_CEC_CNTRL_4), - VC4_REG32(VC4_HDMI_CEC_CNTRL_5), - VC4_REG32(VC4_HDMI_CPU_STATUS), - VC4_REG32(VC4_HDMI_CPU_MASK_STATUS), - - VC4_REG32(VC4_HDMI_CEC_RX_DATA_1), - VC4_REG32(VC4_HDMI_CEC_RX_DATA_2), - VC4_REG32(VC4_HDMI_CEC_RX_DATA_3), - VC4_REG32(VC4_HDMI_CEC_RX_DATA_4), - VC4_REG32(VC4_HDMI_CEC_TX_DATA_1), - VC4_REG32(VC4_HDMI_CEC_TX_DATA_2), - VC4_REG32(VC4_HDMI_CEC_TX_DATA_3), - VC4_REG32(VC4_HDMI_CEC_TX_DATA_4), -}; - -static const struct debugfs_reg32 hd_regs[] = { - VC4_REG32(VC4_HD_M_CTL), - VC4_REG32(VC4_HD_MAI_CTL), - VC4_REG32(VC4_HD_MAI_THR), - VC4_REG32(VC4_HD_MAI_FMT), - VC4_REG32(VC4_HD_MAI_SMP), - VC4_REG32(VC4_HD_VID_CTL), - VC4_REG32(VC4_HD_CSC_CTL), - VC4_REG32(VC4_HD_FRAME_COUNT), -}; - static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) { struct drm_info_node *node = (struct drm_info_node *)m->private; @@ -133,7 +84,7 @@ vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) if (drm_probe_ddc(vc4_hdmi->ddc)) return connector_status_connected; - if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) + if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) return connector_status_connected; cec_phys_addr_invalidate(vc4_hdmi->cec_adap); return connector_status_disconnected; @@ -231,10 +182,10 @@ static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); u32 packet_id = type - 0x80; - HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, - HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); + HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, + HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); - return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & + return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & BIT(packet_id)), 100); } @@ -243,12 +194,16 @@ static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, { struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); u32 packet_id = frame->any.type - 0x80; - u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); + const struct vc4_hdmi_register *ram_packet_start = + &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; + u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; + void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, + ram_packet_start->reg); uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; ssize_t len, i; int ret; - WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & + WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE), "Packet RAM has to be on to store the packet."); @@ -263,23 +218,23 @@ static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, } for (i = 0; i < len; i += 7) { - HDMI_WRITE(packet_reg, - buffer[i + 0] << 0 | - buffer[i + 1] << 8 | - buffer[i + 2] << 16); + writel(buffer[i + 0] << 0 | + buffer[i + 1] << 8 | + buffer[i + 2] << 16, + base + packet_reg); packet_reg += 4; - HDMI_WRITE(packet_reg, - buffer[i + 3] << 0 | - buffer[i + 4] << 8 | - buffer[i + 5] << 16 | - buffer[i + 6] << 24); + writel(buffer[i + 3] << 0 | + buffer[i + 4] << 8 | + buffer[i + 5] << 16 | + buffer[i + 6] << 24, + base + packet_reg); packet_reg += 4; } - HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, - HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); - ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & + HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, + HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); + ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & BIT(packet_id)), 100); if (ret) DRM_ERROR("Failed to wait for infoframe to start: %d

", ret); @@ -357,11 +312,11 @@ static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); int ret; - HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); + HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); - HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); - HD_WRITE(VC4_HD_VID_CTL, - HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); + HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16); + HDMI_WRITE(HDMI_VID_CTL, + HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); clk_disable_unprepare(vc4_hdmi->pixel_clock); @@ -416,18 +371,18 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) return; } - HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, + HDMI_WRITE(HDMI_SW_RESET_CONTROL, VC4_HDMI_SW_RESET_HDMI | VC4_HDMI_SW_RESET_FORMAT_DETECT); - HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); + HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); /* PHY should be in reset, like * vc4_hdmi_encoder_disable() does. */ - HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); + HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0xf << 16); - HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); + HDMI_WRITE(HDMI_TX_PHY_RESET_CTL, 0); if (debug_dump_regs) { struct drm_printer p = drm_info_printer(&vc4_hdmi->pdev->dev); @@ -437,20 +392,20 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) drm_print_regset32(&p, &vc4_hdmi->hd_regset); } - HD_WRITE(VC4_HD_VID_CTL, 0); + HDMI_WRITE(HDMI_VID_CTL, 0); - HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, - HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | + HDMI_WRITE(HDMI_SCHEDULER_CONTROL, + HDMI_READ(HDMI_SCHEDULER_CONTROL) | VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); - HDMI_WRITE(VC4_HDMI_HORZA, + HDMI_WRITE(HDMI_HORZA, (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | VC4_SET_FIELD(mode->hdisplay * pixel_rep, VC4_HDMI_HORZA_HAP)); - HDMI_WRITE(VC4_HDMI_HORZB, + HDMI_WRITE(HDMI_HORZB, VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep, VC4_HDMI_HORZB_HBP) | @@ -461,13 +416,13 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) mode->hdisplay) * pixel_rep, VC4_HDMI_HORZB_HFP)); - HDMI_WRITE(VC4_HDMI_VERTA0, verta); - HDMI_WRITE(VC4_HDMI_VERTA1, verta); + HDMI_WRITE(HDMI_VERTA0, verta); + HDMI_WRITE(HDMI_VERTA1, verta); - HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); - HDMI_WRITE(VC4_HDMI_VERTB1, vertb); + HDMI_WRITE(HDMI_VERTB0, vertb_even); + HDMI_WRITE(HDMI_VERTB1, vertb); - HD_WRITE(VC4_HD_VID_CTL, + HDMI_WRITE(HDMI_VID_CTL, (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); @@ -492,21 +447,21 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, VC4_HD_CSC_CTL_MODE); - HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); - HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); - HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); - HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); - HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); - HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); + HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); + HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); + HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); + HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); + HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); + HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); vc4_encoder->limited_rgb_range = true; } else { vc4_encoder->limited_rgb_range = false; } /* The RGB order applies even when CSC is disabled. */ - HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); + HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); - HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); + HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); if (debug_dump_regs) { struct drm_printer p = drm_info_printer(&vc4_hdmi->pdev->dev); @@ -516,30 +471,30 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) drm_print_regset32(&p, &vc4_hdmi->hd_regset); } - HD_WRITE(VC4_HD_VID_CTL, - HD_READ(VC4_HD_VID_CTL) | - VC4_HD_VID_CTL_ENABLE | - VC4_HD_VID_CTL_UNDERFLOW_ENABLE | - VC4_HD_VID_CTL_FRAME_COUNTER_RESET); + HDMI_WRITE(HDMI_VID_CTL, + HDMI_READ(HDMI_VID_CTL) | + VC4_HD_VID_CTL_ENABLE | + VC4_HD_VID_CTL_UNDERFLOW_ENABLE | + VC4_HD_VID_CTL_FRAME_COUNTER_RESET); if (vc4_encoder->hdmi_monitor) { - HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, - HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | + HDMI_WRITE(HDMI_SCHEDULER_CONTROL, + HDMI_READ(HDMI_SCHEDULER_CONTROL) | VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); - ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); WARN_ONCE(ret, "Timeout waiting for " "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE

"); } else { - HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, - HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & + HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, + HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~(VC4_HDMI_RAM_PACKET_ENABLE)); - HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, - HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + HDMI_WRITE(HDMI_SCHEDULER_CONTROL, + HDMI_READ(HDMI_SCHEDULER_CONTROL) & ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); - ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); WARN_ONCE(ret, "Timeout waiting for " "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE

"); @@ -548,31 +503,31 @@ static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) if (vc4_encoder->hdmi_monitor) { u32 drift; - WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); - HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, - HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | + HDMI_WRITE(HDMI_SCHEDULER_CONTROL, + HDMI_READ(HDMI_SCHEDULER_CONTROL) | VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); - HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, + HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, VC4_HDMI_RAM_PACKET_ENABLE); vc4_hdmi_set_infoframes(encoder); - drift = HDMI_READ(VC4_HDMI_FIFO_CTL); + drift = HDMI_READ(HDMI_FIFO_CTL); drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; - HDMI_WRITE(VC4_HDMI_FIFO_CTL, + HDMI_WRITE(HDMI_FIFO_CTL, drift & ~VC4_HDMI_FIFO_CTL_RECENTER); - HDMI_WRITE(VC4_HDMI_FIFO_CTL, + HDMI_WRITE(HDMI_FIFO_CTL, drift | VC4_HDMI_FIFO_CTL_RECENTER); usleep_range(1000, 1100); - HDMI_WRITE(VC4_HDMI_FIFO_CTL, + HDMI_WRITE(HDMI_FIFO_CTL, drift & ~VC4_HDMI_FIFO_CTL_RECENTER); - HDMI_WRITE(VC4_HDMI_FIFO_CTL, + HDMI_WRITE(HDMI_FIFO_CTL, drift | VC4_HDMI_FIFO_CTL_RECENTER); - ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & + ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); WARN_ONCE(ret, "Timeout waiting for " "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); @@ -612,7 +567,7 @@ static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi) VC4_HD_MAI_SMP_M_SHIFT) + 1, &n, &m); - HD_WRITE(VC4_HD_MAI_SMP, + HDMI_WRITE(HDMI_MAI_SMP, VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); } @@ -631,7 +586,7 @@ static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) do_div(tmp, 128 * samplerate); cts = tmp; - HDMI_WRITE(VC4_HDMI_CRP_CFG, + HDMI_WRITE(HDMI_CRP_CFG, VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); @@ -640,8 +595,8 @@ static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) * providing a CTS_1 value. The two CTS values are alternated * between based on the period fields */ - HDMI_WRITE(VC4_HDMI_CTS_0, cts); - HDMI_WRITE(VC4_HDMI_CTS_1, cts); + HDMI_WRITE(HDMI_CTS_0, cts); + HDMI_WRITE(HDMI_CTS_1, cts); } static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) @@ -668,7 +623,7 @@ static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, * If the HDMI encoder hasn't probed, or the encoder is * currently in DVI mode, treat the codec dai as missing. */ - if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & + if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) return -ENODEV; @@ -694,9 +649,9 @@ static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) if (ret) dev_err(dev, "Failed to stop audio infoframe: %d

", ret); - HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); - HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); - HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); + HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); + HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); + HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); } static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, @@ -732,7 +687,7 @@ static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, vc4_hdmi->audio.channels = params_channels(params); vc4_hdmi->audio.samplerate = params_rate(params); - HD_WRITE(VC4_HD_MAI_CTL, + HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET | VC4_HD_MAI_CTL_FLUSH | VC4_HD_MAI_CTL_DLATE | @@ -752,22 +707,22 @@ static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, /* Set the MAI threshold. This logic mimics the firmware's. */ if (vc4_hdmi->audio.samplerate > 96000) { - HD_WRITE(VC4_HD_MAI_THR, + HDMI_WRITE(HDMI_MAI_THR, VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); } else if (vc4_hdmi->audio.samplerate > 48000) { - HD_WRITE(VC4_HD_MAI_THR, + HDMI_WRITE(HDMI_MAI_THR, VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); } else { - HD_WRITE(VC4_HD_MAI_THR, + HDMI_WRITE(HDMI_MAI_THR, VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); } - HDMI_WRITE(VC4_HDMI_MAI_CONFIG, + HDMI_WRITE(HDMI_MAI_CONFIG, VC4_HDMI_MAI_CONFIG_BIT_REVERSE | VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); @@ -777,8 +732,8 @@ static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, channel_map |= i << (3 * i); } - HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); - HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); + HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); + HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); vc4_hdmi_set_n_cts(vc4_hdmi); return 0; @@ -793,21 +748,22 @@ static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, switch (cmd) { case SNDRV_PCM_TRIGGER_START: vc4_hdmi_set_audio_infoframe(encoder); - HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, - HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & + HDMI_WRITE(HDMI_TX_PHY_CTL_0, + HDMI_READ(HDMI_TX_PHY_CTL_0) & ~VC4_HDMI_TX_PHY_RNG_PWRDN); - HD_WRITE(VC4_HD_MAI_CTL, + + HDMI_WRITE(HDMI_MAI_CTL, VC4_SET_FIELD(vc4_hdmi->audio.channels, VC4_HD_MAI_CTL_CHNUM) | VC4_HD_MAI_CTL_ENABLE); break; case SNDRV_PCM_TRIGGER_STOP: - HD_WRITE(VC4_HD_MAI_CTL, + HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_DLATE | VC4_HD_MAI_CTL_ERRORE | VC4_HD_MAI_CTL_ERRORF); - HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, - HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | + HDMI_WRITE(HDMI_TX_PHY_CTL_0, + HDMI_READ(HDMI_TX_PHY_CTL_0) | VC4_HDMI_TX_PHY_RNG_PWRDN); break; default: @@ -941,6 +897,8 @@ static const struct snd_dmaengine_pcm_config pcm_conf = { static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) { + const struct vc4_hdmi_register *mai_data = + &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; struct snd_soc_card *card = &vc4_hdmi->audio.card; struct device *dev = &vc4_hdmi->pdev->dev; @@ -953,6 +911,11 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) return 0; } + if (mai_data->reg != VC4_HD) { + WARN_ONCE(true, "MAI isn't in the HD block

"); + return -EINVAL; + } + /* * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve * the bus address specified in the DT, because the physical address @@ -961,7 +924,7 @@ static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) * This VC/MMU should probably be exposed to avoid this kind of hacks. */ addr = of_get_address(dev->of_node, 1, NULL, NULL); - vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; + vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; vc4_hdmi->audio.dma_data.maxburst = 2; @@ -1053,7 +1016,7 @@ static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); for (i = 0; i < msg->len; i += 4) { - u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); + u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + i); msg->msg[i] = val & 0xff; msg->msg[i + 1] = (val >> 8) & 0xff; @@ -1065,26 +1028,26 @@ static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) { struct vc4_hdmi *vc4_hdmi = priv; - u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); + u32 stat = HDMI_READ(HDMI_CPU_STATUS); u32 cntrl1, cntrl5; if (!(stat & VC4_HDMI_CPU_CEC)) return IRQ_NONE; vc4_hdmi->cec_rx_msg.len = 0; - cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); - cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); + cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); + cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; if (vc4_hdmi->cec_irq_was_rx) { vc4_cec_read_msg(vc4, cntrl1); cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); + HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; } else { vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; } - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); - HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); + HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); + HDMI_WRITE(HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); return IRQ_WAKE_THREAD; } @@ -1094,7 +1057,7 @@ static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); /* clock period in microseconds */ const u32 usecs = 1000000 / CEC_CLOCK_FREQ; - u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); + u32 val = HDMI_READ(HDMI_CEC_CNTRL_5); val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | VC4_HDMI_CEC_CNT_TO_4700_US_MASK | @@ -1103,30 +1066,30 @@ static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); if (enable) { - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | + HDMI_WRITE(HDMI_CEC_CNTRL_5, val | VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, + HDMI_WRITE(HDMI_CEC_CNTRL_5, val); + HDMI_WRITE(HDMI_CEC_CNTRL_2, ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, + HDMI_WRITE(HDMI_CEC_CNTRL_3, ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, + HDMI_WRITE(HDMI_CEC_CNTRL_4, ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); - HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); + HDMI_WRITE(HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); } else { - HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | + HDMI_WRITE(HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); + HDMI_WRITE(HDMI_CEC_CNTRL_5, val | VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); } return 0; @@ -1136,8 +1099,8 @@ static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) { struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, - (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | + HDMI_WRITE(HDMI_CEC_CNTRL_1, + (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); return 0; } @@ -1150,20 +1113,20 @@ static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, unsigned int i; for (i = 0; i < msg->len; i += 4) - HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, + HDMI_WRITE(HDMI_CEC_TX_DATA_1 + i, (msg->msg[i]) | (msg->msg[i + 1] << 8) | (msg->msg[i + 2] << 16) | (msg->msg[i + 3] << 24)); - val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); + val = HDMI_READ(HDMI_CEC_CNTRL_1); val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); + HDMI_WRITE(HDMI_CEC_CNTRL_1, val); val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; val |= VC4_HDMI_CEC_START_XMIT_BEGIN; - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); + HDMI_WRITE(HDMI_CEC_CNTRL_1, val); return 0; } @@ -1174,26 +1137,63 @@ static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { }; #endif +static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, + struct debugfs_regset32 *regset, + enum vc4_hdmi_regs reg) +{ + const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; + struct debugfs_reg32 *regs; + unsigned int count = 0; + unsigned int i; + + regs = kzalloc(variant->num_registers * sizeof(*regs), + GFP_KERNEL); + if (!regs) + return -ENOMEM; + + for (i = 0; i < variant->num_registers; i++) { + const struct vc4_hdmi_register *field = &variant->registers[i]; + + if (field->reg != reg) + continue; + + regs[count].name = field->name; + regs[count].offset = field->offset; + count++; + } + + regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); + if (!regs) + return -ENOMEM; + + regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); + regset->regs = regs; + regset->nregs = count; + + return 0; +} + static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) { struct platform_device *pdev = vc4_hdmi->pdev; struct device *dev = &pdev->dev; + int ret; vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); if (IS_ERR(vc4_hdmi->hdmicore_regs)) return PTR_ERR(vc4_hdmi->hdmicore_regs); - vc4_hdmi->hdmi_regset.base = vc4_hdmi->hdmicore_regs; - vc4_hdmi->hdmi_regset.regs = hdmi_regs; - vc4_hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs); + ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); + if (ret) + return ret; vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); if (IS_ERR(vc4_hdmi->hd_regs)) return PTR_ERR(vc4_hdmi->hd_regs); - vc4_hdmi->hd_regset.base = vc4_hdmi->hd_regs; - vc4_hdmi->hd_regset.regs = hd_regs; - vc4_hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs); + ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); + if (ret) + return ret; vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); if (IS_ERR(vc4_hdmi->pixel_clock)) { @@ -1286,12 +1286,12 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) } /* HDMI core must be enabled. */ - if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { - HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); + if (!(HDMI_READ(HDMI_M_CTL) & VC4_HD_M_ENABLE)) { + HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); udelay(1); - HD_WRITE(VC4_HD_M_CTL, 0); + HDMI_WRITE(HDMI_M_CTL, 0); - HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); + HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); } pm_runtime_enable(dev); @@ -1315,8 +1315,8 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) cec_fill_conn_info_from_drm(&conn_info, hdmi->connector); cec_s_conn_info(hdmi->cec_adap, &conn_info); - HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); - value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); + HDMI_WRITE(HDMI_CPU_MASK_SET, 0xffffffff); + value = HDMI_READ(HDMI_CEC_CNTRL_1); value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; /* * Set the logical address to Unregistered and set the clock @@ -1325,7 +1325,7 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) */ value |= VC4_HDMI_CEC_ADDR_MASK | (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); - HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); + HDMI_WRITE(HDMI_CEC_CNTRL_1, value); ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), vc4_cec_irq_handler, vc4_cec_irq_handler_thread, 0, @@ -1372,6 +1372,9 @@ static void vc4_hdmi_unbind(struct device *dev, struct device *master, struct snd_soc_card *card = dev_get_drvdata(dev); struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(card); + kfree(vc4_hdmi->hdmi_regset.regs); + kfree(vc4_hdmi->hd_regset.regs); + cec_unregister_adapter(vc4_hdmi->cec_adap); vc4_hdmi_connector_destroy(&vc4_hdmi->connector); vc4_hdmi_encoder_destroy(&vc4_hdmi->encoder.base.base); @@ -1399,6 +1402,9 @@ static int vc4_hdmi_dev_remove(struct platform_device *pdev) } struct vc4_hdmi_variant bcm2835_variant = { + .registers = vc4_hdmi_fields, + .num_registers = ARRAY_SIZE(vc4_hdmi_fields), + .init_resources = vc4_hdmi_init_resources, }; diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h index b00d9c806428..f4c052a78802 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h @@ -21,7 +21,15 @@ to_vc4_hdmi_encoder(struct drm_encoder *encoder) return container_of(encoder, struct vc4_hdmi_encoder, base.base); } +struct vc4_hdmi_register; + struct vc4_hdmi_variant { + /* List of the registers available on that variant */ + const struct vc4_hdmi_register *registers; + + /* Number of registers on that variant */ + unsigned int num_registers; + /* Callback to get the resources (memory region, interrupts, * clocks, etc) for that variant. */ @@ -83,9 +91,4 @@ encoder_to_vc4_hdmi(struct drm_encoder *encoder) return container_of(_encoder, struct vc4_hdmi, encoder); } -#define HDMI_READ(offset) readl(vc4_hdmi->hdmicore_regs + offset) -#define HDMI_WRITE(offset, val) writel(val, vc4_hdmi->hdmicore_regs + offset) -#define HD_READ(offset) readl(vc4_hdmi->hd_regs + offset) -#define HD_WRITE(offset, val) writel(val, vc4_hdmi->hd_regs + offset) - #endif /* _VC4_HDMI_H_ */ diff --git a/drivers/gpu/drm/vc4/vc4_hdmi_regs.h b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h new file mode 100644 index 000000000000..dd5cea16f71c --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_hdmi_regs.h @@ -0,0 +1,244 @@ +#ifndef _VC4_HDMI_REGS_H_ +#define _VC4_HDMI_REGS_H_ + +#include "vc4_hdmi.h" + +#define VC4_MASK(high, low) ((u32)GENMASK(high, low)) +/* Using the GNU statement expression extension */ +#define VC4_SET_FIELD(value, field) \ + ({ \ + uint32_t fieldval = (value) << field##_SHIFT; \ + WARN_ON((fieldval & ~field##_MASK) != 0); \ + fieldval & field##_MASK; \ + }) + +#define VC4_HDMI_PACKET_STRIDE 0x24 + +enum vc4_hdmi_regs { + VC4_INVALID = 0, + VC4_HDMI, + VC4_HD, +}; + +enum vc4_hdmi_field { + HDMI_AUDIO_PACKET_CONFIG, + HDMI_CEC_CNTRL_1, + HDMI_CEC_CNTRL_2, + HDMI_CEC_CNTRL_3, + HDMI_CEC_CNTRL_4, + HDMI_CEC_CNTRL_5, + HDMI_CEC_CPU_MASK_STATUS, + HDMI_CEC_CPU_STATUS, + + /* + * Transmit data, first byte is low byte of the 32-bit reg. + * MSB of each byte transmitted first. + */ + HDMI_CEC_RX_DATA_1, + HDMI_CEC_RX_DATA_2, + HDMI_CEC_RX_DATA_3, + HDMI_CEC_RX_DATA_4, + HDMI_CEC_TX_DATA_1, + HDMI_CEC_TX_DATA_2, + HDMI_CEC_TX_DATA_3, + HDMI_CEC_TX_DATA_4, + HDMI_CORE_REV, + HDMI_CRP_CFG, + HDMI_CSC_12_11, + HDMI_CSC_14_13, + HDMI_CSC_22_21, + HDMI_CSC_24_23, + HDMI_CSC_32_31, + HDMI_CSC_34_33, + HDMI_CSC_CTL, + + /* + * 20-bit fields containing CTS values to be transmitted if + * !EXTERNAL_CTS_EN + */ + HDMI_CTS_0, + HDMI_CTS_1, + HDMI_FIFO_CTL, + HDMI_FRAME_COUNT, + HDMI_HORZA, + HDMI_HORZB, + HDMI_HOTPLUG, + HDMI_HOTPLUG_INT, + + /* + * 3 bits per field, where each field maps from that + * corresponding MAI bus channel to the given HDMI channel. + */ + HDMI_MAI_CHANNEL_MAP, + HDMI_MAI_CONFIG, + HDMI_MAI_CTL, + + /* + * Register for DMAing in audio data to be transported over + * the MAI bus to the Falcon core. + */ + HDMI_MAI_DATA, + + /* Format header to be placed on the MAI data. Unused. */ + HDMI_MAI_FMT, + + /* Last received format word on the MAI bus. */ + HDMI_MAI_FORMAT, + HDMI_MAI_SMP, + HDMI_MAI_THR, + HDMI_M_CTL, + HDMI_RAM_PACKET_CONFIG, + HDMI_RAM_PACKET_START, + HDMI_RAM_PACKET_STATUS, + HDMI_SCHEDULER_CONTROL, + HDMI_SW_RESET_CONTROL, + HDMI_TX_PHY_CTL_0, + HDMI_TX_PHY_RESET_CTL, + HDMI_VERTA0, + HDMI_VERTA1, + HDMI_VERTB0, + HDMI_VERTB1, + HDMI_VID_CTL, +}; + +struct vc4_hdmi_register { + char *name; + enum vc4_hdmi_regs reg; + unsigned int offset; +}; + +#define _VC4_REG(_base, _reg, _offset) \ + [_reg] = { \ + .name = #_reg, \ + .reg = _base, \ + .offset = _offset, \ + } + +#define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset) +#define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset) + +static const struct vc4_hdmi_register vc4_hdmi_fields[] = { + VC4_HD_REG(HDMI_M_CTL, 0x000c), + VC4_HD_REG(HDMI_MAI_CTL, 0x0014), + VC4_HD_REG(HDMI_MAI_THR, 0x0018), + VC4_HD_REG(HDMI_MAI_FMT, 0x001c), + VC4_HD_REG(HDMI_MAI_DATA, 0x0020), + VC4_HD_REG(HDMI_MAI_SMP, 0x002c), + VC4_HD_REG(HDMI_VID_CTL, 0x0038), + VC4_HD_REG(HDMI_CSC_CTL, 0x0040), + VC4_HD_REG(HDMI_CSC_12_11, 0x0044), + VC4_HD_REG(HDMI_CSC_14_13, 0x0048), + VC4_HD_REG(HDMI_CSC_22_21, 0x004c), + VC4_HD_REG(HDMI_CSC_24_23, 0x0050), + VC4_HD_REG(HDMI_CSC_32_31, 0x0054), + VC4_HD_REG(HDMI_CSC_34_33, 0x0058), + VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068), + + VC4_HDMI_REG(HDMI_CORE_REV, 0x0000), + VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004), + VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008), + VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c), + VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c), + VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090), + VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094), + VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098), + VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c), + VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0), + VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4), + VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8), + VC4_HDMI_REG(HDMI_CTS_0, 0x00ac), + VC4_HDMI_REG(HDMI_CTS_1, 0x00b0), + VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0), + VC4_HDMI_REG(HDMI_HORZA, 0x00c4), + VC4_HDMI_REG(HDMI_HORZB, 0x00c8), + VC4_HDMI_REG(HDMI_VERTA0, 0x00cc), + VC4_HDMI_REG(HDMI_VERTB0, 0x00d0), + VC4_HDMI_REG(HDMI_VERTA1, 0x00d4), + VC4_HDMI_REG(HDMI_VERTB1, 0x00d8), + VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8), + VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec), + VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0), + VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4), + VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8), + VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc), + VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100), + VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104), + VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108), + VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c), + VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110), + VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114), + VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118), + VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0), + VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4), + VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340), + VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c), + VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400), +}; + +static inline +void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi, + enum vc4_hdmi_regs reg) +{ + switch (reg) { + case VC4_HD: + return hdmi->hd_regs; + + case VC4_HDMI: + return hdmi->hdmicore_regs; + + default: + return NULL; + } + + return NULL; +} + +static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi, + enum vc4_hdmi_regs reg) +{ + const struct vc4_hdmi_register *field; + const struct vc4_hdmi_variant *variant = hdmi->variant; + void __iomem *base; + + if (reg > variant->num_registers) { + dev_warn(&hdmi->pdev->dev, + "Invalid register ID %u

", reg); + return 0; + } + + field = &variant->registers[reg]; + base = __vc4_hdmi_get_field_base(hdmi, field->reg); + if (!base) { + dev_warn(&hdmi->pdev->dev, + "Unknown register ID %u

", reg); + return 0; + } + + return readl(base + field->offset); +} +#define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg) + +static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi, + enum vc4_hdmi_regs reg, + u32 value) +{ + const struct vc4_hdmi_register *field; + const struct vc4_hdmi_variant *variant = hdmi->variant; + void __iomem *base; + + if (reg > variant->num_registers) { + dev_warn(&hdmi->pdev->dev, + "Invalid register ID %u

", reg); + return; + } + + field = &variant->registers[reg]; + base = __vc4_hdmi_get_field_base(hdmi, field->reg); + if (!base) + return; + + writel(value, base + field->offset); +} +#define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val) + +#endif /* _VC4_HDMI_REGS_H_ */ diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index 35279b118d41..5a3ee2030cff 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -493,32 +493,16 @@ #define SCALER5_DLIST_START 0x00004000 -#define VC4_HDMI_CORE_REV 0x000 - -#define VC4_HDMI_SW_RESET_CONTROL 0x004 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) # define VC4_HDMI_SW_RESET_HDMI BIT(0) -#define VC4_HDMI_HOTPLUG_INT 0x008 - -#define VC4_HDMI_HOTPLUG 0x00c # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) -/* 3 bits per field, where each field maps from that corresponding MAI - * bus channel to the given HDMI channel. - */ -#define VC4_HDMI_MAI_CHANNEL_MAP 0x090 - -#define VC4_HDMI_MAI_CONFIG 0x094 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27) # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26) # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0) # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0 -/* Last received format word on the MAI bus. */ -#define VC4_HDMI_MAI_FORMAT 0x098 - -#define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29) # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24) # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19) @@ -532,12 +516,8 @@ # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0) # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0 -#define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) -#define VC4_HDMI_RAM_PACKET_STATUS 0x0a4 - -#define VC4_HDMI_CRP_CFG 0x0a8 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead * of pixel clock. */ @@ -551,23 +531,12 @@ # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0) # define VC4_HDMI_CRP_CFG_N_SHIFT 0 -/* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */ -#define VC4_HDMI_CTS_0 0x0ac -#define VC4_HDMI_CTS_1 0x0b0 -/* 20-bit fields containing number of clocks to send CTS0/1 before - * switching to the other one. - */ -#define VC4_HDMI_CTS_PERIOD_0 0x0b4 -#define VC4_HDMI_CTS_PERIOD_1 0x0b8 - -#define VC4_HDMI_HORZA 0x0c4 # define VC4_HDMI_HORZA_VPOS BIT(14) # define VC4_HDMI_HORZA_HPOS BIT(13) /* Horizontal active pixels (hdisplay). */ # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) # define VC4_HDMI_HORZA_HAP_SHIFT 0 -#define VC4_HDMI_HORZB 0x0c8 /* Horizontal pack porch (htotal - hsync_end). */ # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) # define VC4_HDMI_HORZB_HBP_SHIFT 20 @@ -578,7 +547,6 @@ # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) # define VC4_HDMI_HORZB_HFP_SHIFT 0 -#define VC4_HDMI_FIFO_CTL 0x05c # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) @@ -591,15 +559,12 @@ # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff -#define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) -#define VC4_HDMI_VERTA0 0x0cc -#define VC4_HDMI_VERTA1 0x0d4 /* Vertical sync pulse (vsync_end - vsync_start). */ # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) # define VC4_HDMI_VERTA_VSP_SHIFT 20 @@ -610,8 +575,6 @@ # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) # define VC4_HDMI_VERTA_VAL_SHIFT 0 -#define VC4_HDMI_VERTB0 0x0d0 -#define VC4_HDMI_VERTB1 0x0d8 /* Vertical sync pulse offset (for interlaced) */ # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) # define VC4_HDMI_VERTB_VSPO_SHIFT 9 @@ -619,7 +582,6 @@ # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) # define VC4_HDMI_VERTB_VBP_SHIFT 0 -#define VC4_HDMI_CEC_CNTRL_1 0x0e8 /* Set when the transmission has ended. */ # define VC4_HDMI_CEC_TX_EOM BIT(31) /* If set, transmission was acked on the 1st or 2nd attempt (only one @@ -660,7 +622,6 @@ /* Set these fields to how many bit clock cycles get to that many * microseconds. */ -#define VC4_HDMI_CEC_CNTRL_2 0x0ec # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24) # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24 # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17) @@ -672,7 +633,6 @@ # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0) # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0 -#define VC4_HDMI_CEC_CNTRL_3 0x0f0 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24) # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16) @@ -682,7 +642,6 @@ # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0) # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0 -#define VC4_HDMI_CEC_CNTRL_4 0x0f4 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24) # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16) @@ -692,7 +651,6 @@ # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0) # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0 -#define VC4_HDMI_CEC_CNTRL_5 0x0f8 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27) # define VC4_HDMI_CEC_RX_SW_RESET BIT(26) # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25) @@ -705,39 +663,11 @@ # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0) # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0 -/* Transmit data, first byte is low byte of the 32-bit reg. MSB of - * each byte transmitted first. - */ -#define VC4_HDMI_CEC_TX_DATA_1 0x0fc -#define VC4_HDMI_CEC_TX_DATA_2 0x100 -#define VC4_HDMI_CEC_TX_DATA_3 0x104 -#define VC4_HDMI_CEC_TX_DATA_4 0x108 -#define VC4_HDMI_CEC_RX_DATA_1 0x10c -#define VC4_HDMI_CEC_RX_DATA_2 0x110 -#define VC4_HDMI_CEC_RX_DATA_3 0x114 -#define VC4_HDMI_CEC_RX_DATA_4 0x118 - -#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 - -#define VC4_HDMI_TX_PHY_CTL0 0x2c4 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25) -/* Interrupt status bits */ -#define VC4_HDMI_CPU_STATUS 0x340 -#define VC4_HDMI_CPU_SET 0x344 -#define VC4_HDMI_CPU_CLEAR 0x348 # define VC4_HDMI_CPU_CEC BIT(6) # define VC4_HDMI_CPU_HOTPLUG BIT(0) -#define VC4_HDMI_CPU_MASK_STATUS 0x34c -#define VC4_HDMI_CPU_MASK_SET 0x350 -#define VC4_HDMI_CPU_MASK_CLEAR 0x354 - -#define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4)) -#define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24)) -#define VC4_HDMI_PACKET_STRIDE 0x24 - -#define VC4_HD_M_CTL 0x00c /* Debug: Current receive value on the CEC pad. */ # define VC4_HD_CECRXD BIT(9) /* Debug: Override CEC output to 0. */ @@ -747,7 +677,6 @@ # define VC4_HD_M_SW_RST BIT(2) # define VC4_HD_M_ENABLE BIT(0) -#define VC4_HD_MAI_CTL 0x014 /* Set when audio stream is received at a slower rate than the * sampling period, so MAI fifo goes empty. Write 1 to clear. */ @@ -772,7 +701,6 @@ /* Single-shot reset bit. Read value is undefined. */ # define VC4_HD_MAI_CTL_RESET BIT(0) -#define VC4_HD_MAI_THR 0x018 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24) # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16) @@ -782,31 +710,20 @@ # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0) # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0 -/* Format header to be placed on the MAI data. Unused. */ -#define VC4_HD_MAI_FMT 0x01c - -/* Register for DMAing in audio data to be transported over the MAI - * bus to the Falcon core. - */ -#define VC4_HD_MAI_DATA 0x020 - /* Divider from HDMI HSM clock to MAI serial clock. Sampling period * converges to N / (M + 1) cycles. */ -#define VC4_HD_MAI_SMP 0x02c # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8) # define VC4_HD_MAI_SMP_N_SHIFT 8 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0) # define VC4_HD_MAI_SMP_M_SHIFT 0 -#define VC4_HD_VID_CTL 0x038 # define VC4_HD_VID_CTL_ENABLE BIT(31) # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) -#define VC4_HD_CSC_CTL 0x040 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) # define VC4_HD_CSC_CTL_ORDER_SHIFT 5 # define VC4_HD_CSC_CTL_ORDER_RGB 0 @@ -824,15 +741,6 @@ # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) # define VC4_HD_CSC_CTL_ENABLE BIT(0) -#define VC4_HD_CSC_12_11 0x044 -#define VC4_HD_CSC_14_13 0x048 -#define VC4_HD_CSC_22_21 0x04c -#define VC4_HD_CSC_24_23 0x050 -#define VC4_HD_CSC_32_31 0x054 -#define VC4_HD_CSC_34_33 0x058 - -#define VC4_HD_FRAME_COUNT 0x068 - /* HVS display list information. */ #define HVS_BOOTLOADER_DLIST_END 32 -- git-series 0.9.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 161+ messages in thread

* Re: [PATCH 29/89] dt-bindings: display: Convert VC4 bindings to schemas 2020-02-25 11:54 ` Maxime Ripard @ 2020-02-25 14:02 ` Rob Herring 0 siblings, 0 replies; 161+ messages in thread From: Rob Herring @ 2020-02-25 14:02 UTC (permalink / raw) To: Maxime Ripard Cc: devicetree, Tim Gover, Dave Stevenson, linux-kernel, dri-devel, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Nicolas Saenz Julienne, Phil Elwell, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, moderated list:BROADCOM BCM2835 ARM ARCHITECTURE On Tue, Feb 25, 2020 at 5:54 AM Maxime Ripard <maxime@cerno.tech> wrote: > > Hi Rob, > > On Mon, Feb 24, 2020 at 12:41:07PM -0600, Rob Herring wrote: > > On Mon, 24 Feb 2020 10:06:31 +0100, Maxime Ripard wrote: > > > The BCM283x SoCs have a display pipeline composed of several controllers > > > with device tree bindings that are supported by Linux. > > > > > > Now that we have the DT validation in place, let's split into separate > > > files and convert the device tree bindings for those controllers to > > > schemas. > > > > > > Cc: Rob Herring > > > Cc: devicetree@vger.kernel.org > > > Signed-off-by: Maxime Ripard > > > --- > > > Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt | 174 +------------------------------------------------------------------------ > > > Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml | 66 +++++++++++++++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml | 73 ++++++++++++++++++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml | 75 +++++++++++++++++++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml | 37 +++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml | 40 +++++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml | 37 +++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml | 42 +++++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml | 34 ++++++++++++++- > > > Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml | 44 ++++++++++++++++++- > > > MAINTAINERS | 2 +- > > > 11 files changed, 449 insertions(+), 175 deletions(-) > > > delete mode 100644 Documentation/devicetree/bindings/display/brcm,bcm-vc4.txt > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dpi.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-v3d.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml > > > create mode 100644 Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml > > > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > > > warning: no schema found in file: Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml: ignoring, error in schema: properties > > Documentation/devicetree/bindings/display/simple-framebuffer.example.dts:21.16-37.11: Warning (chosen_node_is_root): /example-0/chosen: chosen node must be at root node > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml: properties: '#clock-cells' is a dependency of 'clock-output-names' > > Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.example.dts' failed > > make[1]: *** [Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.example.dts] Error 1 > > Makefile:1263: recipe for target 'dt_binding_check' failed > > make: *** [dt_binding_check] Error 2 > > > > See https://patchwork.ozlabs.org/patch/1242907 > > Please check and re-submit. > > Yeah, that was fixed in patch 31 ("dt-bindings: display: vc4: dsi: Add > missing clock properties"). I'm not quite sure what the preferred > approach here would be: I did a conversion as is of the binding, and > then fixed it, or do you prefer having it all in the same patch? https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 161+ messages in thread

* Re: [PATCH 07/89] clk: bcm: rpi: Allow the driver to be probed by DT 2020-02-25 16:00 ` Nicolas Saenz Julienne @ 2020-02-26 15:01 ` Maxime Ripard 2020-02-28 19:57 ` Nicolas Saenz Julienne 0 siblings, 1 reply; 161+ messages in thread From: Maxime Ripard @ 2020-02-26 15:01 UTC (permalink / raw) To: Nicolas Saenz Julienne Cc: Tim Gover, Dave Stevenson, Stephen Boyd, Michael Turquette, linux-kernel, dri-devel, linux-clk, bcm-kernel-feedback-list, linux-rpi-kernel, Phil Elwell, linux-arm-kernel [-- Attachment #1.1: Type: text/plain, Size: 6024 bytes --] Hi Nicolas, On Tue, Feb 25, 2020 at 05:00:56PM +0100, Nicolas Saenz Julienne wrote: > On Mon, 2020-02-24 at 10:06 +0100, Maxime Ripard wrote: > > The current firmware clock driver for the RaspberryPi can only be probed by > > manually registering an associated platform_device. > > > > While this works fine for cpufreq where the device gets attached a clkdev > > lookup, it would be tedious to maintain a table of all the devices using > > one of the clocks exposed by the firmware. > > > > Since the DT on the other hand is the perfect place to store those > > associations, make the firmware clocks driver probe-able through the device > > tree so that we can represent it as a node. > > I'm not convinced this is the right approach, and if we decide to go this way, > there are more changes to take into account. This was actually a shameless bait to start that discussion, so I'm glad it worked ;) > For one, if we create a dt node for this driver, we'd have to delete the > platform device creation in firmware/raspberrypi.c and then we'd be even able > to bypass raspberrypi-cpufreq altogether by creating opp tables in dt. But > there are reasons we didn't go that way at the time. Right, I missed that one since the check for the firmware phandle was preventing the double-probe to happen, but it's bad indeed. > We've made an effort to avoid using dt for firmware interfaces whenever > possible as, on one hand, it's arguable they don't fit device-tree's hardware > description paradigm and, on the other, the lack of flexibility they impose > once the binding is defined. VC4's firmware interfaces are not set in stone, > nor standardized like SCMI, so the more flexible we are to future changes the > better. The device tree isn't just about the hardware though, but also contains the state the bootloader / firmware left the hardware in. You're mentionning SCMI, and SCMI clocks IDs are stored in the device tree. Just like pen release addresses, PSCI function ids, etc. The firmware IDs of these clocks shouldn't change too. But you also raise a valid point with the lack of flexibility, especially since the clock tree isn't that well understood. > Another thing I'm not all that happy about it's how dynamic clock registering > is handled in patch #22 (but I'll keep it here as relevant to the discussion): > > - Some of those fw managed clocks you're creating have their mmio counterpart > being registered by clk-bcm238. IMO either register one or the other, giving > precedence to the mmio counterpart. Note that for pllb, we deleted the > relevant code from clk-bcm2385. Indeed, and it's really that part of the discussion I wanted to start. For some reason, it looks like a good chunk of those clocks are non-functional at the moment (they all report 0). If we're going to use the firmware clocks as I did here, we'd have to modify most of the device clocks used so far (UART, especially) to derive from the core clock. I wasn't really sure of the implications though, since it's my first experience with the RPi clock tree. > - The same way we were able to map the fw CPU clock into the clk tree > (pllb/pllb_arm) there are no reasons we shouldn't be able to do the same for > the VPU clocks. It's way nicer and less opaque to users (this being a > learning platform adds to the argument). This would make the Linux clock tree match the one in hardware, which would indeed be more readable to a beginner, but I see three main drawbacks with this: - The parent / child relationship is already encoded in the firmware discovery mechanism. It's not used yet by the driver, because the firmware reports all of them as root clocks, but that's pretty easy to fix. - It would make the code far more complicated and confusing than it could, especially to beginners. And as far as I know, only the RPi is doing that, while pretty much all the other platforms either have the clock tree entirely defined, or rely on the firmware, but don't have an hybrid. So they would learn something that cannot really be applied to anywhere else. - I have no idea what the clock tree is supposed to look like :) > - On top of that, having a special case for the CPU clock registration is > nasty. Lets settle for one solution and make everyone follow it. It seemed to me that the CPU clock had a factor between the actual CPU frequency and its clock? If not, then yeah we should definitely get rid of it. > - I don't see what's so bad about creating clock lookups. IIUC there are only > two clocks that need this special handling CPU & HDMI, It's manageable. You > don't even have to mess with the consumer driver, if there was ever to be a > dt provided mmio option to this clock. V3D needs one too, and I might have missed a bunch of them in that series given how the current debugging of the remaining issues turn out to be. And clk_lookups are local to devices, so you need to factor that by the number of devices you have. Sure, it works, but it feels to me like that's going to be an issue pretty fast, especially with the lookups on the way out? > > drivers/clk/bcm/clk-raspberrypi.c | 11 ++++++++--- > > 1 file changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk- > > raspberrypi.c > > index 1654fd0eedc9..94870234824c 100644 > > --- a/drivers/clk/bcm/clk-raspberrypi.c > > +++ b/drivers/clk/bcm/clk-raspberrypi.c > > @@ -255,15 +255,13 @@ static int raspberrypi_clk_probe(struct platform_device > > *pdev) > > struct raspberrypi_clk *rpi; > > int ret; > > > > - firmware_node = of_find_compatible_node(NULL, NULL, > > - "raspberrypi,bcm2835-firmware"); > > + firmware_node = of_parse_phandle(dev->of_node, "raspberrypi,firmware", > > 0); > > There is no such phandle in the upstream device tree. Maybe this was aimed at > the downstream dt? raspberrypi,firmware is the property, it points to the /soc/firmware node that is defined in bcm2835-rpi.dtsi Maxime [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 161+ messages in thread

* Re: [PATCH 07/89] clk: bcm: rpi: Allow the driver to be probed by DT 2020-02-26 15:01 ` Maxime Ripard @ 2020-02-28 19:57 ` Nicolas Saenz Julienne 0 siblings, 0 replies; 161+ messages in thread From: Nicolas Saenz Julienne @ 2020-02-28 19:57 UTC (permalink / raw) To: Maxime Ripard Cc: Tim Gover, Dave Stevenson, Stephen Boyd, Michael Turquette, linux-kernel, dri-devel, linux-clk, bcm-kernel-feedback-list, linux-rpi-kernel, Phil Elwell, linux-arm-kernel [-- Attachment #1.1: Type: text/plain, Size: 6537 bytes --] Hi Maxime, On Wed, 2020-02-26 at 16:01 +0100, Maxime Ripard wrote: [...] > This was actually a shameless bait to start that discussion, so I'm > glad it worked ;) :) [...] > > - Some of those fw managed clocks you're creating have their mmio > > counterpart > > being registered by clk-bcm238. IMO either register one or the other, > > giving > > precedence to the mmio counterpart. Note that for pllb, we deleted the > > relevant code from clk-bcm2385. > > Indeed, and it's really that part of the discussion I wanted to > start. For some reason, it looks like a good chunk of those clocks are > non-functional at the moment (they all report 0). Yes, although they should be alright. I think it's just a matter of passing the right flags to the clk framework (disable caching and so on), but never found the time to investigate further. > If we're going to > use the firmware clocks as I did here, we'd have to modify most of the > device clocks used so far (UART, especially) to derive from the core > clock. I wasn't really sure of the implications though, since it's my first > experience with the RPi clock tree. That's something I'm confused about. I played around with your code and the HSM clock changes seem to be completely unrelated to the VPU clock. Actually it seems it's derived from 'plld_per' (here Florian can maybe contradict me). I found out by feeding the mmio HSM clock to your driver, which actually seemed to work (albeit maybe just out of luck since the FW already set up everything). Bare in mind, we disable turbo mode upstream so as for the firmware not to change the VPU frequencies on par with CPU changes (controlled by a special bit in the CPU clock mailbox property). So, if I'm not wrong, this simplifies things. As we don't have to worry about re-clocking all peripherals with every resolution change. This even opens up another question. Which clocks is the firmware interface monitoring for DVFS? If it's just the VPU and CPU we could be over-complicating things here, and MMIO clks could be an option, isn't it? On the subject of re-clocking, I had a word with the clk maintainers on how to properly implement it, see the two last paragraphs here if curious: https://www.spinics.net/lists/linux-clk/msg36937.html > > - The same way we were able to map the fw CPU clock into the clk tree > > (pllb/pllb_arm) there are no reasons we shouldn't be able to do the same > > for > > the VPU clocks. It's way nicer and less opaque to users (this being a > > learning platform adds to the argument). > > This would make the Linux clock tree match the one in hardware, which > would indeed be more readable to a beginner, but I see three main > drawbacks with this: > > - The parent / child relationship is already encoded in the firmware > discovery mechanism. It's not used yet by the driver, because the > firmware reports all of them as root clocks, but that's pretty > easy to fix. Had a look at this, they all return root as their parent. Which is somewhat true from the fw interface perspective (only leaves are represented), but not too endearing. > - It would make the code far more complicated and confusing than it > could, especially to beginners. And as far as I know, only the RPi > is doing that, while pretty much all the other platforms either > have the clock tree entirely defined, or rely on the firmware, but > don't have an hybrid. So they would learn something that cannot > really be applied to anywhere else. Fair enough. Still, for now, I think I prefer a hybrid clk tree approach. > - I have no idea what the clock tree is supposed to look like :) I don't have access to the official clock tree either. The closest we have is whatever the mmio clk driver exposes. > > - On top of that, having a special case for the CPU clock registration is > > nasty. Lets settle for one solution and make everyone follow it. > > It seemed to me that the CPU clock had a factor between the actual CPU > frequency and its clock? If not, then yeah we should definitely get > rid of it. Yes, IIRC, there is a factor because the CPU clock firmware interface actually controls the underlying PLL frequency which is then divided by 2 before reaching the CPU. Which kind of breaks the FW interface design if you ask me (alongside this turbo mode thing). > > - I don't see what's so bad about creating clock lookups. IIUC there are > > only > > two clocks that need this special handling CPU & HDMI, It's manageable. > > You > > don't even have to mess with the consumer driver, if there was ever to be > > a > > dt provided mmio option to this clock. > > V3D needs one too, and I might have missed a bunch of them in that > series given how the current debugging of the remaining issues turn > out to be. Would be nice to see if V3D is also affected by DVFS, and the rest of clocks for that matter. > And clk_lookups are local to devices, so you need to factor that by the > number of devices you have. Sure, it works, but it feels to me like that's > going to be an issue pretty fast, especially with the lookups on the way out? I see your point, TBH I don't mind moving it into the device-tree if things are going to get nasty. > > > drivers/clk/bcm/clk-raspberrypi.c | 11 ++++++++--- > > > 1 file changed, 8 insertions(+), 3 deletions(-) > > > > > > diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk- > > > raspberrypi.c > > > index 1654fd0eedc9..94870234824c 100644 > > > --- a/drivers/clk/bcm/clk-raspberrypi.c > > > +++ b/drivers/clk/bcm/clk-raspberrypi.c > > > @@ -255,15 +255,13 @@ static int raspberrypi_clk_probe(struct > > > platform_device > > > *pdev) > > > struct raspberrypi_clk *rpi; > > > int ret; > > > > > > - firmware_node = of_find_compatible_node(NULL, NULL, > > > - "raspberrypi,bcm2835-firmware"); > > > + firmware_node = of_parse_phandle(dev->of_node, "raspberrypi,firmware", > > > 0); > > > > There is no such phandle in the upstream device tree. Maybe this was aimed > > at > > the downstream dt? > > raspberrypi,firmware is the property, it points to the /soc/firmware > node that is defined in bcm2835-rpi.dtsi Yes, my bad. On that topic, I kind of like Robh's suggestion of making this driver a child of the firmware node (see an example in input/touchscreen/raspberrypi-ts.c). Regards, Nicolas [-- Attachment #1.2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 488 bytes --] [-- Attachment #2: Type: text/plain, Size: 160 bytes --] _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 161+ messages in thread

* Re: [PATCH 25/89] reset: simple: Add reset callback 2020-02-24 9:06 ` [PATCH 25/89] reset: simple: Add reset callback Maxime Ripard @ 2020-03-04 12:03 ` Philipp Zabel 0 siblings, 0 replies; 161+ messages in thread From: Philipp Zabel @ 2020-03-04 12:03 UTC (permalink / raw) To: Maxime Ripard, Nicolas Saenz Julienne, Eric Anholt Cc: Tim Gover, Dave Stevenson, linux-kernel, dri-devel, bcm-kernel-feedback-list, linux-rpi-kernel, Phil Elwell, linux-arm-kernel Hi Maxime, On Mon, 2020-02-24 at 10:06 +0100, Maxime Ripard wrote: > The reset-simple code lacks a reset callback that is still pretty easy to > implement. The only real thing to consider is the delay needed for a device > to be reset, so let's expose that as part of the reset-simple driver data. > > Cc: Philipp Zabel <p.zabel@pengutronix.de> > Signed-off-by: Maxime Ripard <maxime@cerno.tech> This shoulod be done in such a way that simple reset drivers which do not set the reset delay continue to return -ENOTSUPP from reset_control_reset(). > --- > drivers/reset/reset-simple.c | 21 +++++++++++++++++++++ > include/linux/reset/reset-simple.h | 4 ++++ > 2 files changed, 25 insertions(+) > > diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c > index c854aa351640..7a8c56512ae9 100644 > --- a/drivers/reset/reset-simple.c > +++ b/drivers/reset/reset-simple.c > @@ -11,6 +11,7 @@ > * Maxime Ripard <maxime.ripard@free-electrons.com> > */ > > +#include <linux/delay.h> > #include <linux/device.h> > #include <linux/err.h> > #include <linux/io.h> > @@ -63,6 +64,25 @@ static int reset_simple_deassert(struct reset_controller_dev *rcdev, > return reset_simple_update(rcdev, id, false); > } > > +static int reset_simple_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + struct reset_simple_data *data = to_reset_simple_data(rcdev); > + int ret; You could just return -ENOTSUPP here if data->reset_ms == 0. > + ret = reset_simple_assert(rcdev, id); > + if (ret) > + return ret; > + > + mdelay(data->reset_ms); Have you considered specifying the delay in microseconds instead? That would allow to use usleep_range() for shorter delays. > + ret = reset_simple_deassert(rcdev, id); > + if (ret) > + return ret; > + > + return 0; > +} > + > static int reset_simple_status(struct reset_controller_dev *rcdev, > unsigned long id) > { > @@ -80,6 +100,7 @@ static int reset_simple_status(struct reset_controller_dev *rcdev, > const struct reset_control_ops reset_simple_ops = { > .assert = reset_simple_assert, > .deassert = reset_simple_deassert, > + .reset = reset_simple_reset, > .status = reset_simple_status, > }; > EXPORT_SYMBOL_GPL(reset_simple_ops); > diff --git a/include/linux/reset/reset-simple.h b/include/linux/reset/reset-simple.h > index 08ccb25a55e6..a5887f6cbe50 100644 > --- a/include/linux/reset/reset-simple.h > +++ b/include/linux/reset/reset-simple.h > @@ -27,6 +27,9 @@ > * @status_active_low: if true, bits read back as cleared while the reset is > * asserted. Otherwise, bits read back as set while the > * reset is asserted. > + * @reset_ms: Minimum delay in milliseconds needed that needs to be > + * waited for between an assert and a deassert to reset the > + * device. If multiple consumers with different delay requirements are connected to this reset controllers, this must the largest minimum delay. Could you add mention for this in the comment? regards Philipp _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 161+ messages in thread

* Re: [PATCH 87/89] drm/vc4: hdmi: Support the BCM2711 HDMI controllers 2020-02-24 9:07 ` [PATCH 87/89] drm/vc4: hdmi: Support the BCM2711 HDMI controllers Maxime Ripard @ 2020-03-17 18:25 ` Daniel Rodriguez 0 siblings, 0 replies; 161+ messages in thread From: Daniel Rodriguez @ 2020-03-17 18:25 UTC (permalink / raw) To: dri-devel, maxime Cc: tim.gover, dave.stevenson, nsaenzjulienne, linux-kernel, bcm-kernel-feedback-list, linux-rpi-kernel, phil, linux-arm-kernel On 2/24/20 4:07 AM, Maxime Ripard wrote: > static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) > { > struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; > @@ -1314,6 +1438,92 @@ static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) > return 0; > } > This function fails on my Raspberry Pi 4 running patched 5.6-rc6. The errors printed to syslog are as follows: [ 15.167559] vc4-drm gpu: [drm] *ERROR* fbdev: Failed to setup generic emulation (ret=-22) [ 46.116273] WARNING: CPU: 2 PID: 1057 at drivers/gpu/drm/vc4/vc4_hdmi_phy.c:414 vc5_hdmi_phy_init+0x7b4/0x2078 [vc4] [ 47.127798] Timeout waiting for VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE [ 47.127865] WARNING: CPU: 1 PID: 1057 at drivers/gpu/drm/vc4/vc4_hdmi.c:652 vc4_hdmi_encoder_enable+0x1518/0x1e10 [vc4] [ 47.128353] WARNING: CPU: 1 PID: 1057 at drivers/gpu/drm/vc4/vc4_hdmi.c:671 vc4_hdmi_encoder_enable+0x18c8/0x1e10 [vc4] ----------------------------------------------------------------- Backtrace: [ 46.116373] pc : vc5_hdmi_phy_init+0x7b4/0x2078 [vc4] [ 46.116386] lr : vc4_hdmi_encoder_enable+0x1cc/0x1e10 [vc4] [ 46.116440] vc5_hdmi_phy_init+0x7b4/0x2078 [vc4] [ 46.116451] vc4_hdmi_encoder_enable+0x1cc/0x1e10 [vc4] [ 46.116497] vc4_atomic_complete_commit+0x3f0/0x530 [vc4] [ 46.116508] vc4_atomic_commit+0x1d8/0x1f8 [vc4] The specific offending conditional (before the warning on line 652) under vc4_hdmi_encoder_enable() in drm/vc4/vc4_hdmi.c: 645 if (vc4_encoder->hdmi_monitor) { 646 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 647 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 648 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 649 650 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 651 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 652 WARN_ONCE(ret, "Timeout waiting for " 653 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE

"); Which causes vc4_hdmi_encoder_enable() to fail. The failure of vc5_hdmi_phy_init() earlier left the phy inactive, causing the encoder enabling function above to fail. The offending code around line 414 in vc4_hdmi_phy.c, under vc5_hdmi_phy_init() reads 411 HDMI_WRITE(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, word_sel); 412 413 HDMI_WRITE(HDMI_TX_PHY_CTL_3, 414 VC4_SET_FIELD(phy_get_cp_current(vco_freq), 415 VC4_HDMI_TX_PHY_CTL_3_ICP) | 416 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP) | 417 VC4_SET_FIELD(1, VC4_HDMI_TX_PHY_CTL_3_CP1) | 418 VC4_SET_FIELD(3, VC4_HDMI_TX_PHY_CTL_3_CZ) | 419 VC4_SET_FIELD(4, VC4_HDMI_TX_PHY_CTL_3_RP) | 420 VC4_SET_FIELD(6, VC4_HDMI_TX_PHY_CTL_3_RZ)); As the hdmi-related timeout occurs 30 seconds after the drm failure, I'm bound to believe that the timeout occurs due to the drm setup failure leaving nothing for the phy functions to act on. Earlier in the syslog an error potentially related to the VC4_SET_FIELD(phy_get_cp_current(vco_freq) failure: [ 3.729745] raspberrypi-clk raspberrypi-clk: Missing firmware node [ 3.743915] raspberrypi-clk: probe of raspberrypi-clk failed with error -2 I thought the patch series added the firmware node? Perhaps the bcm2835 clock stub in the bcm2835 common dts is not being imported in the bcm2711 devicetree? The result is a connected hdmi monitor has signal from the simple framebuffer until the failed modeswitch, upon which it loses signal. I'm looking around for these possibilities in the kernel tree, though I thought the code worked as it was? I did have to disable CONFIG_DRM_VC4_HDMI_CEC in Kconfig to get the patches to compile as another user in linux-arm-kernel discovered the CEC code relied on removed functions (Jian-Hong Pan). I still hope these patches can be cleaned up/fixed to make the 5.7 merge window. Daniel Rodriguez _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 161+ messages in thread

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