Introduction

The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The processor is the first released model in Cobham Gaisler's RiSC-V line of processors that complement the LEON line of processors.

The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.

The NOEL-V is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.

The NOEL-V processor has the following features:

RISC-V 64-bit architecture, 32-bit version scheduled for 2020

Hardware multiply and divide units



Compressed (16 bit) instruction support



Atomic instruction extension



32/64 bit floating point extensions using non-pipelined area efficient FPU or high-performance fully pipelined IEEE-754 FPU



Machine, supervisor and user mode. RISC-V standard MMU with configurable TLB.



User level interrupts

RISC-V standard PLIC

RISC-V standard PMP (physical memory protection)

RISC-V standard external debug support

Advanced dual-issue in-order pipeline

Dynamic branch prediction, branch target buffer and return address stack

Four full ALUs, two of them late in the pipeline to reduce stalls

Separate instruction and data L1 cache (Harvard architecture) with snooping

Optional L2 cache: 256-bit internal, 1-4 ways, 16 KiB - 8 MiB

Native AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide.

Subsystem including processor and Level-2 cache with AXI4 backend also available.

Robust and fully synchronous single-edge clock design

Extensively configurable

Large range of software tools: compilers, kernels and debug monitors

High Performance*: CoreMark: 4.03** / 4.69*** CoreMark/MHz

*For HPP64 configuration. CoreMark score varies with processor configuration, microarchitectural changes, and toolchains. The CoreMark score is preliminary and will be updated for the v4 and v5 milestones.

**-march=rv64im -mabi=lp64 -O2 -funroll-all-loops -funswitch-loops -fgcse-after-reload -fpredictive-commoning -mtune=sifive-7-series

-finline-functions -fipa-cp-clone -falign-functions=8 -falign-loops=8 -falign-jumps=8 --param max-inline-insns-auto=20 using GCC 9.2.0 under RTEMS 5

*** Using "#define ee_u32 int32_t" in core_portme.h, as is common for 64 bit RISC-V.

Synthesis The NOEL-V processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

Software development

The NOEL-V processor implements the RISC-V ISA which means that compilers and kernels for RISC-V can be used with NOEL-V (kernels will need a NOEL-V BSP). To simplify software development, Cobham Gaisler provides several toolchains. At the initial release, the NOEL-V processor will be supported by pre-built RTEMS toolchains. Over time, the NOEL-V software support will be extended to the same level of support that exists for the LEON line of processors

The GRMON monitor interfaces to the NOEL-V on-chip debug support unit, implementing a large range of debug functions including GDB support for source level debugging.

Configurations

The NOEL-V processor core is available as part of a subsystem that also contains system peripherals. The subsystem can be configured to use the processor configurations listed in the table below. The configurations listed below are the ones recommended by Cobham Gaisler since they are covered by regression tests. Software toolchains provided by Cobham Gaisler are developed and built considering the same configurations. It is also possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem.

Configuration ISA* Pipeline Cache MMU PMP FPU Note Availbility TIN32 RV32IMAC single issue no no no no Tiny configuration Milestone v4 MIN32 RV32IMAC single issue yes no yes no Minimal 32-bit configuration Milestone v4 MIN64 RV64IMAC single issue yes no yes no Minimal 64-bit configuration Milestone v4 GPP32 RV32GCHN single issue yes yes yes GRFPU or NanoFPU General purpose 32-bit configuration Milestone v4 GPP64 RV64GCHN single issue yes yes yes GRFPU or NanoFPU General purpose 64-bit configuration Milestone v4 HPP32 RV32GCHN dual issue yes yes yes GRFPU or NanoFPU High-performance 32-bit configuration Milestone v4 HPP64** RV64GCHN dual issue yes yes yes GRFPU or NanoFPU High-performance 64-bit configuration Milestone v3

Note*: Key for ISA column:

RV32I - 32-bit Base Integer instructions

RV64I - 64-bit Base Integer instructions

M - Hardware support for multiply and division

A - Atomics

FD - Single/Double Floating Point

G - short for IMAFD

C - Compressed

H - Hardware hypervisor support

N - User-level interrupts

Note: **The 2020-June-30 release of NOEL-V does not support the C, H and N extensions for the HPP64 configuration. This is planned for the v4 release that will be available later in 2020 (please see milestone table in the Availbility section below). The 2020-June-30 relase of the NOEL-V RISC-V 64-bit processor supports the RV64G instruction set (RV64IMAFD) and has the following limitations compared to the full HPP64 configuration:

Does not support the H, C, N and B extensions

The floating-point implementation shall be considered as experimental as the verification effort is ongoing. Only NanoFPU is supported.

The model cannot be implemented with fault-tolerance features enabled

Note: Fault tolerance features can be enabled, as applicable and following the v4 milestone, for all the configurations above.

Note: The standard configurations are may be further detailed and may also be extended when additional extensions are supported by NOEL-V. For example, the B extension may become part of the standard configurations in the future.

Availability

NOEL-V is part of the GRLIB IP Library from release 2020.2 There are also pre-built FPGA development board bitstreams available. Additional features for the NOEL-V processor will become available as part of milestone releases. The table below shows the planned milestones. Please note that the future milestone features and dates are tentative.

Milestone Description Date v0 First RV64IMC release. Available as NOEL-XCKU example design. 2019-Dec v1 - v2 Source release to first adopters, with the following features: RV64IMAC

VIPT cache 2020-Apr v3 The v3 release is the first generally available source release. Allows to create SoCs equivalent to LEON3/4/5 systems in terms of functionality: RV64GC+HN (see note about FD and H below)

FD extension (experimental - not fully verified)

A extension and multi-core support

Improved debug interface. Breakpoint and watchpoint triggers.

Performance counters (internal) and external event signals Support for HPP64 configuration. 2020-Jul v4 The v4 release adds fault-tolerance features and introduces configurations that are suitable for more FPGA implementations

(requiring fewer logic resources to implement the processor core). New functionality: Release of fault-tolerance support

FD extension

H extension

N extension

B extension Support for TIN32, MIN32, GPP32, GPP64, HPP32 configurations. 2020-Dec v5 - ... Features under consideration for the v5 release and beyond include: FT adaptations to specific target technologies.

Multi-port bus connection between processor core and L2 cache

P and V extensions

Support for more resource efficient floating-point implementations 2021

The NOEL-V is part of Cobham Gaisler's free open source GRLIB IP Library (the pipelined GRFPU5 is a commercial-only offering and will not be included in the free open source distribution). NOEL-V is also available under a low-cost commercial license, allowing it to be used in any commercial application. The commercial NOEL-V license includes:

High-performance pipeline GRFPU5 floating-point unit

The L2CACHE Level-2 cache controller

GRIOMMU IO memory management unit

Additional peripheral IP as described in the GRLIB IP Core User's Manual

Demonstration systems and documentation



GRLIB IP Library

NOEL-V documentation is available in the GRLIB IP Library User's Manual - NOEL-V subsystem.

FPGA programming files are also available, please see the NOEL-XCKU example design.

Community



Cobham Gaisler AB maintains a Discourse forum for those interested in the open source company's processor products.