I was recently presented, as a mere onlooker, with the potential differences that exist in the syntax of a Makefile for anything non-trivial, when using different implementations of make .

(For the uninitiated, a Makefile is essentially a list of recipes that are automatically followed to build some targets from given dependencies, and are usually used to describe how to compile a program. Different implementations of make , the program that reads the Makefile s and runs the recipes, exist; and the issue is that for anything beyond the simplest of declarations and recipe structure, the syntax they support is different, and incompatible.)

Used as I was to using GNU make and its extensive set of functions and conditionals and predefined macros and rules, I rarely bothered looking into alternatives, except maybe for completely different build systems or meta-build-systems (the infamous GNU autotools, cmake, etc). However, being presented with the fact that even simple text transformations could not be done in the same way across the two major implementations of make (GNU and BSD) piqued my curiosity, and I set off to convert the rather simple (but still GNU-dependent) Makefile of my clinfo project to make it work at least in both GNU and BSD make .

Get the code for

clinfo: gitweb clinfo git clinfo GitHub clinfo

Since clinfo is a rather simple program, its Makefile is very simple too:

it defines the path under which the main source file can be found; it defines a list of header files, on which the main source file depends; it detects the operating system used for the compilation; it selects libraries to be passed to the linker to produce the final executable ( LDLIBS ), based on the operating system.

The last two points are necessary because:

under Linux, but not under any other operating system, the dl library is needed too;

library is needed too; under Darwin, linking to OpenCL is done using -framework OpenCL , whereas under any other operating system, this is achieved with a simpler -lOpenCL (provided the library is found in the path).

In all this, the GNU-specific things used in the Makefile were:

the use of the wildcard function to find the header files; the use of the shell function to find the operating system; the use of the ifeq / else / endif conditionals to decide which flags to add to the LDLIBS .

Avoiding wildcard

In my case, the first GNUism is easily avoided by enumerating the header files explicitly: this has the underside that if a new header file is ever added to the project, I should remember to add it myself.

(An alternative approach would be to use some form of automatic dependency list generation, such as the -MM flag supported by most current compiles; however, this was deemed overkill for my case.)

(A third option, assuming a recent enough GNU make , is presented below.)

Avoiding shell

BSD make supports something similar to GNU make 's shell function by means of the special != assignment operator. The good news is that GNU make has added support for the same assignment operator since version 4 (introduced in late 2013). This offers an alternative solution for wildcard as well: assigning the output of ls to a variable, using != .

If you want to support versions of GNU make older than 4, though, you're out of luck: there is no trivial way to assign the output of a shell invocation to a Makefile variable that works on both GNU and BSD make (let alone when strict POSIX compliance is required).

If (and only if) the assignments can be done ‘before’ any other assignment is done, it is however possible to put them into a GNUmakefile (using GNU's syntax) and makefile (using BSD's syntax), and then have both of these include the shared part of the code. This works because GNU make will look for GNUmakefile first.

In my case, the only call to shell I had was a $(shell uname -s) to get the name of the operating system. The interesting thing in this case is that BSD make actually defines its own OS variable holding just what I was looking for.

My solution was therefore to add a GNUmakefile which defined OS using the shell invocation, and then include the same Makefile which is parsed directly by BSD make .

Conditional content for variables

Now comes the interesting part: we want the content of a variable ( LDLIBS in our case) to be set based on the content of another variable ( OS in our case).

There are actually two things that we want to do:

(the simple one) add something to the content of LDLIBS only if OS has a specific value; (the difficult one) add something to the content of LDLIBS only if OS does not have a specific value.

Both of these would be rather trivial if we had conditional statements, but while both BSD and GNU make do have them, their syntax is completely incompatible. We therefore have to resort to a different approach, one that leverages features present in both implementations.

In this case, we're going to use the fact that when using a variable, you can use another variable to decide the name of the variable to use: whenever make comes across the syntax $(foo) (or ${foo} ), it replaces it with the content of the foo variable. The interesting thing is that this holds even within another set of $() or ${} , so that if foo = bar and bar = quuz , then $(${foo}) expands to $(bar) and thus ultimately to quuz .

Add something to a variable only when another variable has a specific value

This possibility actually allows us to solve the ‘simple’ conditional problem, with something like:

LDLIBS_Darwin = -framework OpenCL LDLIBS_Linux = -ldl LDLIBS += ${LDLIBS_$(OS)}

Now, if OS = Darwin , LDLIBS will get extended by appending the value of LDLIBS_Darwin ; if OS = Linux , LDLIBS gets extended by appending the value of LDLIBS_Linux , and otherwise it gets extended by appending the value of LDLIBS_ , which is not defined, and thus empty.

This allows us to achieve exactly what we want: add specific values to a variable only when another variable has a specific value.

Add something to a variable only when another variable does not have a specific value

The ‘variable content as part of the variable name’ trick cannot be employed as-is for the complementary action, which is adding something only when the content of the control variable is not some specific value (in our case, adding -lOpenCL when OS is not Darwin ).

We could actually use the same trick if the Makefile syntax allowed something like a -= operator to ‘remove’ things from the content of a variable (interestingly, the vim scripting and configuration language does have such an operator). Since the operator is missing, though, we'll have to work around it, and to achieve this we will use the possibility (shared by both GNU and BSD make ) to manipulate the content of variables during expansion.

Variable content manipulation is another field where the syntax accepted by the various implementations differs wildly, but there is a small subset which is actually supported by most of them (even beyond GNU and BSD): the suffix substitution operator.

The idea is that often you want to do something like enumerate all your source files in a variable sources = file1.c file2.c file3.c etc and then you want to have a variable with all the object files that need to be linked, that just happen to be the same, with the .c suffix replaced by .o : in both GNU and BSD make (and not just them), this can be achieved by doing objs = $(sources:.c=.o) . The best part of this is that the strings to be replaced, and the replacement, can be taken from the expansion of a variable!

We can then combine all this knowledge into our ‘hack’: always include the value we want to selectively exclude, and then remove it by ‘suffix’ substitution, where the suffix to be replaced is defined by a variable-expanded variable name: a horrible, yet effective, hack:

LDLIBS = -lOpenCL LDLIBS_not_Darwin = -lOpenCL LDLIBS := ${LDLIBS:$(LDLIBS_not_${OS})=}

This works because when OS = Darwin , the substitution argument will be $(LDLIBS_not_Darwin) which in turn expands to -lOpenCL , so that in the end the value assigned to LDLIBS will be ${LDLIBS:-lOpenCL=} , which is LDLIBS with -lOpenCL replaced by the empty string. For all other values of OS , we'll have ${LDLIBS:=} which just happens to be the same as ${LDLIBS} , and thus LDLIBS will not be changed

Cross-make selection

We can then combine both previous ideas:

LDLIBS = -lOpenCL LDLIBS_Darwin = -framework OpenCL LDLIBS_not_Darwin = -lOpenCL LDLIBS_Linux = -ldl LDLIBS += ${LDLIBS_$(OS)} LDLIBS := ${LDLIBS:$(LDLIBS_not_${OS})=}

And there we go: LDLIBS will be -framework OpenCL on Darwin, -lOpenCL -ldl on Linux, -lOpenCL on any other platform, regardless of wether GNU or BSD make are being used.

Despite the somewhat hackish nature of this approach (especially for the ‘exclusion’ case), I actually like it, for two reasons.

The first is, obviously, portability. Not requiring a specific incarnation of make is at the very least an act of courtesy. Being able to do without writing two separate, mostly duplicate, Makefile s is even better.

But there's another reason why I like the approach: even though the variable-in-variable syntax isn't exactly the most pleasurable to read, the intermediate variable names end up having a nice, self-explanatory name that gives a nice logical structure to the whole thing.

That being said, working around this kind of portability issues can make a developer better appreciate the need for more portable build systems, despite the heavier onus in terms of dependencies. Of course, for a smaller projects, deploying something as massive as autotools or cmake would still be ridiculous overkill: so to anyone that prefers leaner (if more fragile) options, I offer this set of solutions, in the hope that they'll help stimulate convergence.