In an engineering first, Stanford researchers have built a working prototype for a new type of memory chip that has the potential to store more data, using less space, than the flash memory chips found in smart phones, tablets and laptops today.

This new chip uses a technology called resistive random access memory or RRAM. Resistance slows down electrons. Conductivity lets electrons flow. By applying tiny jolts of voltage to carefully chosen materials, the Stanford engineers can toggle their RRAM chip between resistive and conductive states to create and store digital zeroes and ones.

In addition to creating a working RRAM chip, the Stanford team has also shown how to fabricate these devices using processes that could be scaled up to produce these new memory chips in volume.

The team will unveil its RRAM prototype and fabrication process at the International Electron Devices Meeting (IEDM) this week in Washington, D.C.

IEDM is the semiconductor industry’s premier technical conference, where major companies and universities worldwide report important advances.

Many technologists think RRAM technology is the next big thing in data storage. Just as flash memory once replaced hard disk drives, RRAM could supplant flash chips and help pave the way for new and even more useful mobile electronic devices.

But RRAM technology also has potential applications that go far beyond simply storing data, according to H.-S. Philip Wong, a professor of electrical engineering and leader of the Stanford team. The principles behind RRAMs, and the process used to make them, could spawn an entirely new type of hybrid chip, one that would combine memory and microprocessor on a single slice of silicon.

“We can look ahead and see that RRAM will remain useful for 10 or 15 years or more,” said Wong, the Willard R. and Inez Kerr Bell Professor in the School of Engineering.

Flash memory versus RRAM

The industry-wide interest in RRAM arises from the challenges facing flash memory.

Flash chips are made of silicon. A flash memory chip consists of billions of tiny cells or boxes etched onto a silicon chip. Data is stored by putting a specific number of electrons into each cell. That creates a one. Pushing these electrons out of the cell creates a zero.

To pack more data onto flash chips, engineers must shrink the size of each cell. Many technologists believe this process is approaching the point at which the cells will shrink so small as to make it impossible to confine and release electrons with the required degree of precision.

Resistive random access memory chips also store data in cells. So RRAM researchers must also make the cells on their chips as small as possible.

But because RRAMs store data differently, many researchers think it will be possible to continue this shrinking process beyond the point where flash chips begin to fumble electrons.

Yi “Alice” Wu, who recently earned her PhD in electrical engineering from Stanford, helped to design and fabricate the RRAM chip. She explained how it works at the level of the individual cell, that is, the unit on the device that actually stores the zeroes and ones.

Each storage cell consists of four materials: titanium nitride, titanium oxide, hafnium oxide and platinum. The four materials are deposited in layers. Hafnium oxide and titanium oxide are naturally resistive. But when voltage is applied to the top of this four-layered amalgam, the electric field pulls oxygen atoms away from the hafnium and titanium compounds and leaves behind a conductive pathway through the resistive materials.

When the voltage going to the cell is reversed, the conductive pathway is broken, and the hafnium oxide and titanium oxide become resistive again.

This change in state from resistive to conductive is the mechanism of storage. When the power is off, the RRAM cell remains in whatever state it was last in, which makes it useful for data storage.

A scalable process to create RRAMs

Linda He Yi, a doctoral student in Wong’s lab, oversaw the process of fabricating this RRAM prototype. She used a simple, cost-effective process to define the small memory cells. This process could be the key to making RRAMs in large volumes.

Yi began with a wafer of silicon. Her first goal was to make a series of nano-size etchings into this silicon wafer to create holes that would become data storage cells.

To do this, she coated the silicon chip with a two-part polymer – two different plastics joined together to form a single tiny strand. Imagine zillions of gummy worms, each blue on one end, green on the other, evenly distributed over the silicon chip. Heating the chip caused these gummy worms to arrange themselves perfectly – green with green, and blue with blue. This created billions of nano-islands, some green, others blue, on the silicon.

Using a series of chemical operations, the researchers washed away one of the polymers to create millions of bare spots on the silicon. Using light and chemistry, they etched tiny holes into these bare spots. They then removed the other polymer to leave behind an array of nanoscale indentations in the silicon wafer.

This part of the process is called diblock copolymer self-assembly lithography. Although the Stanford team did not invent the process, this is the first time it has been used to make a chip that works. Wong thinks this approach has the potential to scale up from the laboratory to the factory.

“We are very excited about this process,” Wong said. “Diblock copolymer self-assembly could produce nanoscale chips more efficiently and less expensively than the lithography techniques in use today.”

Final steps, future promise

Finishing the prototype RRAM required a few more steps. Yi had to fill each nano-hole in the chip with the four materials needed to create an RRAM data-storage cell.

She used existing fabrication techniques to deposit the materials. She wired the data storage cells together and made sure they could be toggled into resistive and conductive states. The prototype being presented at IEDM has 50 working cells, or roughly enough capacity to store a 10-digit phone number with a three-digit extension.

The Stanford researchers used a transmission electron microscope to create images of one of these RRAM cells. The image shows a cone-shaped structure 25 nanometers wide on top and 12 nanometers wide at the base, with an active device region of less than 10 nanometers. Future improvements will aim to make each storage unit narrower, so as to pack more storage in less space.

But Wong said the diameters of the cells on the prototype are already comparable to the size of the cells in today’s flash memory. And whereas flash may be bumping up against its limits, RRAM chips should be able to continue shrinking.

“I want to see how this technology works at 10 nanometers, five nanometers, one nanometer,” he said.

Even as they continue trying to develop RRAM for data storage, the researchers are also exploring how to use technology in new ways.

S. Simon Wong (no relation), a professor of electrical engineering and another member of the team, wants to build RRAM storage cells on the same slice of silicon as the logic circuits in a microprocessor.

Several years ago, members of the team showed that it was possible to put RRAM cells and logic circuits on the same chip. But the processes available at the time created RRAMs too large to coexist with today’s most advanced logic circuits.

But now, having shrunk the RRAMs to the same scale as the logic, it becomes possible to envision making hybrid chips that combine memory and logic functions, creating electronic devices that are smaller, faster and cheaper than anything available today.

“Putting memory and logic on the same chip will be less expensive to make, take up less space and consume less energy, making it possible to create smaller and more powerful devices,” Wong said.

Other members of the Stanford team include Zhiping Zhang, who recently earned his PhD in electrical engineering, and Zizhen Jiang and Joon Sohn, who are both graduate students in the department.

This work was supported in part by the Trusted Integrated Chips (TIC) program of the Intelligence Advanced Research Projects Activity. TIC seeks to develop and demonstrate new split-manufacturing chip fabrication processes that would assure security and protect intellectual property. Other funding sources include the member companies of the Stanford Non-Volatile Memory Technology Research Initiative, the National Science Foundation and the Semiconductor Research Corporation.

H.-S. Philip Wong, professor of electrical engineering at Stanford University

S. Simon Wong, professor of electrical engineering at Stanford University