Due to issues with wordpress htmlifying code of posts when I edit them to add next part links, I’ve created this page. Latest parts at the top.

RISC-V:

Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality

Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit

Designing a RISC-V CPU in VHDL, Part 17: DDR3 Memory Controller, Clock domain crossing

Designing a RISC-V CPU in VHDL, Part 16: Arty S7 RPU SoC, Block Rams, 720p HDMI

Designing a CPU in VHDL, Part 15: Introducing RPU

Github RPU CPU Repo

Github Arty S7-50 SoC Repo

TPU:

Designing a CPU in VHDL, Part 14: ISA changes, software interrupts and bugfixing that BIOS code

Designing a CPU in VHDL, Part 13: Memory system and BIOS beginnings

Designing a CPU in VHDL, Part 12: Text mode video output

Designing a CPU in VHDL, Part 11: VRAM and HDMI output

Designing a CPU in VHDL, Part 10b: A very irritating issue, resolved.

Designing a CPU in VHDL, Part 10: Interrupts and Xilinx block RAMs

Designing a CPU in VHDL, Part 9: Byte addressing, memory subsystem and UART

Designing a CPU in VHDL, Part 8: Revisiting the ISA, function calling, assembler

Designing a CPU in VHDL, Part 7: Memory Operations, Running on FPGA

Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching

Designing a CPU in VHDL, Part 5: Pipeline and Control Unit

Designing a CPU in VHDL, Part 4: The ALU, Comparisons and Branching

Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM

Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, register file, testing

Designing a CPU in VHDL, Part 1: Rationale, tools, method

Github repository with VHDL sources, ISE project, assembler and ISA.