Most discussions of 3D packaging involve silicon chips with millions and millions of transistors. Billions in the case of memory chips. TI’s PowerStack 3D packaging skews all the way to the other end of the spectrum. The die packaged in a PowerStack package each have one on-die transistor. One big on-die transistor. Yesterday, Texas Instruments announced that it has been shipping power transistor pairs in 3D PowerStack packages for more than a year and that it has already shipped more than 30 million of the devices. 3D advocates have been saying that power is a killer app for 3D and the technical details provided by TI with respect to PowerStack packaging clearly show why.

To understand why, let’s start with a photomicrograph cross section of a TI PowerStack component:

The packaged product consists of two power MOSFETs (high-side and low-side) sandwiched between relatively heavy copper conductors that TI calls “clips.” The low-side MOSFET is attached to a foundational pad that provides a ground connection for the stack. The Vsw clip connects the two MOSFETs in the stack and serves as a center conductor pin for the stack. A Vin clip supplies power to the high-side MOSFET. The resulting circuit looks like this:

This circuit diagram shows three equivalent circuits. The circuit on the left is the conventional schematic for a wire-bonded two-MOSFET stack and this diagram includes all of the resistive and inductive parasitic components introduced by conventional, wire-bonded packaging. TI’s PowerStack 3D packaging with its large copper bus bars make four of those parasitic components—two resistors and two inductors—“effectively disappear” as shown in the diagram’s center schematic. The resulting circuit, shown on the right side of the above diagram, contains only half of the parasitic components.

TI’s PowerStack construction delivers substantial benefits to designers: better power efficiency, improved thermal management, and board-space savings.

This next diagram illustrates the kind of power efficiency gained from PowerStack 3D packaging.

At high currents (around 20A), PowerStack packaging alone accounts for an additional 2% in circuit efficiency. If you’re designing high-efficiency power supplies or motor drivers, getting 2% efficiency improvement just from the power component’s package is important stuff, especially at these power levels. (It’s actually a 20% improvement in “inefficiency” if you look at it from the right perspective.) But there’s something that’s even more important: that electrical energy is no longer transforming into waste heat. It’s going into the power supply’s output—a double benefit. Less heat and more drive current.

Because the two power MOSFET die in the TI PowerStack package are stacked, the resulting device has roughly half of the footprint of a similar component that arranges the MOSFETs side-by-side. This space savings is increasingly important in all products—even a Web server’s overall volume becomes important when you’re sticking 100,000 of them in a building—but it’s especially important in mobile products where every cubic millimeter not occupied by electronics tends to be filled with battery. Smaller electronics means bigger batteries, which in turn leads to longer use and standby times, which make the product more attractive to purchasers.

For a pretty informative video describing this 3D Packaging technology, click here.

Finally, most of you might disregard the lessons from TI’s 3D PowerStack packaging because the end component is perhaps a billion or so transistors short of being interesting. Not so. The lessons of vanishing parasitic components, improved power efficiency, better thermal management, and reduced board footprint are universally important for all Silicon Realization teams, making the power-saving properties of 3D packaging a true killer app.