Graphene/SiO x /indium tin oxide (ITO) devices

We first chose graphene and ITO as the top and bottom electrode materials, respectively. Graphene represents a new class of two-dimensional material that is promising for future transparent electronics21, whereas ITO represents the mainstream choice for transparent conductive materials. The combination of the two electrode materials in a single device demonstrates the versatility of the SiO x -based memory with respect to the choice of transparent electrode materials. Vertical sandwiched pillar structures of G/SiO x /ITO (here G denotes graphene) were defined on a glass substrate (Fig. 1a). Specifically, the SiO x layer (~70 nm thick) was prepared by physical vapour deposition on a glass substrate coated with a layer of ITO (~120 nm thick), with the top electrode consisting of bilayer graphene prepared by the chemical vapour deposition method and transfer process22. Photolithography and reactive ion etching were then used to define the circular G/SiO x /ITO memory units at a diameter of ~100 μm for an easy probe-tip landing (Supplementary Fig. S1). The electrical characterizations were performed in vacuum (10−5 Torr) at room temperature in a probe station connected to an Agilent 4155C semiconductor parameter analyser.

Figure 1: Memory effect in a G/SiO x /ITO device. (a) Left panel: schematic of the G/SiO x /ITO device arrays on a glass substrate and the setup for electrical characterization. The top right panel shows the G/SiO x /ITO-layered structure on a glass substrate and the bottom right panel shows the optical images of the G/SiO x /ITO devices; scale bar, 100 μm. (b) I–V curves from an electroformed G/SiO x /ITO device, with the numbers indicating the voltage-sweep orders. Curves 1–4 are forward voltage sweeps (0→14 V), and curve 5 is backward voltage sweep (14→0 V). The voltage sweep rate is 2.8 V s−1 for this and the other I–V curves in this paper. (c) (Top panel) A series of voltage pulses of +6 V, +1 V (five times) and +14 V serve as set, read (five times) and reset operations, respectively. (Bottom panel) Currents corresponding to each read pulse in the top panel. (d) 300 memory cycles in a G/SiO x /ITO device. (e) Retention of the memory state tested by continuous +1 V voltage pulses (at a rate of 1 pulse per second) for both an ON and an OFF state. Full size image

Figure 1b shows a series of current–voltage (I–V) curves from a G/SiO x /ITO device after the electroforming process (Supplementary Fig. S2). In the characteristic I–V curve (black curve), starting from a high-resistance (OFF) state, the current level suddenly increases at ~4 V to a low-resistance (ON) state and then decreases at ~10 V. The current or conductance increase and decrease define the set and reset values, respectively17,20, indicating unipolar resistive switching behaviour. The resistance or memory state can be read at a low-voltage bias (<3 V) without altering its value, featuring the nonvolatile property. Figure 1c,d shows a series of memory cycles using +1, +6 and +14 V as read, set and reset voltages, respectively. Note that more detailed mechanistic discussions with respect to the phenomenological behaviours of the set and reset processes can be found in ref. 18. The nonvolatility or memory retention was tested by continuous memory-state readout at + 1 V, which showed no degradation after 5×104 s (Fig. 1e). This is consistent with our previous study showing that the memory state is robust in ambient environment for more than 3 months23. After testing more than 20 devices, a device yield of ~70% was achieved for the tested memory units, discounting the possibility of a contamination-related memory effect. The device failure is defined as either the failure to electroform the device (up to 40 V) or a state of non-switchable conducting (short circuited) after the attempt of electroforming. However, this depressed yield compared with that achieved in devices with polysilicon electrodes17 is likely caused by the atomically thin nature of the graphene electrode, as structural damage in the graphene layer might result during the processing and/or the probe-tip landing processes, during which the contacting pressure could not be well monitored (Fig. 1a). The resultant damage could cause sliding of the graphene electrode towards the etched edge region of the device or the direct puncture and penetration of oxide, and hence, shorting of the devices, thereby lowering the yield. Note that the possibility of extrinsic switching through metal filament formation from the tungsten probe tip in contact with the top electrode was ruled out by control experiments in which memory switching could not be achieved in devices that were devoid of the top graphene electrodes (Supplementary Fig. S3). Note that the I–V curves in the reset region generally involve current fluctuations23 (blue curve, Fig. 1b), which prevent a clear definition of the threshold value of the reset voltage. The current fluctuations are indications of the dynamic and competing effects between the set and reset processes18. We therefore performed a series of measurement on the set voltages, as well as the ON and OFF currents, showing a comparatively narrow distribution of the set voltages (4.26±0.54 V) and the ON/OFF ratios are between 103 and 106 (Supplementary Fig. S4).

G/SiO x /G devices

The intrinsic memory switching in SiO x enables the construction of completely metal-free transparent memory devices by using graphene as the only electrode material. For the fast progress in synthesis and abundance in the carbon sources24,25,26, graphene has become a promising candidate for transparent electrode materials21,25. The use of graphene and SiO x , another low-cost and industry-standard material, as the only materials for constructing memory devices, therefore, comes with the advantages both in the material composition and processing. This is in contrast to other transparent resistive switching memory based on traditional metal-oxide materials11,12,13, for which low-cost replacements such as graphene have been sought21,25. As shown in Fig. 2a, vertical sandwiched pillar structures of G/SiO x /G with the same diameters (~100 μm) were defined on the glass substrate (Supplementary Fig. S5), which shows 90% transparency at 550 nm (Fig. 2b). Specifically, bilayer graphene sheets were used for both the top and bottom electrodes with the SiO x thickness ~70 nm. The devices showed similar resistive switching I–V curves and memory property (Fig. 2c,d) to those exhibited in Fig. 1 at a yield of 65% with over 20 devices being tested; the 35% non-operating devices being short circuited. The use of graphene as both top and bottom electrodes further indicates the intrinsic memory property of SiO x by excluding the possibility of metal filament formation from the electrode materials. Note that although graphene and graphene oxide have been used in some resistive switching systems, the inevitable use of metal electrodes limits the transparency of the memory devices27,28. Because of the low optical absorbance in graphene29, uniform transmittance as high as ~90% over the entire visible range is achieved in the G/SiO x /G devices (Fig. 2b). Note that here bilayer graphene was used for both the top and bottom electrodes for the purpose of better coverage. It is not due to an intrinsic limit with respect to the resistance. In fact, as the ON-state resistance of SiO x is ≫10 kΩ (Fig. 2d), doped monolayer graphene (<1 kΩ sq −1)21 can serve as the electrode material. As a result, the transmittance can be further increased to ~95% (blue curve, Fig. 2b), which is higher and more uniform than those achieved in other systems11,12,13,30.

Figure 2: Memory effect in a G/SiO x /G device. (a) Schematic of the G/SiO x /G device on glass. (b) Optical transmittance in G/SiO x /G-layered structures with different layer thicknesses of graphene. The green, blue and black curves correspond to the transmittance in MLG/SiO x /MLG, MLG/SiO x /BLG and BLG/SiO x /BLG structures. Here BLG and MLG denote bilayer graphene and monolayer graphene, respectively. (c) Characteristic I–V curves from an electroformed G/SiO x /G device. The arrows indicate the voltage-sweep directions and the numbers indicate the order. (d) Corresponding memory cycles from the device using +6 and +15 V as set and reset voltages, respectively. The programming current is not shown here and the memory states (current) were recorded at +1 V. Full size image

Although the vertical pillar structures adopted above are frequently used for single-device testing purpose16, the implementation of the memory device relies on the construction of crossbar arrays10,16. We further demonstrate the transparent SiO x crossbar memory arrays with graphene serving as both the electrode and interconnect material, in this case constructed atop a silicon/silicon oxide substrate. Figure 3a shows a 4×4 SiO x crossbar structure with the SiO x (~70 nm thick) sandwiched between the top and bottom bilayer graphene lines. Figure 3b,c show the typical I–V curve and memory switching cycles from one of the crossbar units (20×20 μm2), featuring the same switching characteristics as those shown in the vertical pillar structures. The observed ON and OFF currents fall into the same range as those observed in vertical pillar structures (Supplementary Fig. S4). The crossbar structure with both the top and bottom electrodes extended through the graphene lines avoids the direct contact between the probe tip and the memory unit during the electrical testing, which eliminates the possibility of metal contamination from the probe tip and, hence, further confirms the intrinsic memory effects in SiO x . This may have also contributed to an increased device yield to ~80% (16 of 20 devices) due to the absence of damage from the probe tip to the graphene electrodes as discussed before. The SiO x memory here features low programming current levels (~0.1 mA, Fig. 3b), more than one order of magnitude lower than those in other transparent resistive memory systems11,12,13,30. Consequently, despite a working voltage up to 15 V, the devices still feature an approximately tenfold reduction in the power-consumption factor (the product of current and voltage) during programming compared with those in other transparent resistive memories11,12,13. The reduced programming currents lower the current densities in the interconnects, providing more area for the transparent interconnects for a transparent circuit.

Figure 3: Memory effect in a G/SiO x /G crossbar structure. (a) Optical image of the 4×4 G/SiO x /G crossbar structure (right panel), with the illustration showing the perspective view of the memory unit. Scale bar, 20 μm. (b) Characteristic I–V curves from an electroformed crossbar memory unit. (c) 100 memory cycles from the device using +5 and +15 V as set and reset voltages, respectively. The programming current is not shown here and the memory states (current) were recorded at +1 V. Full size image

The versatile transfer process of graphene to various substrates21 also enables the fabrication of the memory devices on plastic transparent films. We fabricated G/SiO x /G devices using both crossbar and pillar structures on a plastic (fluoropolymer, PFA) substrate (Fig. 4a,b). Here a fluoropolymer was chosen as the plastic substrate for its comparatively high-melting point (>280 °C) in order to sustain the current local heating involved during the initial electroforming process in the G/SiO x /G devices. The electroformed devices showed the same memory switching characteristics (Fig. 4c and Supplementary Fig. S6a) as those from devices on rigid substrates. Similar device yields of ~70% were achieved in the crossbar structures (Fig. 4a). The yield was comparatively low (~20%) for the pillar structures (Fig. 4b); the lowered yield in the pillar structure was largely due to the direct contacting between the probe tip and the memory unit during electrical characterization. Unlike the rigid substrate, the flexibility in the plastic substrate made control of the contacting pressure between the probe tip and device surface difficult, and probe-tip-induced local curvature of the device likely resulted in damage to the SiO x layer and, hence, the decreased yield. Both structures showed no memory-state degradation on bending the flexible plastic substrate (Fig. 4d and Supplementary Fig. S6b), demonstrating the feasibility of both transparent and flexible memory applications.

Figure 4: Flexible transparent memory devices. (a) (Left panel) Schematic of the G/SiO x /G crossbar structures on a plastic (fluoropolymer) substrate and (right panel) the optical image of the structures. Scale bar, 20 μm. (b) Optical image of the G/SiO x /G pillar structures with the inset showing the schematic image. Scale bar, 100 μm. (c) Memory cycles from one of the crossbar devices using +5 and +14 V as set and reset voltages, respectively. The programming current is not shown here and the memory states (current) were recorded at +1 V. (d) Retention of both ON and OFF memory states (read at +1 V) from a crossbar device is shown on bending the plastic substrate around a ~1.2-cm diameter curvature; the central devices on the sheet being tested throughout the bending cycles. The inset shows the actual transparent memory devices using the pillar structures on the plastic substrate. Full size image

Planar G–SiO x –G nanogap devices

Although the transparent memory devices demonstrated above all use the common vertical sandwiched structures, they can also be made in the planar configuration. Topologically, the vertical G–SiO x –G structure is equivalent to the planar G–SiO x –G nanogap system (Fig. 5a). For the demonstration, we transferred graphene onto a silicon substrate capped with 500-nm-thick SiO 2 . The graphene layer was patterned with electron-beam lithography and then etched into stripes and then contacted by electrodes (2 nm Ti/30 nm Au) with a channel length ~2 μm (top panel, Fig. 5b). Electrical breakdown was induced (Supplementary Fig. S7a) in the graphene stripe to generate a narrow disruption region or nanogap19 (bottom panel, Fig. 5b). The size of the nanogap is usually 10–60 nm, close to the thickness of SiO x layer used in the vertical G/SiO x /G devices. The electroforming of SiO x in the nanogap (Supplementary Fig. S7b) region usually occurs immediately after the breakdown event in the graphene stripe, most likely due to the existence of local confinement so that high field is easily attained locally. It features a reduced electroforming voltage compared with the typical value obtained from the pristine vertical structure (Supplementary Fig. S2). This material-assisted local-field enhancement offers another route to bring down the electroforming voltage apart from thermal annealing17. As a result, a thin layer of conducting molecules or carbon materials could be coated over the SiO x surface region to induce local-field enhancement for reduction of the electroforming voltage20. The switching properties obtained in this planar nanogap configuration are similar to those from vertical structures, confirming the same switching mechanism intrinsic to SiO x 18. Note that more detailed discussions about this intrinsic SiO x switching mechanism are covered in our previous studies17,18,19,20.