'High rise' 3D chips are ready for Big Data

In a development which could help address the current data processing limitations of today's technology, a team of Stanford engineers has pioneered a scalable 3D computer chip that interconnects logic and memory.

The researchers believe that with further work, the advance could enable large amounts of data to be processed quickly and more efficiently.



The approach involves building layers of logic atop layers of memory to create a tightly interconnected 'high rise' chip. According to lead researcher Subhasish Mitra, the sheer number of short distance connections would allow the data to travel much faster, using less electricity, sidestepping the problem of bottlenecking almost completely.



The innovation leverages three breakthroughs. The first is a new technology for creating transistors, while the second is a new type of computer memory that lends itself to multi-story fabrication. The third is a technique to build these new logic and memory technologies into high rise structures in a different way than previous efforts to stack chips.



"This research is at an early stage, but our design and fabrication techniques are scalable," Mitra said. "With further development this architecture could lead to computing performance that is much, much greater than anything available today."

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