Designing, integrating and assembling heterogeneous packages from blocks developed at any process node or cost point is proving to be far more difficult than expected, particularly where high performance is one of the main criteria.

At least part of the problem is there is a spectrum of choices, which makes it hard to achieve economies of scale. Even where there is momentum for a particular approach, such as 2.5D packages with chips developed at the most advanced nodes, the silicon interposers used to connect different die remain proprietary. On top of that, there is a long list of technical issues involving bonding, cleaning, warpage, as well as a variety of physical effects that generally were assumed to be non-issues with packaging.

“One of the questions we get asked a lot is what is the right packaging platform for heterogeneous integration,” said Suresh Ramalingam, a Xilinx fellow in charge of the company’s advanced packaging. “That requires multi-dimensional thinking about the architecture. The answer can be different, depending on how you are partitioning an FPGA, CPU or GPU. It’s a very difficult question, and it is not easy to define standards.”

That isn’t for lack of trying. The whole chiplet approach, for example, is aimed at integrating individual dies in a package using a die-to-die interconnect. Several groups are attempting to hammer out common specs for interconnects, among other things, including IEEE, DARPA and at least one group of companies. None of those is in place yet.

Still, that doesn’t mean advanced packaging is in trouble. There are multi-chip packages in every major phone, data center, network and even some of the higher-end smart watches. But this approach will require time and experience before advanced packages are easy to design, cheap enough to use for more than the most advanced electronics, and quick to manufacture with predictable results and high yield.

“Customers want tools, which don’t exist today, and this is not one size fits all,” said Johanna Swan, director of packaging research and fellow at Intel. “It’s typically a mix of many products from many customers. We are striving toward more standard ways of doing things. For example, will it be important to have standard interfaces? But then you run into the question of how standard is standard?”

Consider chiplets, for example. The idea of various-sized chips developed at any process node that can be quickly packaged together using a common interconnect scheme has been talked about for a decade. The concept makes sense from both a business and a technology standpoint, and even today a SerDes or HBM2 stack can be attached to a package in a semi-standard way. Intel has created an entire architecture called Foveros based upon chiplets, connected physically through its Embedded Multi-die Interconnect Bridge (EMIB) as well as an on-chip network, which it acquired when it bought NetSpeed Systems last year. Others are pushing similar approaches.



Fig. 1: Interconnect optimization. Source: Intel

“Chiplets are at an inflection point,” said Calvin Cheung, vice president of engineering at ASE. “The reason for chiplets is compelling. You reduce the die size and also the power. From an OSAT standpoint, we offer a few different platforms for this — 2.5D is one of them. High-density fan-out on wafer-level or panel-level is another. Which one is the right platform to use? That’s not clear. There also are bridges, such as EMIB from Intel. But all of those have important implications for design, reliability and test. And at the end of the day, there is the cost. Those are the open questions for chiplets.”

Different packaging options

One of the biggest problems in packaging is figuring out which type of package will work best for a particular application. AI/machine learning/deep learning, which seems to be almost everywhere these days, is particularly well suited for advanced packaging because it allows a variety of different processing elements and memories to be coupled together using very high-speed interconnects.

The highest-performance packaging approach is 3D-IC, at least in theory. Through-silicon vias (TSVs) can run from one layer to another, greatly speeding movement of data to and from various layers and between processors and memories. The problem is that dynamic power density, static leakage and resistance in wires all generate heat, and in a 3D device thermal management is a serious challenge because some of the chips have no exposed surfaces. That, in turn, limits how fast and how long processors can run without sophisticated cooling. In addition, 3D requires a whole separate design flow, which is not fully in place today because it’s not clear how widespread 3D-ICs will become.

That has made 2.5D more popular, where different dies are connected to an interposer layer packed with TSVs. Xilinx introduced its first 2.5D configuration at 28nm, primarily for yield reasons because yield is higher with smaller die than a single larger die. But since then, 2.5D has emerged as the highest-performance solution available because of the fat-pipe interposer, which uses less power to drive signals with less resistance over shorter distances than what would be required for a single die with standard wirebond connections to DRAM.

“Our first product was chip-to-chip with about 200,000 microbumps,” Xilinx’s Ramalingam said. “We are approaching 1 million these days. But some of the challenges involve the packaging complexity. A silicon interposer is still thought of as a servicing option by foundries. If you want to source the silicon interposer by itself, it is very difficult. And even though it is thought of as a traditional back-end layer, it requires a lot of fab processes.”

That pushes up the cost of the device, because only the foundries are offering those interposers. A similar, less-costly approach involves the use of a bridge interconnect between die. This can happen underneath the chips, which is the approach being pushed by Samsung, or it can happen on top of the die, which is how Intel is approaching the problem.

“The advantage is that you can have whatever node chiplets you want on top,” said Intel’s Swan. “We anticipate we will have mixed nodes that you can optimize with a mix-and-match type of approach. But there are a lot of decisions to make. There are a lot of tradeoffs about what you do nearby versus farther away. We’re also developing directional interconnects, which we call ODI (omni-directional interconnect). That’s the next extension of EMIB. Whatever you put on the base die, if you want a high-speed I/O and DDR on top, but you want a separate die, you can move it from the bottom to the top. That also helps with thermals. ODI is bump-to-bump and it is the shortest channel.”

Chiplets also can be used in a fan-out configuration, with a variety of different connectivity options.

“ASE has been working on panel-level and wafer-level to develop a successful 300mm x 300mm panel for high-density fan-outs,” said ASE’s Cheung. “One of the key features is we can use high-density fan-outs on 2-2μ lines and spaces to replace silicon interposers. There is an embedded layer in the substrate. We talk about power delivery for chiplets. One of the major pushes from design houses is how to deliver with power. With high-density fan-outs, the main question is, ‘What is your yield?’ We have functional silicon in multiple iterations. We have modified the design rules so that yield is very high.”



Fig. 2: Different types of fan-outs. Source: ASE

Technology issues

While the basic technology in today’s packages are well proven, there is much work around the edges to improve power, performance and cost.

Depending on the type of package, alignment can become problematic because the chips can move during the packaging process. This is especially true in fan-outs, where die-shift is an issue. Brewer Science, for example, is developing a “stencil” approach to help limit movement of components during packaging. By creating an outline for components, they are held in place during bonding, which in turn helps to minimize movement that can affect both yield and reliability.

New types of stacking also require different technologies, not all of which are ready today.

“We’ve done lateral die stacking,” said Max Min, director at Samsung Foundry. “But when we start stacking vertically, then memories will need to be coupled differently. That’s becoming important with people trying to go faster, and as we move into chiplets or chiplet-types of approaches and decoupling capacitors for silicon.”

This is evident with DRAM, which is based on a one-transistor, one-capacitor (1T1C) cell structure. The cells are arranged in a rectangular, grid-like array. Voltage is applied to the transistor in the DRAM cell, given a data value, and then placed on a bit-line. This, in turn, charges the storage capacitor, where every data bit is stored.

The capacitor portion is a honeycomb-like device. What gets etched into each cylindrical portion of that honeycomb pattern gets smaller at each new node, and there is less high-k material to store a charge. This is why scaling has slowed on DRAM, and why HBM is becoming a better choice for high-performance applications.

“What’s happening is memory makers are adding more layers, not scaling,” said Ajit Paranjpe, CTO at Veeco. “But when they do that, they are adding more process margin. This is all about exploiting processors, and the industry has really figured out where to leverage different process steps. You see this in DRAM, which used to follow traditional scaling until they got to the 1xnm dimension. After that, they didn’t go 18 to 14 to 7 to 5nm. They went 19 to 18 to 17 to 15 to 14, which is 1x, 1y, 1z, 1a and 1b. They push process margin on process steps. But if you go off-device with HBM, that makes it simpler. It’s another access point for improvement at the system level.”

Materials issues

Alongside of all of this, there is work underway to add new materials into the packaging process.

“Moore’s Law has driven a lot of the innovation, but that was possible because of the innovation in the materials space,” said Ming Li, R&D director at ASM Pacific Technology. “This certainly has motivated interconnect solutions. We try to reduce the pitch. We’ve moved from wirebonding to copper pillar and micro-pillar. Some of the materials we already have for making the packages. So for high-bandwidth memory and processors on the interposer, some of the metallization — copper, RDL, copper pillars, bumping — will be running, and we can apply polymers and patterning, or some of the dielectric materials or thermal materials.”

Li noted that chip-on-wafer is still a traditional reflow process. “The challenging part is the flux cleaning,” she said. “It is multiple compounds on a die, so you have to select the right underfill and the right EMC (epoxy molding compounds) to reduce the warpage. For such a compound die on a substrate, the warpage is very challenging. We need to use thermal compression bonding to get to temperature uniformity and to reduce stress.”

Brewer Science also has begun developing alternatives to removing all materials, which can reduce what needs to be cleaned.

“In the past, most of our materials have been sacrificial,” said Srikanth Kommu, executive director of the semiconductor business at Brewer Science. “Now we’re working with customers to leave certain materials behind. This is selective modification. The line features are so small, that you have to optimize the chemistry of the compounds. So rather than depositing materials, you leave some behind with temperature chemistry. That saves on laborious deep etch for polymeric materials and shifts it away from traditional structure problem solving.”

Business issues

Any standards that do exist today are de facto, based upon processes and architectures developed by TSMC, Samsung, Intel and some of the OSATs. But even if industry-wide standards do become prevalent, ensuring reliability with chips in a packaging is much more time-consuming than with a planar chip. There is more to inspect and test, and many of the structures are in 3D.

“When you’re doing advanced packaging inspection for system-in-package and different types of 3D stacking, testing at the die level is quite important,” said Tim Skunes, vice president of R&D at CyberOptics. “All it takes is for one solder connection to fail or one bad silicon interposer and the entire package is wrecked. So now you have to figure out when to inspect and when not to inspect, and you need a return-on-investment analysis of assembly yields. That means you need to do 100% of the inspection in 3D for things like ball height planarity. And you have to adapt this to different applications, so that impacts speed and ultimately cost.”

Skunes noted that current systems measure lateral feature sizes, but with vertical stacking the challenge is how to inspect and test on the Z axis. He said that capability is expected to begin rolling out at the end of this year.

Packaging appears to be further along from a technology standpoint than from a supply chain standpoint. While EDA tools still have to be fine tuned for various flavors of packaging, much of the process and the technology has been in use for at least the past several years. Much of this is the result of searching for new options on planar chips.

“Moore’s Law has driven innovation in other areas of the supply chain,” said Rozalia Beica, global director of strategic marketing at DuPont. “We’ve seen development in organic and panel processing from the substrate side, micro-vias and high-density interconnects. And because of the gap between the pitch on the substrate and the pin side, there are several packaging technologies that have been developed to bridge that gap. Today we have different flavors of packaging platforms. And because advanced packaging and heterogeneous integration is bringing more value, different business models and companies are entering into this space.”

But processes and flows still need to mature before cost and development time can be reduced sufficiently for many applications.

“For packaging in general, there is a lot of pressure from a cost perspective,” Beica said. “Different technology has been available for more than 10 years, and in some cases much longer than that. But it could not be adopted in mobile because of the high price. Hopefully now, with more end applications and the adoption of through-silicon vias, we will get closer to economies of scale and be able to apply it to applications that are cost-sensitive.”

This is largely a chicken-and-egg problem.

“The key question is, ‘With new technologies and the necessary high investment in resources and time, where you require early engagement, are they they’re willing to pay more?’ From an OSAT standpoint, you need to invest in resources and equipment and many other things,” said ASE’s Cheung. “How do we do that? Do we lower the price right at the get-go so the market adoption comes faster? That’s something we have been wrestling with.”

Conclusion

A lot of experimentation is happening with advanced packaging. The concept has been proven in volume production, but there is much more that can be done with this technology. For example, Intel is experimenting with using TSVs for delivering power, and other companies have been looking at TSVs for electrostatic discharge and heat removal.

How much of this is viable isn’t known at this point, but it’s clear that existing progress in packaging will continue, utilizing whatever it can from advancements in planar chip technology.

“CMOS will go for a long time,” said Gary Dickerson, president and CEO of Applied Materials, during a recent panel discussion. “But package and structures will change.”

How much they will change remains to be seen. But the general assessment is that packaging is just beginning to take hold, and it will become much more prevalent at all nodes as new applications demand it and as more devices are developed with advanced packaging architectures.

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