Cern reveals AMD 32-core Zen CPU with 8 channel DDR4 memory

Cern reveals AMD 32-core Zen CPU with 8 channel DDR4 memory

| Source: Cern Author: Mark Campbell

Cern reveals AMD 32-core Zen CPU with 8 channel DDR4 memory

Internal Cern slides have revealed an upcoming 32-core Zen based CPU from AMD, a new CPU design which will have 8 channel DDR4 memory support and PCIe gen 3.0 connectivity.

Like all other AMD Zen based CPUs this CPU will be designed and manufactured using the 14nm FinFET manufacturing process and will feature a 40% increase in Instructions Per Clock (IPC) when compared to current AMD offerings.

This 32 core CPU will have 32 physical CPU cores with SMT, meaning that this CPU will have a total of 64 threads, making this a very powerful CPU design.

According to the code of a recently leaked Linux Kernel patch AMD is working on a new 32 core CPU using it's Zen Architecture, matching previous rumors that stated that AMD would be creating ultra high performance CPUs and APUs for high performance compute applications.

Zen has been created from the beginning to have a modular design, allowing AMD to easily use their parts to create semi-custom CPU and APU designs using a group of standard components. This will allow AMD to more easily create custom designs like those in the PS4 and Xbox One as well as to be able to better suit the requirements of their hardware partners.

Zen CPUs can be made up of Zen Quad core units, meaning that AMD can combine these units, or modules, into larger and larger CPUs using a special AMD designed interconnect, allowing AMD to scale this design up to 8 core, or in this case 32 core parts.

AMD's Zen architecture will feature SMT, so for every 4 cores there will be 8 total threads, meaning that this 32 core CPU will have a total of 64 threads, which is simply insane from a consumer standpoint.

AMD Zeppelin (Family 17h, Model 00h) introduces an instructions retired performance counter which indicated by CPUID.8000_0008H:EBX[1]. And dedicated Instructions Retired register (MSR 0xC000_000E9) increments on once for every instruction retired. Signed-off-by: Huang Rui <[email protected]>

—

arch/x86/include/asm/cpufeature.h | 1 +

arch/x86/include/asm/msr-index.h | 3 +++

arch/x86/kernel/cpu/perf_event_msr.c | 30 +++++++++++++++++++———–

3 files changed, 23 insertions(+), 11 deletions(-) + core_complex_id = (apicid & ((1 << c->x86_coreid_bits) – 1)) >> 3;

+ per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;

AMD's new Zen architecture is designed to be a significant leap in terms of both performance and efficiency, hopefully making AMD's CPU lineup competitive with Intel both in the consumer, datacenter and high performance computing markets.

Right now AMD say that their new Zen architecture will have a 40% increase in IPC compared to AMD's current Excavator CPU designs, making it a historical leap in performance for AMD.

You can join the discussion on AMD's upcoming 32 core Zen CPU design on the OC3D Forums.

Cern has revealed an upcoming AMD 32-core Zen based CPU with 8 channel DDR4 memory supporthttps://t.co/krTMrzSBdY pic.twitter.com/SATV7e4d5j — OC3D (@OC3D) February 13, 2016

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