Overview

Only designers who make no mistakes can avoid debugging. The question is, how fast can you debug? That depends largely on how clearly the issues identified by your tools are presented. A good debugging environment can save hours of frustration and tedium.

To quickly find pre-simulation and synthesis problems in chip designs, designer use RTL lint. However, traditional RTL analysis tool or linters are difficult to use because of these issues:

Features

Links from log files messages to RTL code and schematic

Search for any object (pin, port, net, instance) in the design hierarchy

Ability to filter messages to group and prioritize messages

Full or pruned schematic to visualize the design problem

Fast schematic trace forward or backward in the design from any net or pin to find driving gate or Flip-flop to understand the context of the problem.