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The global economy is currently a sea of gloom. Several financial institutions have forecast that 2020 will see the worst economic performance in the global financial crisis 10 years ago.

To TSMC’s 40,000-plus workforce, however, the future could not be brighter, much like the sunny weather that shined on the company’s Sports Day in Hsinchu on Nov. 2.

“Next year will be a year of huge growth,” TSMC Chairman Mark Liu declared confidently on the occasion. The next day, the comment made the front pages of many major media, and foreign brokerages revised their earnings forecasts for TSMC upwards.

Source: TSMC

Three days later, for example, research and brokerage firm Sanford Bernstein raised its target price for TSMC from NT$285 to NT$330, and it forecast EPS growth of 20 percent in both 2020 and 2021, far higher than the single-digit growth since in recent years. Weekly financial publication Barron’s led with a headline on Oct. 18 reading “TSMC Topples Intel for the Chip Crown” and stress that TSMC is firing on all cylinders, which is bad news for former chip leader Intel.

Why is that TSMC is hitting the accelerator at a time of general economic sluggishness, with plans to increase investment by 40 percent a year the next two years that could create growth at double or triple the rate seen in the recent past? What is it that TSMC’s management has seen and that has analysts so upbeat?

CommonWealth Magazine interviewed several industry insiders and outside analysts to find out and grouped their responses into five main keys to TSMC’s success.

Key to Success No. 1: Leading the Way in Technology Breakthroughs

The first key is the most direct, and one highlighted by Mark Liu in his message to shareholders in TSMC’s annual report – in 2018 the company “ramped our 7-nanometer technology to high volume successfully, at least a full year ahead of any other semiconductor player.”

In June 2019, it became the first chipmaker to successfully commercialize use of extreme ultraviolet lithography (EUV) in high volume production, applying it 2nd-generation 7nm technology (which it calls N7+).

The achievement was highly significant because it marked the first time in history that TSMC led the rest of the field at a pivotal point in an important technology’s development.

At the last critical juncture for a key technology – the introduction of 3D transistors (which TSMC and Samsung call FinFET and Intel calls Tri-gate), TSMC was four years behind Intel and half a year behind Samsung. For EUV, however, TSMC has a two-year lead over Intel, which is not expected to make use of the technology until 2021.

Many history-changing developments have emerged because of small details originally seen as insignificant. In this case, TSMC was able to shake off Samsung and TSMC largely because of tiny specs of “dust” imperceptible to the human eye.

The EUV process has long been considered as the “savior” of the semiconductor industry, which had seen the industry’s longtime driver of progress – Moore’s Law – running out of steam.



TSMC has exceeded sales expectations, and its future seems bright. When retired founder Morris Chang returned for the company’s Sports Day on Nov. 2, he received an enthusiastic welcome. (Photo by Chien-Ying Chiu/CW)

Chipmaking revolves around lithography – projecting light through a blueprint of a pattern to be printed. The pattern is known as a “mask.”

The semiconductor industry’s mainstream production process at present relies on argon fluoride lasers with 193-nanometer wavelengths to create those patterns, but the technique has been pushed to its limits as transistors have shrunk in size to tens of nanometers. Using the laser for small nanometer specifications has been like trying to write small characters on the head of a fly with a coarse paint brush, which is why most industry observers were predicting an end to Moore’s Law – the belief that computing speeds can double every two years.

The EUV process uses a much shorter 13.5nm wavelength, closing in on the length of an X-ray. The problem with EUV light, however, is that it is absorbed by everything, including air, which is why EUV systems have large high-vacuum chambers, according to the world’s only EUV system manufacturer, Netherlands-based ASML. Because of this new technology, the semiconductor industry is moving toward the era of the picometer (1/1,000th of a nanometer age).

Because most materials tend to absorb EUV light, only ultra-reflective mirrors can be used to guide EUV light to its target, but the requirements are such that German optics manufacturer Carl Zeiss has to make the mirrors to an unprecedented level of perfection. Flaws now can be no bigger than a picometer, akin to a mirror of a surface area the size of Germany having a maximum protrusion of no more than a centimeter.

Confronting Nanometer Dust

The requirements for the cleanliness of an EUV production environment are also more stringent than ever.

For example, TSMC’s “mask blank” – a 6-inch bright square mirror that costs millions of Taiwan dollars – has more than 80 layers above it that form the multilayer reflector. Even just a few nanometer-sized specks of dust getting into those layers can have a major adverse effect on the yield rate of the chips.

Anthony Yen, who heads ASML’s Technology Development Center, says the company has already reduced the intrusion from about 100 specks when the EUV project began to single digits today. ASML also does not allow dust floating down from its polishing machine. Its technical spec, according to Yen, is that only one speck of dust is allowed per 10,000 wafers polished, and he says, “we are getting very close.”

Source: TSMC

Because of the difficulties of controlling dust, a key technology in high-volume EUV production is a transparent membrane no thicker than 50 nanometers, or 1/1,000th the thickness of a hair, called a “pellicle.” This transparent membrane protects the bright surface of the masks by keeping tiny specks of dust away. One errant speck on a photomask can result in an entire batch of wafers being defective.

At TSMC’s investor conference in October, one analyst asked whether TSMC had the infrastructure in place to make full use of its EUV tools. TSMC CEO C.C. Wei answered, “All the infrastructure, actually TSMC, we are prepared,” and stressed, “We produce our own pellicle.”

This protective cover is extremely hard to produce because it challenges physical extremes. They have to be thin enough to remain transparent but strong enough to resist the intense heat of EUV radiation blasts, which can reach hundreds of degrees.

“If there’s the slightest vibration, the pellicle can split,” says an executive with a supplier in the industry.

Once a pellicle breaks, the tiny debris that breaks off can contaminate the production machine, requiring a seven-day cleanup and a week-long shutdown of the production line. The TSMC supplier says Samsung and Intel have both struggled with their pellicles, impairing the efficiency of their EUV processes.

So how has TSMC overcome the challenge?

The supplier source says TSMC has taken a different approach. It discovered by surprise that by using a special dust-prevention design for the mask package, it could achieve a certain yield rate without the need for a pellicle.

“That’s possible,” ASML’s Yen says. Though he is not aware of the details of TSMC’s latest technological breakthrough, he asserts that TSMC has long researched “solutions that do not require pellicles.”

Having achieved the breakthrough, TSMC has begun accelerating high-volume EUV production.

This EUV lithography machine holds one of the keys to TSMC’s future. Mastering this technology will determine the winner in the latest round of competition in the semiconductor industry. (Source: ASML)

EUV lithography machines can cost more than US$100 million, making it the most expensive “machine tool” in human history. TSMC and ASML have not revealed how many of the machines TSMC has bought, but Taiwan import statistics may provide a clue.

Taiwan’s imports of machines of the manufacture of semiconductor devices from the Netherlands has surged this year to US$3.39 billion in the first 10 months of 2019, equal to total imports in all of 2017 and 2018 combined.

Key to Success No. 2: Investing Heavily in EUV to Leave Opponents Behind

Among the many nuggets of wisdom uttered by TSMC founder Morris Chang during his long reign atop the company before retiring in 2018, was a classic pearl in 2009.

The world economy had just been hit by the global financial crisis and was still at rock bottom. Chang was once again TSMC’s CEO after having tried to step down to start the succession process, and highly upbeat on future smartphone demand he immediately doubled capital expenditure for 2010 to US$5.9 billion, focused mostly on the 28nm process, the most advanced wafer process at the time.

Though the bold investment strategy shocked the industry, it set the stage for TSMC’s rapid growth in the following years.

TSMC originally anticipated capex to be US$10 billion to US$11 billion in 2019 but it announced at the October investor conference that it was increasing that to a record US$14 billion to US$15 billion despite the semi-downturn in the industry in the past year.

Analyst Sebastian Hou of CL Securities Taiwan wondered if the sudden boost in capital expenditure was similar to the huge step-up in capex in 2010 at another point when business was down but set the stage for a “golden era” for TSMC. It was a bit of a softball question for C.C. Wei.

A 12-inch GIGAFAB at TSMC (Source: TSMC)

Yet he did anything but hit it out of the park. Instead, Wei went into “deep reflection” mode.

“I know what you ask, but let me say that TSMC is getting smarter,” Wei answered. “We decided to increase the capacity at this time with a lot of detailed analysis. And I certainly have confidence that we won’t repeat the same kind of error that we did.”

In fact, Wei misunderstood Hou’s question for a specific reason.

“There were actually different opinions internally at TSMC over this expansion of capacity,” says an analyst at a foreign brokerage. The 28nm process is the most successful process in the company’s history, but it has now become TSMC’s biggest burden because overcapacity industry-wide has led to cutthroat pricing competition. TSMC’s gross margin was on the low side in the first half of the year because the utilization of 28nm capacity was “very low,” according to Wei.

TSMC’s planning department initially opposed the huge capex increase because it was worried of a repeat of the 28nm experience of “early prosperity, later decline,” and its resistance was “made known all the way to the top,” the analyst says.

Ultimately, however, Liu and Wei decided to “hit the gas.”

Another reason for the move was that competitors are unable to catch up because “7nm and 5nm with EUV, that technology barrier is much, much, much higher than you can expect from the [28nm process] high-K metal gate,” Wei said.

Planting Fertile Seeds with Long-term R&D

Earlier in the decade, EUV was actually a technology supported by Intel. In 2012, ASML’s R&D schedule hit a delay, and TSMC, Intel and Samsung all put up the equivalent of NT$10.2 billion to keep the initiative going.

Everybody invested time and money, so why was TSMC so especially confident in the technology?

The answer: because it invested the most in high-volume production using this dream technology.

TSMC is investing more than NT$1 trillion in its Fab 18 in the Southern Taiwan Science Park. It is the company’s biggest project ever and will become its main driver of growth by producing the advanced 5 nm process. (Photo by Chien-Tong Wang/CW)

ASML’s Yen was a part of that history. Before joining ASML, he led the development of EUV lithography, including its mask technology, at TSMC from 2006 to 2017.

In the late 1990s, he and his boss at the time, Burn Lin, went to the United States to see how far EUV technology had progressed.

“Back then, TSMC was not very big, but its R&D was already looking far into the future,” Yen recalls.

He then sent a researcher to Belgium to work with semiconductor R&D hub IMEC in Belgium on a project in partnership with ASML. Initially, the project’s prospects were relatively gloomy. The test machine was down most of the time, and only 20 wafers were sent back over two years.

“But the lines etched were really nice,” Yen recalls. So after the senior researcher, Chiang Shang-yi, an executive vice president overseeing R&D, returned to Taiwan, he approved the purchase of an EUV machine to conduct further research.

To ramp up EUV to mass production required innumerable challenges to be overcome. The thorniest among them was generating a sufficiently powerful and stable light source. The current method seems like a high-energy physics experiment. Operating in a vacuum environment, a high-powered laser fires bacteria-sized droplets of molten tin. They are then turned into a mist and become super-hot balls of plasma that emit EUV light.

Sending that light through the reflector process wastes a huge amount of energy, leaving an extremely low amount of power for the actual lithography process. For many years, the output power never rose above 40 watts, well off the 250W target needed for mass production. The results were so disappointing that many industry insiders were skeptical that EUV could ever be used for high-volume wafer production.

One night in September 2014 was a watershed moment in the technology’s development. Yen recalls that night as though it was yesterday. He was working overtime at TSMC’s Hsinchu plant doing tests with ASML engineers when they succeeded in getting a power output of 90W.

“That was the most exciting night of my life,” Yen remembers.

He reported the result at the EUVL Symposium in Washington D.C. a month later, drawing a collective gasp from the audience. To confirm the result’s stability, TSMC’s senior vice president for research & development Lo Wei-jen requested the production of 500 wafers a day using the EUV process for one month.

When that experiment succeeded, Yen felt relieved, and he was convinced that high-volume EUV production was closer than ever.

Why wasn’t it Intel or Samsung that scored the breakthrough?

One veteran industry insider argues that it may be because Samsung and Intel primarily make chips for their own production. That may especially be true of Intel, which has a gross margin of 70 percent on its CPUs (central processing unit) and can afford a somewhat slower rollout of products.

As a result, “Intel’s attitude [toward EUV] is more conservative.”

But TSMC, which only produces chips on a contracting basis for outside customers, does not have that luxury. It has therefore dedicated itself to supporting ASML’s research, striving for a high-volume production rate of 125 wafers per hour and the 250W of output power needed to achieve that.

“If we stayed put at 40W, [TSMC] would not have had a future. We kept pushing the envelope,” Yen says.

Several ASML breakthroughs on EUV technology originate from the United States or the Netherlands and then brought to TSMC’s No. 12 R&D factory in the Hsinchu Science Park to complete preliminary high-volume production tests.

Next➣

TSMC Leaving Samsung Behind with High Yield Rate

In the final part of this two-part series, we will look at the three other factors that have helped TSMC remain a step above Samsung and Intel.

More on TSMC➣

♦ Decoding U.S. Export Controls: Can TSMC Continue to Supply Huawei?

♦ Snatching Apple Orders: TSMC’s Unsung Weapon

♦ China's Big Money ≠ A Second TSMC

Insight from Morris Chang➣

♦ Unstable World Makes TSMC Vitally Important in Geostrategic Terms

♦ Ready for a Clean Break with TSMC

♦ Who Do Corporations Fight for?

Translated by Luke Sabatier

Edited by Sharon Tseng