Novel nanotube tunnel FET architecture

(Nanowerk Spotlight) Classical semiconductor physics suggests that a single charge transport CMOS (complementary metal-oxidesemiconductor) device cannot achieve ultra-high-performance and ultra-low-standby-power at the same time. Nanoelectronics researchers are trying to design devices that hit the 'sweet spot', i.e. where a charge transport device can provide its highest performance at its lowest power consumption, especially in its 'off' state.

Now, in new work, researchers from the Integrated Nanotechnology Lab at King Abdullah University of Science and Technology (KAUST) show a unique device concept which combines the advantages of a tunnel field-effect transistor (TFET) for ultra-low OFF (leakage) current and ultra-steep sub-threshold slope for sharper and faster ON and OFF switching due to the FET's nanotube architecture.

In addition, this nanotube device, which is built on heterogeneous material systems, shows scalability and area efficiency in an unprecedented way. According to the scientists, this is the highest comprehensive functionality achieved ever in single device.

"We capitalized on an innovative design of nanotube architecture with a core (inner) gate and a shell (outer) gate," Muhammad Mustafa Hussain, an Associate Professor of Electrical Engineering at KAUST, tells Nanowerk. "This way we were able to achieve utmost electrostatic control for ultra-low-standby-power operation."

The team reports their findings in the April 29, 2015 online edition of Scientific Reports ("InAs/Si Hetero-Junction Nanotube Tunnel Transistors").

Schematic of the nanotube architecture. (© Scientific Reports)

"We believe that our nanotube device can be built using conventional channel materials such as silicon, silicon germanium, germanium, III-V materials," says Hussain. "Nanotube thickness is controlled down to below 15 nm to achieve full volume inversion. Deposition control gate length can allow achieving in ultra-short channel devices. Epitaxial growth can enable ultra-steep junctions for source/channel/drain."

Based on the significant improvements achieved with the new design, the device can also achieve ultra-high-performance.

"By using semi-classical transport simulation we evaluated how different device architectures affect transport behavior," notes Hussain. "We have found that nanotube architecture FET outperforms gate-all-around nanowire architecture FET due to lateral tunneling – the dominant band-to-band tunneling mechanism for the devices is highly dependent on the junction cross-sectional area. And since the nanotube has a high available cross-sectional when compared to that of the gate-all-around nanowire devices, it has sown higher normalized ON current."

As part of their investigations, the KAUST team also found that the Shockley-Reed-Hall (SRH) recombination in the nanotube devices was lower than that of the gate-all-around nanowire devices due to the higher carrier density within the source (InAs).

"This has been the first attempt to evaluate hetero-structure material system with the nanotube architecture for a TFET application," Hussain points out. "The main motivation was that TFET suffer from low I ON problem which limits their potential for logic applications. Therefore, we have presented an architecture which mitigates this issue, and allows circuit design by controlling the ON current as a function of the core gate diameter in the nanotube TFET."

The device can be used for area efficient ultra-high-performance and ultra-low-standby power logic applications. In addition, the device can be used for ultra-compact non-volatile memory applications.