Brain emulation requires enormous computing power; enormous computing power requires further progression of Moore’s law ; further Moore’s law relies on large-scale production of cheap processors in ever more-advanced chip fabs ; cutting-edge chip fabs are both expensive and vulnerable to state actors (but not non-state actors such as terrorists ). Therefore: the advent of brain emulation can be delayed by global regulation of chip fabs.

Here I will defend the following chain of claims:

Why might one be interested in this topic? Chip fab risks and costs may turn out to be a major limiting factor on Moore’s law, and a factor that has gone almost entirely unrecognized (eg. who has ever heard of “Moore’s Second Law” governing chip fabs?). The progress of Moore’s law is of major importance to any future forecasts of economic growth, progress of both research & application of artificial intelligence & machine learning (“big data” vs clever algorithms), sociological developments, and all forecasts of a technological Singularity. Anyone interested in a better understanding of the topics, more accurate forecasts, or perhaps even affecting events directly. The fragility of chip fabs is of independent interest as it is not generally appreciated, and has potentially global consequences—for example, a conflict between China & Taiwan (which is home to many cutting-edge chip fabs) would, at the least, interrupt semiconductor chip deliveries to the rest of the world, a contingency which may not have been adequately prepared for.

Why might we want to affect the natural development of either approach? WBEs are frequently regarded as being potentially highly untrustworthy and dangerous, constituting an existential risk .

WBE is generally believed to be relatively straightforward engineering, but is expected to take 10 18 FLOPS (supercomputer estimate: by 2019) to 10 43 FLOPS (supercomputer: by 2111) to do in comparison with the latter which either takes a similar amount (if it is as inefficient as emulated brains and winds up effectively being a synthetic upload) or potentially much less if there are efficient algorithms and optimizations unavailable to evolution through brains or unavailable period with brains. Hence, we expect that uploads will be made more likely by powerful hardware and de novo AGI be made more likely by powerful software/algorithms/mathematical insight. This observation immediately suggests that any slowing in hardware developed will reduce the probability of uploads coming before de novo AGI (whatever that probability is), and vice versa, any slowing in software/math will reduce the probability of de novo AGI coming before uploads (whatever that probability was). A slowing in both may not change the probabilities or relative dates of them, but rather postpone the appearance of either or both.

On the other hand, at no point in those 60 years has anyone seriously attempted to slow down Moore’s law, and any attempt to do so will have been through ordinary commercial methods, which are highly limited in what coercion can be applied. In particular, that 60 year period has been historically unusually favorable for technological development, with no major wars in the relevant nations like Japan, Taiwan, or America (historically unusual—and a war involving China was, and still is, perfectly plausible). Had Moore’s law survived a multilateral thermonuclear exchange, that would be evidence for robustness. Had Moore’s law survived legal assault like peer-to-peer filesharing has, that would be evidence for robustness. But in fact, Moore’s law has been heavily favored by government subsidies to research as American computer & semiconductor capabilities were seen as a major advantage over the Soviet Union during the Cold War; and they have continued, as with the end of the Cold War, computers also became a key part of the American economy and self-image. (‘We may not have manufacturing’, the elites say, ‘but we’re still the best Internet and computer economy in the world! Just learn you some computer stuff and there is a good job waiting in Economy 2.0 for you!’ There is enough truth to this.) Where there is sufficient political will, even the most dramatic and accessible technology can decline—witness the end of Ming China’s extraordinary sea expeditions led by Zheng He or Tokugawa-era Japan’s suppression of firearms . Throughout history, there have been long periods of technological stagnation or even regression: to draw a straight or exponential line from a few points using overlapping chronologies is just cherry-picking.

How feasible is this? The relevant measure of progress, Moore’s law, has operated reliably since the 1950s, over more than 60 years, and has even sped up at times. This would suggest it is difficult to slow down or reverse this particular kind of technological progress.

Of course, from the utilitarian perspective, such a move would have enormous consequences inasmuch as it would probably constitute a price floor on processing power, disadvantaging low-power applications like embedded processors or supplies to the developing world; and many business arrangements are founded directly or indirectly on Moore’s law holding for another decade or three. Poverty kills, and any delay in economic growth also kills. Since we cannot observe the consequences of either de novo AGI or brain emulations before they are created , and once one is created we will cease to care about their timings (from an existential risk point of view), we must resort to arguments about what might affect their relative appearances; even in math, arguments or proofs come with non-trivial error rates —so how much more so in a legal or economic argument? To not be banal , we would need to make a very solid case indeed—a case I cannot make nor will make here. Let’s assume that the case has been made and examine an easier question, how feasible such strategies are at accomplishing the goal at all.

If an organization (such as a singleton world government like the UN Security Council) wanted to shift probability towards de novo AGI (the desirability of uploads is contentious, with pro and con ), then they might withhold subsidies from hardware research & development, regulate it, or even actively oppose it with penalties ranging from the financial to the civil to the military. (Or perhaps neo-Luddites wish to delay computer progress in the interests of economic justice.) This has been informally proposed before; for example, Berglas 2009–2012 .

While the Internet is famously distributed and does not at first glance follow any bow tie network, the semiconductor industry is amazingly centralized: <14 companies make up the majority of global manufacturing. Much of the industry (like AMD or ARM ) does not actually possess manufacturing facilities; they focus on research, design, and licensing. The facilities require myriads of skills, resources, and tools, and also as in a bow tie, the outputs of these few facilities are shipped world-wide to be used in countless applications in every field of endeavour. The chip fabs look very much like the knot of a bow tie and where we might want to start.

…a myriad of nutrient sources are catabolized, or ‘fan in’, to produce a handful of activated carriers (e.g. ATP, NADH and NADPH) and 12 precursor metabolites (e.g. glucose 6-phosphate, fructose 6-phosphate, phosphoenolpyruvate and pyruvate), which are then synthesized into roughly 70 larger building blocks (e.g. amino acids, nucleotides, fatty acids and sugars). The precursors and carriers can be thought of as two ‘knots’ of separate bow ties that are both fed by catabolism, but whereas the former ‘fan out’ locally to the biosynthesis of universal building blocks, the latter fan out to the whole cell to provide energy, reducing power and small moieties.

When examing a system to speed it up or slow it down, one wants as much leverage as possible, to manipulate central nodes. In a highly distributed network, manipulation may be difficult to impossible as no node is especially important: the system can only be manipulated by manipulating a large fraction of the nodes. But many networks are not very distributed, and may looks more like a butterfly or follow the bow tie organizational architecture seen in cellular metabolism:

The costs they bear to build each chip fabrication plant is astounding, and increasing even as revenue growth slows (squeezing out many old companies) ; the basic equipment alone begin in the hundreds of thousands of dollars, lithography machines were $40 million a piece in 2009, and the most expensive single pieces of equipment (like steppers) can reach prices as high as $50 million dollars. The software licensing and engineering costs that go into a cutting-edge processor are equally staggering; Brown & Linden 2005 (see also Andreas Olofsson):

Cost reduction via offshore investments in low-wage countries was not a feasible strategy because fabrication is so capital-intensive that labor typically accounts for 16% of costs (including depreciation) in U.S. fabs producing 200mm wafers, and less than 10% in the newer 300mm fabs, which undercuts the major labor cost advantage of most industrializing countries.30…The economic characteristics of each step of the process differ significantly. Design is skill intensive, and requires expensive EDA (electronic design automation) software, which is typically licensed per design engineer. Fabrication requires a huge fixed investment (currently on the order of $2 billion [c. 2004]) to build a plant (called a fab) that holds a wide variety of expensive equipment and that meets extreme requirements of cleanliness. Assembly also requires expensive equipment, but the overall costs of plant and equipment are much lower than for the fab, as are the average skill requirements. Overall, worker skill requirements go down along the value chain (i.e., design is more skill-intensive than manufacturing, which is more skill-intensive than assembly)…The availability of outsourcing (foreign or domestic) is particularly important for small companies and start-ups because of the relatively large fixed cost of EDA tools, which are typically licensed per engineer. One consultant estimated that the minimum annual software expense for a small company is $10 million.85 For the industry as a whole, EDA expense runs close to 1% of revenue. In that case, a company earning less than $1 billion in revenue would be below the efficient scale for in-house design. Only the nine largest fabless companies met that criterion in 2004. One consultant estimated that outsourcing even within the United States would save a small start-up that does fewer than five designs a year up to two-thirds the cost of doing the work in-house.86 …Chip design is highly skill-intensive, since it employs only college-trained engineers. A couple of medium-size chip designs will employ as many electrical engineers as a fab for a year or more (although the skills are not directly transferable). A complex chip design like Intel’s Pentium 4, with 42 million transistors on a 180nm linewidth process, engaged hundreds of engineers for the full length of the five-year project.[“Comms held Pentium 4 team together”, EE Times, November 1, 2000. “Linewidth” refers to the size of the features etched on a wafer during the fabrication process. Each semiconductor process generation is named for the smallest feature that can be produced.] …The software effort itself has increased by 375%. According to one software executive, a typical chip in 1995 went into a stand-alone product and required 100,000 lines of code. In 2002, a typical chip for a networked programmable product requires a million lines of code.60 [Jerry Fiddler, chairman of Wind River Systems, cited in “Keynoter says chip value is in its intellectual property,” EE Times, June 14, 2002.] The software, plus the greater complexity of chips themselves, has caused design validation hours to grow by 90% for each million transistors. By comparison, the growth levels for the actual design engineering jobs of logic and physical design for each million transistors are a relatively modest 17% and 52%, respectively. This is largely because, as chips have gotten more complex, the process of chip design has become more automated.61

The facilities are even more impressive: Intel’s Fab 11X has 400,000 square feet of cleanrooms a quarter-mile on a side. Chip fabs use upwards of 40 miles of pipes for their ultrapure water (Klaiber’s law: the pipes expand in diameter each generation) with the internal monorail transportation can be 3 miles long, and the clean rooms must be constructed with custom pre-cleaned construction materials. (Cement consumption is so high that Intel just builds cement plants on their sites.) Chip fab energy consumption is measured in megawatts, 55–65 megawatts in one case. Intel cheerfully notes about its Fab 42 construction:

First of all, Intel is using the largest land-based crane in the world—one that can pick up and place massive roof trusses that weigh approximately 300 tons each. The crane is so large it had to be delivered on trucks to the site in pieces—approximately 250 truck loads in total. Additionally, Fab 42 will require 24,000 tons of steel rebar and 21,000 tons of structural steel. And to make room for the fab, 875,000 cubic yards of dirt had to be excavated. When all is said and done, approximately 10.5 million man hours will be required to complete the project.

A fab cost ~$1.5b in 1998, $2b in 2004, $3b in 2007, and $5b by 2010. Jurvetson wrote in 2004 that

Another problem is the escalating cost of a semiconductor fab plant, which is doubling every three years, a phenomenon dubbed Moore’s Second Law. Human ingenuity keeps shrinking the CMOS transistor, but with increasingly expensive manufacturing facilities—currently $3 billion per fab.

Ross 2003 didn’t foresee the coming explosion in prices in describing Moore’s Second Law, or Rock’s law as he prefers:

Sometimes called Moore’s Second Law, because Moore first spoke of it publicly in the mid-1990s, we are calling it Rock’s Law because Moore himself attributes it to Arthur Rock, an early investor in Intel, who noted that the cost of semiconductor tools doubles every four years. By this logic, chip fabrication plants, or fabs, were supposed to cost $5 billion each by the late 1990s and $10 billion by now. Not so. VLSI Research estimates that fabs cost $2 billion apiece, the same as in the late 1990s, even as their productivity has gone up. “In the 1980s, the fabs increased their yield; in the 1990s, they started [increasing] their throughput,” Hutcheson says. (Throughput refers to the number of wafers a fab produces in a given time.) Wafer throughput rose from 20 per hour in the early 1990s to about 40 to 50 an hour today. Anyhow, the focus was wrongheaded; what matters is not the cost of the fab but the value of its product. If a $100 billion fab made so many transistors per penny that it could undercut the prices of a $10 billion competitor, it would be economical (if, of course, you could get the seed capital together from a coalition of companies-or continents).

Intel’s Fab 32 cost an estimated $3b in 2007 (clean rooms: 184,000 square feet; total: 1 million square feet), revised to $3.5b by 2011. A 2009–2010 upgrade to an Intel fab, Fab 11X, cost $2.5b (on top of the $2b upgrade in 2007). The ‘first stage’ of GlobalFoundries’s New York 1.3 million square foot fab will cost >$4.6 billion dollars ($1b reportedly supplied by New York State); GlobalFoundries CEO Sanjay Jha estimated in 2017 that a 7nm-capable chip fab would cost $10-$12b and the 5nm $14–18b. Intel’s Fab 42 (begun 2011–2012) is projected at >$10b. TSMC’s Fab 15 in Taiwan is estimated at >$9.3 billion, and they are preparing to start a fab in 2015 projected at >$26 billion; a $20b estimate for their next fab was repeated in 2017. Construction of a German chip fab has been blamed for contributing to the financial hobbling of formerly competitive AMD , and involved companies are resorting to collaborations to cover the capital costs, even for the largest players (eg. Intel & Micron building a $3b+ Flash fab together, or Samsung still able to build memory chip fabs with internal financing its memory factories—as a government-backed chaebol representing 1⁄5th of the world’s 15th largest economy). The trend shows little sign of abating for a variety of reasons , and vastly outpaces inflation. At current rates, it is not impossible that the total cost of a bleeding-edge CPU/GPU chip fab may pass the $100b (inflation-adjusted) mark somewhere in the 2020s or 2030s—well before a number of the Bostrom-Sandberg estimates for hardware power reaching brain emulation levels. These billions of dollars of expenditures are developed & managed by hundreds of thousands of employees: TSMC has >38k and Intel >104k.

To put these financial & infrastructure investments in perspective (particularly the projected TSMC investment of >$26b for one new fab), the Manhattan Project—one of the largest, most expensive (after Apollo), and intricate scientific programs ever undertaken, trying multiple pathways to the atomic bomb in parallel—cost $2421945 billion in 1945 or $25–30b in 2012 dollars, with 130k employees.

One can’t help but think that even if possible, no one will engage in such capital expenditures because it will be bad business. (In January 2014, Intel halted development of its Fab 42—“touted as the most advanced high-volume semiconductor-manufacturing facility in the world” and “among the world’s largest construction projects in recent years”—after ~$1b of construction was completed.) A semiconductor consultant shows a 2012 estimate about the cost per gate of the smaller processes (which may require new chip fabs):

Figure 1: Cost per gate 3. Next-generation 20-nm planar CMOS will have a range of additional tolerance control challenges compared to 28-nm. One likely impact is that cost per gate at 20-nm will be higher than at 28-nm. With the potential for increased cost per gate, additional compaction will need to be done, which will lengthen design completion times. Cost per gate at 14-nm can also be higher than that at 28-nm. …New libraries will need to be developed, IP transitioned to the FinFET structures, test chips run, and production volumes ramped up. At 14-nm, complex chips will cost $200 million to $500 million to design, and re-spins will cost $20 million to $50 million. The cost of failure will increase dramatically. What’s more, 14-nm FinFETs are not likely to be in high-volume production outside of Intel until 2016 to 2017. High-volume production will require lower power consumption and lower cost per gate than earlier generations of technologies. After 14-nm, there will be a range of new challenges (EUV, 450-mm, carbon nanotubes, etc). The semiconductor industry must be realistic that the supply challenges are becoming more difficult, and there will be a lengthening of the time to migrate to smaller feature dimensions.

Consistent with squeeze on revenue and escalating capital costs is the observed distribution of manufacturing. “Resource Allocation & Scheduling in Moore’s Law Twilight Zone”, Benini July 2012, pg2; we see 20 manufacturers at the ancient 130nm, but just 5 manufacturers at 22/20nm:

“Market volume wall: only the largest volume products will be manufactured with the most advanced technology”