ANTWERP, Belgium — A 20-year struggle to launch a next-generation lithography tool has entered its final phase as engineers race to unravel a rat’s nest of related issues. Despite complex problems and short deadlines to bring extreme ultraviolet (EUV) steppers into high-volume manufacturing, experts remain upbeat.

The good news is that many shoulders are pushing the wheel ahead. “In the past, one company would take a lead with a new semiconductor technology, but now all the logic guys are jumping in, biting the bullet, and taking the risks,” said An Steegen, executive vice president of technology and systems at Imec.

The research institute in Belgium is a long-standing collaborator with ASML, the developer of EUV in the Netherlands. Together with foundries and suppliers, they now aim to work out the last major kinks in the room-sized systems that will print next-generation chips.

It’s like when the FinFET transistor emerged in 2008 as a significant but challenging vehicle for new performance gains, said Steegen in an interview at the Imec Tech Forum here.

“People compared the worst case of next node to the best case of the old node, but now all sides agree that FinFETs are extremely high-performance devices. My lesson is to take it all with a grain of salt … there are enough features ahead to deliver improvements so that SoC designers get what they want.”

In a separate, informal conversation waiting in line for coffee at Imec’s headquarters, a 32-year veteran working on EUV put it simply: “There are a lot of pressures right now … but we are making progress.”

Indeed, Samsung’s foundry is racing to get EUV into production at 7 nm before the end of the year. It aims to pull ahead of larger rival TSMC, which is taping out many 7-nm chips now using existing immersion steppers.

TSMC and GlobalFoundries are not far behind, aiming to ramp enhanced 7-nm nodes with EUV early next year. Separately, Imec estimates that DRAM makers will adopt EUV for their D14+ nodes — probably in 2021, when half pitches dip below 20 nm.

Two of Imec’s current focus areas are helping to smooth out line-edge roughness and eliminating so-called stochastics, random errors that create missing or kissing contacts. The errors were first reported earlier this year at 15-nm dimensions key for a next-generation 5-nm node, but researchers now say that they also see them at 7 nm.

Steegen expects that hybrid solutions will emerge. They will use a combination of scanner settings, resist materials, and post-processing techniques that stitch broken lines, smooth jagged ones, or fill out missing contacts.

Foundries can apply higher doses of EUV light — say, 80 millijoules/cm2 — to widen a process window, but that will slow throughput. “Deciding the peak dose for the first implementations is up to the foundries,” said Steegen.