Just a few months after standards for PCIe 5.0 were ratified, PCI-SIG has announced the specification for PCIe 6.0, a connection that will double the effective bandwidth from PCIe 5.0 to a maximum of 256 gigabytes per second.

The new standard is described as performing 64 "gigatransfers" per second, twice that of PCIe 5.0, four times that of PCIe 4.0, and eight times the capabilities of the commonly-used PCIe 3.0. The high 256 gigabytes per second of bandwidth also follows a similar multiplier, being eight times better than PCIe 3.0's 32 gigabytes per second.

The same multiplier over earlier versions also applies to the frequency, with PCIe 6.0 functioning at 64GHz. For reference, PCIe 4.0 and PCIe 3.0 operate at 16GHz and 8 GHz respectively.

To enable these higher speeds, PCI-SIG is also implementing PAM4 (Pulse Amplitude Modulation) signaling in PCIe 6.0 rather than the NRZ encoding scheme. Commonly used in networking, it uses low latency Forward Error Correction (FEC) with additional mechanisms to boost bandwidth efficiency.

Backwards compatibility with all previous PCIe generations is also pledged, as well as continuing to have a maximum lane count of 16, keeping it in line with other versions.

While the standard offers considerable bandwidth boosts over the existing PCIe 3.0 and slowly-arriving PCIe 4.0, there will still be quite a wait for it to become usable. Current expectations are for the specification to be published in 2021, with the first devices using it potentially arriving in 2022.

At the moment PCIe 3.0 is the prevalent technology, with PCI 4.0 hardware slowly arriving on the market. The ratification of PCIe 5.0 in January could lead to hardware using the standard arriving later in 2019, effectively outdating PCI 4.0 before it can become widely used.