RISC-V Workshop in Barcelona Proceedings

7-10 May, 2018

Co-hosted By

Co-sponsored By



Keynote sessions at the event included Robert Oshana, vice president of software engineering research and development at NXP, Martin Fink, executive vice president and chief technology officer at Western Digital, and Mateo Valero, director at the Barcelona Supercomputing Center.

Monday, May 7, 2018 – A half-day of tutorials from the working groups of the RISC-V technical committee. The sessions covered topics such as base ISA ratification, BitManip, compliance, debug, formal spec, memory model, opcode space management, privilege spec, security, software toolchain and vector extensions.

A half-day of tutorials from the working groups of the RISC-V technical committee. The sessions covered topics such as base ISA ratification, BitManip, compliance, debug, formal spec, memory model, opcode space management, privilege spec, security, software toolchain and vector extensions. Tuesday and Wednesday, May 8-9, 2018 – Two full days of presentations on RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and more.

Two full days of presentations on RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and more. Thursday, May 10, 2018 – The event will conclude with RISC-V Foundation meetings, restricted to members of the RISC-V Foundation. The day will consist of Technical and Marketing Committee face-to-face meetings to progress the work currently underway within our various Task Groups.

Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event.

For additional photos from the event, please visit: http://www.shingarov.com/riscv/.

Proceedings

Check out the slides and videos from each of the sessions below.

Monday, 7 May, 2018 RISC-V Workshop Tutorial Day

| Video

Time Event Speaker, Affiliation 12:30pm Registration 1:00pm RISC-V ISA & Foundation Overview Rick O’Connor, RISC-V Foundation Slides | Video 1:15pm BASE ISA Andrew Waterman, SiFive Slides | Video 1:50pm Privileged ISA Allen Baum, Esperanto Technologies Slides | Video 2:25pm Memory Model Daniel Lustig, NVIDIA Slides | Video 3:00pm Networking Break 3:20pm Vector ISA Roger Espasa, Esperanto Technologies Slides | Video 3:55pm Debug Specification Gajinder Panesar, UltraSoC Slides | Video 4:30pm Formal Specification Thomas Bourgeat, MIT Slides | Video 5:05pm LLVM for RISCV Alex Bradbury, lowRISC Slides | Video

Tuesday, 8 May, 2018 RISC-V Workshop Day 1

Time Event Speaker, Affiliation 8:00am Registration and Networking Breakfast 8:45am Welcome Address & Foundation Overview Rick O’Connor, RISC-V Foundation Slides | Video 9:00am State of the Union: RISC-V Krste Asanovic, SiFive Slides | Video 9:25am The State of RISC-V Software Palmer Dabbelt, SiFive and Arun Thomas, Draper Laboratory Slides | Video 9:55am Vector ISA Proposal Update Roger Espasa, Esperanto Technologies Slides | Video 10:25am The RISC-V Formal Specification Technical Group: Progress Report Rishiyur Nikhil, Bluespec Slides | Video 10:40am RISC-V Memory Consistency Model Task Group Update Daniel Lustig, NVIDIA Slides | Video 11:55am Networking Break Keynotes 11:20am Software Drives Hardware, lessons learned and future directions Robert Oshana, NXP Slides | Video 11:50pm Unleashing the Power of Data with RISC-V Martin Fink, Western Digital Slides | Video 12:15pm Networking Lunch 1:30pm RISC-V Debugging: Custom ISA Extensions, Multicore, DTM Variants Markus Goehrle, Lauterbach Engineering GmbH Slides | Video 1:45pm GDB for RISC-V: Extending Support for Bare Metal Multi-core Debugging Jeremy Bennett, Embecosm Slides | Video 2:00pm A Common Software Development Environment for Many-core RISC-V based Hardware and Virtual Platforms Gajinder Panesar, UltraSoC and Simon Davidmann, Imperas Slides | Video 2:15pm HiFive Unleashed: World’s First Multi-Core RISC-V Linux Dev Board Yunsup Lee, SiFive Slides | Video 2:30pm HiFive Unleashed Expansion Options and Capabilities Ted Marena, Microsemi Slides | Video 2:45pm Simulating Heterogeneous Multi-node 32-bit and 64-bit RISC-V Systems Running Linux and Zephyr with the Open Source Renode Framework Michael Gielda, Antmicro Slides | Video 3:00pm Networking Break 3:25pm Debian GNU/Linux Port for RISC-V 64-bit Manuel Fernandez Montecelo, Debian Community Slides | Video 3:55pm Fedora on RISC-V Richard Jones, Red Hat and David Abdurachmanov, Independent Slides | Video 4:10pm Smallest RISC-V Device for Next-Generation Edge Computing Seiji Munetoh, IBM Slides | Video 4:25pm Video: The MareNostrum Slides | Video 4:30pm Poster / Demo Previews Slides | Video 6:00pm Networking Reception, Posters Sessions and Demos Slides

Wednesday, 9 May, 2018 RISC-V Workshop Day 2