Figure 1a displays an optical microscopic (OM) image of our p-MoTe 2 /n-MoS 2 channel JFET device fabricated on 285-nm-thick SiO 2 /p-Si wafer. Pt and Au are used as source/drain ohmic electrodes, respectively, for MoTe 2 and MoS 2 channel. As shown in a 3D schematic device view in Fig. 1c, hexagonal 2H-MoS 2 channel overlies on 2H-MoTe 2 when the two channels cross each other. The two semiconducting TMDs are simultaneously and clearly identified by micro Raman spectroscopy as shown in Fig. 1b, for which a central spot of the overlapped region is probed (see the red spot in Fig. 1a). Since the p- and n-channel materials are crossing, four different PN diodes are possibly formed using Pt and Au electrode and such diode behavior was confirmed (see supporting information in Figure S1). In addition, from the same structure, p- and n-type MISFET behavior was also confirmed along with large hysteresis in the transfer curve characteristics (Figure S2a).

Fig. 1 Materials characteristics and device schematic views. a Optical microscopic (OM) image of our JFET device fabricated on 285-nm-thick SiO 2 /p-Si wafer. Red and blue dashed lines outline MoS 2 and MoTe 2 flake area, respectively. Scale bar = 5 μm. b Raman spectra obtained from red dot point of the overlapped region. c 3D schematic view of our MoS 2 and MoTe 2 junction device. Four heterojunction PN diode pairs can basically be formed (supporting information, Fig. S1) d 3D cross sectional views of p-MoTe2 channel (n-MoS2 gate) and n-MoS2 channel (p-MoTe2 gate) JFET devices Full size image

Following the OM for the JFET structure (Figs. 1a and 2a inset), atomic force microscopy (AFM; Fig. 2a, b) and scanning kelvin probe microscopy (SKPM, Fig. 2c) were conducted probing a rectangular region of the same device, which contains four respective surfaces as shown in Fig. 2a: SiO 2 substrate, MoTe 2 , MoS 2 , and overlay MoS 2 on MoTe 2 . According to AFM results (image contrast), the thickness of MoTe 2 and MoS 2 channel appears to be ~16 and 6 nm, respectively. According to SKPM results, the work functions of individual MoTe 2 and MoS 2 are quite the same, to be 4.54 eV, while that of MoS 2 overlay on MoTe 2 is slightly higher to be 4.56 eV. Slightly higher value is probably because MoS 2 on MoTe 2 is exempted from the effects of trap charges on SiO 2 surface47,48 and also because of some electron charge transfer between the two TMDs. Based on SKPM data, we could expect and construct the band diagrams of MoTe 2 /MoS 2 PN junction, MoS 2 n-channel, and MoTe 2 p-channel as seen in Fig. 2d–f, respectively. The PN junction should contain ~0.3 nm vdW gap between MoTe 2 and MoS 2 . Without gate bias, channel has almost no energy barrier but built-in potential energy (qΦ i = 0.02 eV for n-channel). When a reverse bias is applied to the p-type gate of n-channel, the MoS 2 channel should have energy barrier at the p-gated (overlapped) region (Fig. 2e), where the Fermi energy becomes located in the middle of the band gap indicating charge carrier depletion (for OFF state). Similarly, the MoTe 2 channel has the energy barrier at the n-gate region (Fig. 2f) under a reverse bias applied on p-channel. Without drain bias voltage, the band diagram with the barrier must be symmetric; however, it should become asymmetric under drain bias.

Fig. 2 Device band diagram by AFM and SKPM. a 2D and b 3D AFM images of the JFET structure. Scale bar = 1 μm. c SKPM image of the JFET. White dashed box in the inset of a indicates the scanning region for AFM and SKPM (a–c). Energy band diagrams of d MoTe 2 /MoS 2 , e MoS 2 n-channel, and f MoTe 2 p-channel, respectively. V Gn and V Gp means the gate biases, respectively, applied on n- and p-channels Full size image

As expected from the in-plane direction band diagram (Fig. 2e, f), n-channel JFET was experimentally demonstrated in Fig. 3a–f. Figure 3a shows an OM image of another JFET that is different from that of Fig. 1a but has a comparable channel thickness dimension: ~12 and 7 nm, respectively, for MoS 2 and MoTe 2 channels. Output characteristics (drain current–drain voltage; I D –V DS ) of the device in Fig. 3d display three stages for typical transistors: linear (i), pinch-off (ii), and saturation-to-early effect (iii). Those three stages are well explained with schematic JFET cross-sections under, respectively, different V DS in Fig. 3c, while each material component of the device is identified by color in the schematic 3D view of Fig. 3b. Cross-section (i) in Fig. 3c shows a conducting channel under small V DS for linear regime I D . As V DS increases toward more positive voltage, drain side experiences reverse bias with respect to the p-gate and asymmetric channel depletion (crosshatched area) takes place while source side maintains forward bias and channel opening. As V DS increases further, the n-channel reaches to pinch-off state (ii) and even channel length (L) modulation (iii). Such channel length modulation causes shorter length (L′) and elevated current (deviated from saturation; early effect). This channel modulation was quite general in our JFET devices as observed from another JFET (supporting information Figure S3a). Figure 3e shows transfer characteristics (drain current–gate voltage; I D –V GS ), where a good ON/OFF I D ratio of 5 × 104 and SS of ~100 mV/dec were observed. The gate leakage current (I G ) appears to increase with applied gate voltage (V GS ) in Fig. 3e, and it is certainly understandable as forward bias-induced leakage that originates from the PN junction between n-MoS 2 and p-MoTe 2 .

Fig. 3 n-channel of p-MoTe 2 /n-MoS 2 JFET. a OM image of n-channel JFET. Scale bar = 10 μm. b Simple 3D schematic of our n-channel JFET. c 2D cross-section device views according to (i) small, (ii) pinch-off, and (iii) large V DS as sectioned along with the white dashed line in b of our n-channel device. d I D –V DS output characteristics of n-channel JFET. e I D –V GS transfer characteristics of n-channel JFET. f Mobility of our n-channel JFET. Red and orange lines indicate the saturation mobility and black stars indicate the linear mobility at different V GS (0.2, 0.4, 0.6, 0.8 V, respectively) Full size image

The saturation mobility of our JFET is also extracted from the same figure. Threshold voltage and peak saturation mobility appear to be −0.2 V and 500–600 cm2/V·s, respectively, according to Fig. 3e, f. The saturation mobility was driven from the following Eq. (1), which needs the information on carrier concentration, N d , and transconductance, g m , in MoS 2 n-channel. We extract g m plots from transfer curves as a function of V GS in Fig. 3e.

$$g_{\mathrm{m}} = \frac{{dl_{\mathrm{D}}}}{{dV_{{\mathrm{GS}}}}} = \frac{{qN_{\mathrm{d}}\mu tW}}{L}$$ (1)

So the mobility can be calculated as follows,

$$\mu = \frac{{Lg_{\mathrm{m}}}}{{qN_{\mathrm{d}}tW}}$$ (2)

where N d is carrier density as number per cm3; q is an electronic charge; and t, W, and L are the thickness, width, and length of the channel, respectively. Linear mobility can also be extracted out of the output characteristics at different V GS in Fig. 3d, using the following simple Eq. (3) at small V DS .

$$\mu = \frac{{Lg_{\mathrm{d}}}}{{qN_{\mathrm{d}}tW}},\quad \quad \left( {g_{\mathrm{d}} = \frac{{dI_{\mathrm{D}}}}{{dV_{{\mathrm{DS}}}}}} \right)$$ (3)

The maximum linear mobility appears quite comparable to that of saturation regime.

For both estimations of saturation and linear mobilities, N d value would be the most important information. In order to obtain N d value at room temperature, we have actually attempted four-point van der Pauw Hall measurements with Au-contacting 16-nm-thin MoS 2 and Pt-contacting 7-nm-thin MoTe 2 . Figure 4a, b show two OM images of our samples on SiO 2 /p-Si substrate, while each thickness of the samples was measured by AFM scan as shown with the results of Fig. 4c. Although the sample shapes were not ideal symmetric in Fig. 4a, b, MoTe 2 and MoS 2 samples displayed positive and negative slopes, respectively, under magnetic field (H) sweep for relative magnetic resistance [R H (H)–R H (0)] vs. H field plot in Fig. 4d. Those slopes clearly identify or distinguish p- and n-type conduction. According to the slope, hole and electron concentrations (N a and N d ) were calculated to be 2.43 × 1017 and 2.5 × 1016/cm3 at 300 K, respectively. Calculation details are in supporting information section.

Fig. 4 Hall measurement of MoS 2 and MoTe 2 . OM image of a n-MoS 2 and b p-MoTe 2 for four-probe Hall measurement. c Flake thickness profiles of MoS 2 (red) and MoTe 2 (blue) as obtained from AFM scanning, and d R H (H)–R H (0) data under the magnetic field (H) for MoS 2 (top negative slopes) and MoTe 2 (positive slope). Scale bar of a, b = 10 μm Full size image

All of our JFET devices displayed only a little hysteresis unlike MISFET (Figure S2a) because of small density charge traps at the vdW PN junction interface. Mobility plots in Fig. 3f and transfer curves of Figure S2b exhibit a small hysteresis of 0.05–0.1 V whether the device is n- or p-channel JFET (which is actually a single device working with both channels). Figure 5a shows our third JFET with p-channel, and in fact, this JFET has similar channel thickness of ~10 nm, which is comparable to that of n-channel JFET in Fig. 3a. Output curve characteristics in Fig. 5d show the three I D regimes: linear (i), pinch-off (ii), and saturation (iii). At first glance, the p-channel I D output curves are comparable to those of n-channel ones in Fig. 3d; however, it is recognized on detail observation that pinch-off stage appears slower in MoTe 2 p-channel; saturation voltages (V SAT = −1.5 V for V GS = −1 V) of p-channel are larger than those of MoS 2 n-channel (V SAT = ~0.8 V for V GS = 1 V). It is related to the hole carrier density of p-channel, which is an order of magnitude larger than that of n-channel; the charge depletion of p-channel is more difficult under the same V GD (V GS −V DS ) than that of n-channel. Figure 5b, c present schematic 3D and cross-section views of the p-channel JFET. As shown in Fig. 5c, under a positive V GD MoS 2 gate (reverse bias) is more readily depleted than MoTe 2 p-channel, which needs further V DS for reaching to pinch-off. In Fig. 5e, our p-channel JFET shows an order of magnitude lower I D than that of n-channel one, along with inferior SS (200 mV/dec) and ON/OFF I D ratio (5 × 103) to those of n-channel device. Difficult channel depletion or channel closing might be closely related to such inferiorities. According to Fig. 5f, the saturation (13–14 cm2/V·s as the peak mobility) and linear mobilities (4 cm2/V·s) of p-channel JFET appear comparable to the previous reports from p-MoTe 2 MISFETs25 but much inferior to the values from MoS 2 JFET. Impurity scattering due to an order of magnitude higher carrier concentration in the p-channel would be a main reason for the low mobility along with the intrinsic band structure of MoTe 2 .49,50 Besides, we could also suspect the many traps at the MoTe 2 channel/SiO 2 interface as another reason of such low mobility in respect of device geometry.

Fig. 5 p-channel of p-MoTe 2 /n-MoS 2 JFET. a OM image of p-channel JFET. Scale bar = 10 μm. b Simple 3D schematic of our p-channel JFET. c 2D cross-section device views according to (i) small, (ii) pinch-off, and (iii) large V DS as sectioned along with the white dashed line in b of our p-channel device. d I D –V DS output characteristics of p-channel JFET. e I D –V GS transfer characteristics of p-channel JFET. f Mobility of our p-channel JFET. Blue and skyblue lines indicate the saturation mobility and black stars indicate the linear mobility at different V GS (−0.2, −0.4, −0.6, −0.8 V, respectively) Full size image

As our final device, p-WSe 2 /n-MoS 2 JFET was fabricated on purpose to confirm that any p-TMD/n-TMD JFET generally works in principle; p-TMD works as gate for n-TMD channel while n-TMD does as gate for p-TMD channel. Figure 6a, b, respectively, show the OM and schematic 3D view of the JFET, where Au contact was used in common for both p-WSe 2 and n-MoS 2 channel FETs. Figure 6c displays Raman spectra from both flakes as obtained at once by probing the overlaid position (red dot in Fig. 6a). According to output curve characteristics of Fig. 6d, p- and n-channel JFETs operate well again, although the contact resistance between Au and p-WSe 2 appears serious. Owing to such shortcoming in contact resistance, p-WSe 2 JFET shows its inferior I–V characteristics with a few nA of ON state, and the inferior conductance of p-channel WSe 2 results in its insufficient gating for n-MoS 2 JFET. Hence, n-MoS 2 JFET in p-WSe 2 /n-MoS 2 system displays an order of magnitude lower ON state I D than that of p-MoTe 2 /n-MoS 2 JFET case, as seen in the output and transfer characteristics of Fig. 6d, e. However, this demonstration of p-WSe 2 /n-MoS 2 JFET device still supports that any p-TMD/n-TMD JFET generally works in principle using both channels. (Figure S4 shows AFM thickness profile of p-WSe 2 and n-MoS 2 flakes in JFET.)

Fig. 6 p-WSe 2 /n-MoS 2 JFET. a OM image of p-WSe 2 /n-MoS 2 JFET on SiO 2 /p-Si. Scale bar = 10 μm. b 3D schematic cross-sections of p-WSe 2 and n-MoS 2 channel JFET. Au was used as contact metal for both channels. c Raman spectra of WSe 2 and MoS 2 as obtained by probing the red spot in a. d I D –V DS output characteristics of p-WSe 2 and n-MoS 2 channel JFET. e I D –V GS transfer characteristics of p-WSe 2 and n-MoS 2 channel JFET Full size image