Racetrack memory has attracted attention in the last two years because it's a possible replacement for flash and conventional magnetic disks. Racetrack memory devices can potentially have storage densities hundreds of times greater than flash memories, but read/write speed and power consumption remain substantial technological hurdles. The problems arise from the physics of racetrack memory devices, so performance gains must come from an improved scientific understanding of the underlying processes rather than improved device fabrication.

In a nutshell, racetrack memory works by cycling magnetic domains (bits of memory) along ferromagnetic nanowires using a spin polarized current. A transistor in the center of the wire reads and writes data as the bits are moved up and down the nanowirewire. For a full description of the technology, check out Matt Ford's previous coverage.

The key to increasing speed and efficiency in racetrack memory devices is understanding the interaction between spin polarized current and domain wall motion in the nanowires. A team from Texas A&M University recently solved the equations of motion for magnetic domain walls in nanowires under various current conditions. They found that both the efficiency and speed of domain wall motion could be dramatically increased using a series of current pulses rather than DC, AC, or a combination of the two. Most importantly, they show that the optimum pulse conditions can be calculated using basic electrical properties of the nanowire, which are relatively easy to measure.

There is a lot to like here, but one important aspect is the choice of model. Most work on domain wall motion relies on complex numerical codes that tend to hide the underlying physics of the process. This work uses much more basic magnetisation theory so that the physics and implications of the model are transparent and understandable. The conclusions provide clear, testable conditions that can be realized in the lab, and, if the predictions are accurate, demonstrable increases in device speed and efficiency.

Physical Review Letters, 2010. DOI: 10.1103/PhysRevLett.105.217203 (About DOIs).