LLVM Weekly - #249, October 8th 2018

Welcome to the two hundred and forty-ninth issue of LLVM Weekly, a weekly newsletter (published every Monday) covering developments in LLVM, Clang, and related projects. LLVM Weekly is brought to you by Alex Bradbury. Subscribe to future issues at http://llvmweekly.org and pass it on to anyone else you think may be interested. Please send any tips or feedback to asb@asbradbury.org, or @llvmweekly or @asbradbury on Twitter.

News and articles from around the web

Videos are now available from the GNU Tools Cauldron 2018.

The LLVM Dev Meeting 2018 is taking place next week. I hope to see many of you there. I'll be giving a tutorial on LLVM backend development (using RISC-V as an example of course) and running a RISC-V LLVM backend coding lab session.

On the mailing lists

LLVM commits

WebAssembly was promoted from an experimental target. r343746.

-time-passes was implemented for the new pass manager. r343898.

The RISC-V backend gained support for named CSRs (system registers as defined in the spec). r343822.

The X86, AArch64 and ARM backends will no longer attach a debug location to spill/reload instructions on the basis that they have no relation to the original source code. r343895.

GlobalISel gained new combiner helpers for extending loads, which are put to use in an AARch64 pre-legalize combiner. r343564.

Instructions and registers from AArch64 v8.5A Memory Tagging Extension are now recognised by the MC layer.r343570, r343571, r343572.

llvm-mca learned to check if a register move can by eliminated by the underlying physical register file. r343691.

The enableMultipleCopyHints hook was removed, as multiple regalloc hints are always enabled. r343851.

Clang commits

The Clang Windows getting started documentation was updated. r343809.

ASan can now be used with MinGW. r343437.

Other project commits