IBM, working with GlobalFoundries, Samsung, SUNY, and various equipment suppliers, has produced the world's first 7nm chip with functional transistors. While it should be stressed that commercial 7nm chips remain at least two years away, this test chip from IBM and its partners is extremely significant for three reasons: it's a working sub-10nm chip (this is pretty significant in itself); it's the first commercially viable sub-10nm FinFET logic chip that uses silicon-germanium as the channel material; and it appears to be the first commercially viable design produced with extreme ultraviolet (EUV) lithography.

First, the facts and figures. This is a 7nm test chip, built at the IBM/SUNY (State University of New York) Polytechnic 300mm research facility in Albany, NY. The transistors are of the FinFET variety, with one significant difference over commercialised FinFETs: the channel of the transistor is a silicon-germanium (SiGe) alloy, rather than just silicon. To reach such tiny geometries, self-aligned quadruple patterning (SAQR) and EUV lithography is used.

Somewhat extraordinarily, due to incredibly tight stacking (30nm transistor pitch), IBM claims a surface area reduction of "close to 50 percent" over today's 10nm processes. All told, IBM and its partners are targeting "at least a 50 percent power/performance improvement for the next generation of systems"—that is, moving from 10nm down to 7nm. The difference over 14nm, which is the current state of the art for commercially shipping products, will be even more pronounced.

Technologically, SiGe and EUV are both very significant. SiGe has higher electron mobility than pure silicon, which makes it better suited for smaller transistors. The gap between two silicon nuclei is about 0.5nm; as the gate width gets ever smaller (about 7nm in this case), the channel becomes so small that the handful of silicon atoms can't carry enough current. By mixing some germanium into the channel, electron mobility increases, and adequate current can flow. Silicon generally runs into problems at sub-10nm nodes, and we can expect Intel and TSMC to follow a similar path to IBM, GlobalFoundries, and Samsung (aka the Common Platform alliance).

EUV lithography is a more interesting innovation. Basically, as chip features get smaller, you need a narrower beam of light to etch those features accurately, or you need to use multiple patterning (which we won't go into here). The current state of the art for lithography is a 193nm ArF (argon fluoride) laser; that is, the wavelength is 193nm wide. Complex optics and multiple painstaking steps are required to etch 14nm features using a 193nm light source. EUV has a wavelength of just 13.5nm, which will handily take us down into the sub-10nm realm, but so far it has proven very difficult and expensive to deploy commercially (it has been just around the corner for quite a few years now).

I don't think that IBM, GloFo, and Samsung have magically found a way of making EUV commercially viable, but they are probably counting on the wrinkles being ironed out by 2017-2018—7nm's expected arrival date.

While IBM isn't revealing too much at this juncture, we did manage to squeeze a little more information out of Mukesh V. Khare, IBM Research's point person for sub-10nm processes. When asked about whether this 7nm process is actually viable, and not just a one-off chip designed to strike fear into the hearts of Intel and TSMC, Khare told us:

The IBM Research alliance's work focuses on technology that can be used towards IBM’s and our partners’ product needs. The 7nm node defined by the IBM alliance and the test chip produced here are towards the same goal and is expected to meet technology requirements for products.

We also quizzed Khare on the commercial viability of the proposed 7nm node. Usually, as chip makers move to smaller processes, more chips can be crafted from one silicon wafer, which drives down the cost of each chip. Over the last few years, however, as we've moved past 28nm, new processes have been so complex that cost reductions have mostly dried up. Khare's response was somewhat ambivalent:

It's not a given that shrinking makes the next generation of chips less expensive. Given the performance improvements and power efficiencies achieved with 7nm chips, it is expected that the performance-per-cost trade-offs make it a viable technology.

And now, we wait. 10nm is currently being commercialised by Intel, TSMC, GlobalFoundries, and Samsung. It is much too early to guess when 7nm might hit mass production. Earlier this week, a leaked document claimed that Intel was facing difficulties at 10nm and that Cannonlake (due in 2016/2017) had been put on hold. In theory, 7nm should roll around in 2017/2018, but we wouldn't be surprised if it misses that target by some margin.

If IBM and friends actually get 10nm and then 7nm out of the door with relative ease, though, then Intel's process mastery might finally be in contention.