Introduction

Oldland is a 32-bit RISC CPU targeted at FPGAs. The main features are:

5 stage load/store pipeline.

16 general purpose registers.

N-way set-associative blocking instruction/data caches

Software managed instruction/data TLBs with 4KB page size.

JTAG debug controller for execution control and state modification/inspection.

Exception table for interrupts, data/instruction aborts, illegal instruction and software interrupts along with separate ITLB/DTLB miss handlers.

User and supervisor modes.

Keynsham is a SoC using Oldland as the core and has a number of peripherals:

32MB SDR SDRAM controller.

SPI master with configurable number of chip selects.

On-chip bootrom.

On-chip memory.

Programmable timers.

Interrupt controller.

UART.

SPI master.

There is a C model along with Icarus and Verilator RTL simulations. The Keynsham SoC can be synthesized to run on a Terasic DE0 Nano or DE0-CV. There are ports of binutils, gcc, newlib, u-boot and RTEMS available.

The Terasic DE0-CV using an Altera Cyclone V and the DE0-nano board using an Altera Cyclone IV are the supported boards running at ~75MHz on slow silicon @85°C.

Documentation

Testing

Get the Docker images for the build environments:

docker pull jamieiles/oldland-buildenv

Clone oldland-cpu and build with:

git clone https://github.com/jamieiles/oldland-cpu.git git submodule init git submodule update

Enter the build environment:

docker run -it -v $( pwd ) :/data/oldland jamieiles/oldland-buildenv /bin/bash

Build, install and test inside the build environment:

mkdir BUILD cd BUILD cmake /data/oldland/oldland-cpu make all install -j16 oldland-test

Running On Hardware

Build the FPGA image in Quartus and load it onto the device. Run oldland-jtagd on the development machine, oldland-debug can then connect to the CPU over the virtual JTAG.

Licensing

This project is currently licensed under GPLv2 except for oldland-jtagd which is under the Apache License v2.0.

About the Author

I’m Jamie Iles, you can reach me at jamie@jamieiles.com. I’m a software engineer, working at Oracle, leading the Ksplice engineering team.