Time for another update for the Hackaday 68k, the 16-bit retrocomputer developed on Hackaday to show off both our love for vintage hardware and our new project hosting site. There’s still invites to be had, people. Get ’em while they’re hot.

This post is going to cover exactly how complex a simple 68000 system is. The answer is, “not very.” A simple 68k system is at least as simple to design than some other homebrew systems we’ve seen around here. Yes, a 16-bit data bus means there’s more wires going everywhere, but like she said, just because it’s bigger doesn’t mean it’s harder.

There is some progress to report on the construction of the Hackaday 68k. The processor has been verified as working with a blinking LED. It’s the ‘Hello World’ of computer design, and it’s at least as complex as blinking a LED with an Arduino.

You’re gonna want to click that ‘Read more’ link.

The Journal Of Simple 68000 Systems

At least half of the purpose for this project is to demonstrate the 68000 is well suited – simple, even – for a homebrew computer project. The homebrew systems that infrequently hit the Hackaday tip line are usually based around the 6502 CPU, or at the very least something in that family. Now, how do we compare a simple 6502 and 68000 system? How about describing a simple system with both chips?

Building a simple 6502 system

For a simple 6502 system, you’ll want the 6502 itself, some RAM, and an EEPROM. Let’s just say we’ll use a 62256 SRAM for the RAM, and a 28256 EEPROM for the ROM. Wire up the RAM starting at $0000 and make sure you have some of the EEPROM at $FFFF. A few NAND gates will do for the logic glue. Ground the A14 pin of the RAM, and you’ll have a basic system with 16k RAM, 32k ROM, and a lot of space to put in any peripherals.

Throw in a 6551 ACIA and you have a serial port. With a little bit of glue logic and a MAX232 chip, you can make a simple 6502 system that’ll run BASIC. Put a pin header on the 16 address and 8 data lines and you have an extensible system using seven chips:

6502 CPU

28256 EEPROM

62256 SRAM

6551 ACIA

MAX232 serial thingy

74HC04 and 74HC00 logic ‘glue’

Wiring these up involves using the address lines for decoding, the R/W and Phi2 lines for memory control, and shoving a clock signal and reset circuit in there somewhere. You’ll need a crystal, some caps , a few resistors, and a reset button, but there you have it: a simple 6502 system. You can build this on a breadboard in a weekend. No. Big. Deal.

Building a simple 68000 system

“But the 68000 is so much more complex!”, you cry, “There’s more pins! Sixteen of them, and that’s just the data lines! What the hell is BGACK?” I’m not saying you’re wrong, but I do choose to ignore you. It’s actually very easy to construct a simple 68000 system, if you know what pins to ignore:

/DTACK & /BERR

DTACK is a product of very small and slow memories available in the late 70s. The idea behind DTACK was to have the RAM (or ROM, or whatever) acknowledge it got the required data off the data bus. If the RAM (or whatever) didn’t put this pin low in time, the CPU would enter a ‘wait state’; basically the 68000 would just sit there until the RAM caught up.

Now, with fast, huge SRAMs and modern components, you don’t have to worry about this. Ground DTACK and you’ll be fine. Do your calculations for the timings, but you’ll be fine.

BERR is the Bus Error pin, telling the CPU something is wrong with a MMU, there’s a “non-responding device”, or something else sufficiently complex that it shouldn’t be included in a minimal system. Tie this pin to +5 V.

Bus Arbitration Control; /BR, /BG, & /BGACK

These pins are for DMA. We’re doing a simple system here, so no DMA. Tie BGACK and BR to +5 V, and ignore BG. Done.

Interrupt Control; /IPL0, /IPL1, & /IPL2

Interrupts? Again, we’re doing a simple system with some RAM, ROM, and a serial port. Tie these to +5.

M6800 Peripheral Control; E, /VPA, & /VMA

The old Moto engineers that designed the 68000 were extremely cool and gave 68000 system designers a way to interface the old 6800-series parts – ACIAs, display processors, the RIOT, PIAs, floppy disk controllers – to the 68000. These pins are how you do it. Are we using any of these parts? No? Good. Tie /VPA to +5 and ignore /VMA and E.

Processor Status Pins; FC0, FC1, & FC2

These pins tell the rest of the system if the CPU is currently in user or supervisor mode, the kind of stuff that would be handy for an MMU to have. Are we using an MMU? Then ignore these pins.

So, where does that leave us? We have 16 data pins, 23 address pins,, and a few others: We can tie Reset and Halt together. The asynchronous bus control pins, /AS, /UDS, /LDS, & R/W are all that’s needed to do a proper memory decoding and control.

How does that compare to a 6502? With the 8-bit chip, you’ll need to use the R/W pin to tell if you’re reading or writing, and the Phi2 pin on the 65xx is analogous to the /AS pin on the 68k. Really, if you design something with a 68000, the only real difference between it and an 8-bit chip are the /UDS, & /LDS pins, and they’re only there for accessing either D0-D7 or D8-D15.

A chip count for the 68000? You’ll need a CPU, two 8-bit RAM chips, two 8-bit EEPROMs, some sort of ACIA, and a bit of glue logic. You can do that in a dozen chips, max. It’s a lot more wires or traces between chips, but that’s neither here nor there.

So there you go. A reasonable case for the 68000 not being overly complex for a homebrew project.

Blinking A LED

The ‘Hello World’ of computer design is freerunning the processor. All this means is to get the CPU cycling around its address space with an instruction hardwired onto the data pins, attaching an LED to one of the higher address pins, and turning it on. The LED will blink depending on the clock speed and what pin the LED is wired up to. Here’s the video:

That’s the 68000 with the all the data pins tied to ground, the /AS, /UDS, /LDS, & R/W pins ignored, and a Maxim DS1813 reset chip to handle the power-on and push button reset. I’m running it with a 4MHz oscillator. Anyone care to guess what address pin that LED is tied to?

I would like to note that since the 68000 has 68,000 transistors, it’s still possible I’m using fewer transistors to blink a LED than I would with an Arduino. If anyone from Atmel has a more precise count for the number of transistors on an ATMega, drop a note in the comments.

What’s Next

Unfortunately there’s a rather large gulf between blinking an LED and the next, “look what I did!” post. There’s a lot of thought that goes into address decoding for the RAM, ROM, and peripherals, and a shocking amount of work that goes into wirewrapping these chips together. Here’s the current state of the RAM board:

That’s eight 512k x 8 SRAM chips, with the data and address lines all wired up. Blue is data, green is address. I’m not quite sure how long it took me to wrap all those pins, as I’m measuring the time in units of Deep Space Nine episodes. I can tell you that wirewrapping, DS9, and a six-pack is the closest I’ve come to bliss.

For the next post, I’m going to go over the address decoding and memory control logic for the RAM, ROM, whatever I’ll be using for a serial port, as well as the bus transceivers. Then I’ll actually have to wrap all these circuits up; not a quick job. A little code burned onto an EEPROM, and then I’ll actually have something to show off. It’ll be awesome.

Until then, you can check up on my progress on Hackaday Projects.