Moore's Law is back. Or maybe, it didn't really end, just took a little vacation.

There have been concerns that Moore's Law – which states the number of transistors per chip will double every two years – is slowing down, as Intel's transition to a 14nm process has taken longer than expected, and the more general chip-making foundries are later than usual in delivering their next process. But to me, the big takeaway from Intel's Broadwell announcement last week, as well as Samsung's less-heralded comments that it was shipping a 20nm applications processor in its latest smartphone, is that chip-scaling seems to be continuing, despite some delays.

The Broadwell announcement was a little late. Originally, Intel had planned to have chips shipping by the end of 2013 and a full line of 14nm notebook products out by now. But Intel gave a lot of details last week that showed it has made a lot of progress on 14nm, with the specifications looking better than many had expected.

As announced at the Computex show in June, Intel's first 14nm chip will be Broadwell-Y, with the Y-standing for the lowest-power version of the chip, and marketed under the name Core M. This chip was the focus of last week's announcement, which detailed many specifications about the chip and Intel's 14nm process, which includes the second generation of what the company calls its "Tri-gate" transistors (which other people are calling FinFETs.)

The practical result of these chips is that they will enable fanless tablets and laptops that are less than 9mm thick, bringing the Core design to fanless systems. According to Rani Borkar, Intel's Vice President of Platform Engineering, Intel has doubled the CPU core performance between 2010 and 2014, increased graphics performance by seven times, and reduced power requirements by 4 times, enabling systems with half the battery size but double the battery life.

Presenting many of the technical details, Intel Senior Fellow Mark Bohr showed how the transistors have scaled in almost all dimensions, as shown in the slide above. Some of the measurements were at a Moore's Law clip, some were better, some were a bit worse, but the combination looks very strong. (Note that the process node designation was originally the size of the smallest feature, and if the gate pitch were to decline by a scale of 0.7, you would get the transistors to shrink in half.) Interestingly, the height of the transistor fins is larger in the new process (now 42 nm, as compared with 34 nm), resulting in taller and thinner fins, which should result in better performance and lower leakage.

Overall, Bohr said that the size of an SRAM memory cell on a CPU (one of the standard cells used in chip design) would decrease from .108 um2 to .0588 um2, a 54 percent reduction in size. And for the logic area of the chip, he said, scaling was continuing to improve at 0.53x per generation. (That's very impressive, given the issues in chip scaling, especially since the process still uses immersion lithography, as Extreme Ultraviolet or EUV lithography is still years away.) As a result, he said Intel has "true 14nm," which it is delivering both denser and faster than what other foundries are calling 14nm or 16nm.

Bohr said each generation is continuing to provide improvements in performance, active power, and performance per watt. In fact, Bohr said that while Intel has increased performance per watt at a rate of 1.6x with each new generation, Broadwell-Y will deliver more than double the performance per watt compared to the current generation due to the second-generation tri-gate transistors, more aggressive physical scaling, close collaboration between the process and engineering teams, and enhancements to the microarchitecture.

One of the big questions that a lot of analysts have had about Moore's Law is a belief that while new process nodes are going to be able to put more transistors in the same space, the cost of making the transistors is not going to continue to decrease, in part because at 20nm and below, many process steps will require "double-patterning" using immersion lithography. But Bohr showed slides showing that the cost per transistor continues to decrease, saying some new techniques have helped it reduce costs by more than usual at this node. "For Intel, cost per transistor is continuing to come down, if anything at a slightly faster rate using this 14nm process technology," he said.

While yield on 14nm was initially below the yield on 22nm (thus contributing to the delay), Bohr said yields are now "in the healthy range" and improving, with 14nm products being manufactured in Oregon and Arizona this year, and in Ireland next year.

For the Broadwell Y, Intel said a combination of process technology and design has allowed for twice as much power savings as traditional scaling would deliver. Some of the changes include optimizing the chip for low-voltage performance. Overall, the package (which includes the die and the surrounding board) should take up about 25 percent lower board area than the Haswell U/Y (low power) parts, with reductions in all dimensions.

Stephan Jourdan, an Intel Fellow in the Platform Engineering Group, said that the CPU core itself would provide about a 5 percent improvement in single thread instructions per cycle, while the chip offers more significant graphics and media processing improvements (such as 20 percent more compute and up to twice the video quality). In addition, it now includes support for 4K resolutions, as well the most current DirectX and Open CL software drivers, solving an issue that Intel's integrated graphics have had until now.

Core M systems using the 14nm Broadwell Y chip should be on the market in time for the holiday season, with other members of the Broadwell family now slated for the first half of 2015. More details are likely to come at next month's Intel Developer Forum.

The other big chip news was somewhat buried in the stories about the Galaxy Alpha. Samsung said that many models of the phone will use its new Exynos 5 Octa (Exynos 5430) System on Chip (SoC) produced on a 20nm High-k/metal-gate process. While this chip doesn't have radically new CPU features from the earlier 28nm version of the Exynos 5 Octa, with four 32-bit ARM Cortex-A15 chips running at up to 1.8 GHz and four Cortex-A7 chips running at up to 1.3 GHz in a big.LITTLE configuration, it is notable for being the first ARM chip shipping using a 20nm process, which Samsung claims will enable 25 percent lower power consumption. In addition, it now supports displays up to 2,560-by-1,600-pixel displays and has native H.265 decoding. (Note. U.S. versions of the phone are likely to use the Qualcomm Snapdragon 801 instead, with U.S. carriers mostly supporting Qualcomm's LTE technology.)

Again, what makes this unique is the 20nm applications processor, which appears to be the first one shipped (outside of Intel's 22nm process). Such chips were expected earlier, but while Qualcomm has a 20nm modem out, its 20nm Snapdragon 810 application processor isn't expected until the first half of 2015. On the other hand, there are rumors that Apple will announce and ship a 20nm A8 processor for its upcoming iPhone 6.