This is a ROM to test CPU cycle accuracy in emulators & FPGA hardware targeted at the PC-Engine / TurboGrafx-16 game system. It is a visual test, so really it's comparing the CPU timing against correct emulation of the VDC & VCE video chips. In the test, each scanline "starts" with a change in the background colour, and then a single CPU instruction is looped over many times until the CRT beam wraps around and reaches the same spot one line below. I've put all 2-cycle opcodes to be tested together on one screen; all 3-cycle opcodes on another, and so on. Thus, correct timing for (almost) every instruction can be quickly checked as the start- and end-points should line up vertically, minus the odd 1-cycle correction here and there. If the raster split carries down the screen at an angle, then the cycle timing is incorrectly emulated. If the angle heads down and to the left, then somehow the CPU is being emulated too fast. If the angle heads down and to the right, then CPU emulation is too slow. These cycle-timed CPU opcodes can be run either from ROM or RAM. When they are running in RAM, each instruction can be highlighted in the raster display if you press up or down. This can help to single out which instructions are running too fast or slow. If a single instruction's scanline clearly doesn't reach back on itself, then CPU emulation is too fast. If the same coloured scanline wildly overlaps with itself from above, then CPU emulation is too slow.