This week I attended FPGA2020 in Monterey, Seaside, California. This was my second FPGA conference, and I really enjoyed it. The conference was held at the same place as last time, and the omelette in the hotel was amazing as usual. The following are my summary of interesting talks related to high-level synthesis (HLS). Please feel free to correct me in the comments if I understand wrong.

Tutorial: From C/C++ to Dynamically Scheduled Circuits

In the first morning, there were three tutorials held in parallel: Vitis introduction, dynamically scheduling HLS tool and FPGA hardware security. As an HLS tool guy, I attended the second tutorial.

Lana Josipovic, Andrea Guerrieri and Paolo Ienne from EPFL introduce their HLS tool named Dynamatic. Dynamatic is a new HLS tool that supports the synthesis of dynamically scheduled hardware from C++ code. Lana gave us a talk to show how to use the tool to generate the hardware and perform hardware optimisation like buffering and LSQ configuration.

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration

Yuze Chi introduced a frontend of HeteroCL. His paper is a continuing work of the FPGA2019 best paper HeteroCL, which allows users to write more effcient code.

Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization

Yu Zou introduced a general combinatorial optimisation problem solver based on FPGA. The application was quite new to me, but the talk was quite clear and interesting. Their graph-based formulation attrated my attention, and I look forward to reading his paper later.

Keynote II: Xilinx’s Vitis Unified Software Platform

Vinod Kathail gave a keynote talk to introduce Vitis. In the HLS part, the two most exciting thing for me. In Vitis HLS, they get rid of the support of pragmas, so the tool can automatically perform hardware optimisation based on a simple input code. Also, the frontend, i.e. the LLVM transformation, will be open-sourced. Vitis HLS allows LLVM IR code as input, and its backend will automatically schedule the code and synthesise into hardware.

Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis

How complicated can a matrix multiplication be? Johannes de Fine Licht from ETH tells you it is so different in the HPC area. He shows his great open-sourced work to accelerate matrix multiplication in HLS for HPC. He showed that their library has better performance than the pre-installed IP library in Vitis, which was quite impressive! As the evaluator for their artifacts, I am impressed by their work and feel grateful to try his library at a very early stage. Use their tool here!

FPGA2020 Best paper: Buffer Placement and Sizing for High-Performance Dataflow Circuits

Lana Josipovic proposes a novel approach to use marked graph formulation to model the buffering problem in the dynamically scheduled dataflow circuit. It solves the problem of low throughput due to the backpressure in the unbuffered circuit. Like last year, she used interesting animations in the slides to demonstrate how token flows in the dataflow circuit. I really like it!

Combining Dynamic & Static Scheduling in High-level Synthesis

This year I co-authored with Lana Josipovic and Paolo Ienne (also with my supervisors George Constantinides and John Wickerson) to propose an HLS platform tool named DASS. The existing HLS tools both have advantages and disadvantages, and the users have to compromise when choosing one of them. Our tool built on top of these HLS tools to provide another solution that allows users to customise their scheduling approaches in different parts of the hardware. Our results are quite promising, and more details are here (paper) and here (tool). Our collaboration was a great success, and I want to thank Lana and Paolo again to make this work possible! I also thank the guidance from my two amazing supervisors to make me better today!

Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator

Tanner Young-Schultz gave a talk of how he used OpenCL to make designs on FPGA to kill cancer! The animations were quite exciting and brought a lot of fun in the talk. I am a big fan of his work as he detailedly explained what challenges he had during the hardware optimisation at the code level and how he solved them.

Other applications I found interesting:

Apart from Tanner’s work, there are also sevaral interesting application works using HLS:

FPGA-Accelerated Samplesort For Large Data Sets BiS-KM: Enabling Any-Precision K-Means on FPGAs Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-Design

Finding and Understanding Bugs in FPGA Synthesis Tools

This may not be a HLS-related topic, but I really like it! It is a work by my colleague Yann Herklotz and my supervisor John Wickerson. They build a fuzzing tool to automatically find Verilog bugs in the modern FPGA synthesis tools like Quartus and Vivado. The reason why it is interesting is that they found no bug in Quartus Prime and increasing numbers of bugs in Vivado with the version. 😛

Summary

Compared to last year, my general impression for this year is that the number of works with HLS increases significantly. This motivates me a lot to provide better HLS tool supports for them!