If you’re looking for a great video describing the essentials of Moore’s law in under 10 minutes, perhaps for your non-HPC friends and family, look no further. With a direct, easy-to-follow delivery, Professor Derek McAuley with the School of Computer Science at the University of Nottingham lays out the elements of chip design and manufacturing that have today’s chip designers butting up against the laws of physics.

McAuley refers to Moore’s law – Gordon Moore’s observation that the transistors in a given area doubles every two years or so – as the “sweet spot” that occurs with each generation of processors, each time the feature size of a chip’s components (e.g., transistors and wire) get reduced.

The professor recalls early on in his career working at Acorn Computing when his colleagues Sophie Wilson and Steve Furber were designing the ARM processor. At this point, they were all very excited about 3 micron technology, the feature size of the transistor. Today the industry is down to 28 or 22 nanometers.

Professor McAuley gets into describing how transistors are made using semiconductor materials doped with ions (p or n materials) and the slowing down of Moore’s law. “Each generation has required better understanding and more complex optical systems,” says McAuley.

“As these feature sizes get smaller, the areas of the transistor can only fit so many ions or atoms of the doping material – and as it gets smaller and smaller, the number gets less and less. As we get to very small numbers of atoms, the quantum mechanics behavior of the transistor and the probability that it does the right thing start to reduce.”

McAuley continues by saying the prediction that Moore’s law will run out is essentially saying that the transistors will start to do the undesirable thing too often. Error correction can be used to abate some of this behavior, but it only goes so far when errors become too numerous.

There are still many other areas open to development, however, and McAuley sees promise in architecture innovation and 3D chip design.