Ok, now it is kind of proven that binary CPLD (or FPGA) may implement ternary logic, but how we can integrate it with "true" ternary components, especially when CPLD is 3.3V and TRIMUXes are -5V and +5V? Answer is DG403 chips may do the job:

Because simplified ternary mutexes e12 and e21 can be easily implemented by DG403 integrated circuits:

So we need to have ONE DG403 per every binary represented TRIT and it doesn't matter if it's input or output, but number of inputs should be multiple by 2 in order to use DG403 chips optimally. Also we can do similar interfacing for binary ROM or RAM that may also be required for complex ternary systems. For example we can do translation from triad (3 trits) to a byte the same way how it's already done in 3niti alpha simu1 ternary computer simulator on PIC16:



;Format of the triad: ; |7| 6 |5| 4 |3| 2 |1| 0 | ;| + |-| + |-| + |-| + |-| ; |par| low |mid| high ;par (parity) is not yet used, so it 's always 0 0 for now... tOOO EQU 0x00 ; 0 tNOO EQU 0x01 ; -9 tPOO EQU 0x02 ; +9 tONO EQU 0x04 ; -3 tNNO EQU 0x05 ; -12 tPNO EQU 0x06 ; +6 tOPO EQU 0x08 ; +3 tNPO EQU 0x09 ; -6 tPPO EQU 0x0A ; +12 tOON EQU 0x10 ; -1 tNON EQU 0x11 ; -10 tPON EQU 0x12 ; +8 tONN EQU 0x14 ; -4 tNNN EQU 0x15 ; -13 tPNN EQU 0x16 ; +5 tOPN EQU 0x18 ; +2 tNPN EQU 0x19 ; -7 tPPN EQU 0x1A ; +11 tOOP EQU 0x20 ; +1 tNOP EQU 0x21 ; -8 tPOP EQU 0x22 ; +10 tONP EQU 0x24 ; -2 tNNP EQU 0x25 ; -11 tPNP EQU 0x26 ; +7 tOPP EQU 0x28 ; +4 tNPP EQU 0x29 ; -5 tPPP EQU 0x2A ; +13

As you can see we directly translate triad to byte and vice versa for data, but we can do the same for address - lower 3 trit of address can address the same 48 bytes (so instead of 27 triad one page will occupy 48 bytes of binary memory). Higher trits of address may or may not have similar translation.

Also we can have a special CPLD that converts ternary address to binary address optimally (without gaps and holes as above). Below you can see calculations for mostly used memory sizes:

2KB = 11-bit address = 6 trits (729 ternary cells - 28% used);

8KB = 13-bit address = 8 trits (6,561 ternary cells - 63% used);

32KB = 15-bit address = 9 trits (19,683 ternary cells - 48% used);

64KB = 16-bit address = 10 trits (59,049 ternary cells - 71% used);

128KB = 17-bit address = the same 10 trits (59,049 ternary cells - 45% used);

256KB = 18-bit address = 11 trits (177,147 ternary cells - 67% used);

512KB = 19-bit address = the same 11 trits (177,147 ternary cells - almost 34% used);

1MB = 20-bit address = 12 trits (531,441 ternary cells - almost 51% used).

As you can see we have better usage of binary memory in ternary computer system when it's 64KB addressed by 10 trits and this approach will use 71% of memory space.

< comp lib = "4" loc = "(850,300)" name = "ROM" > < a name = "dataWidth" val = "10" /> < a name = "contents" > addr/data: 8 10 0 1 6 4 5 1a 18 19 12 10 11 16 14 15 6a 68 69 62 60 61 66 64 65 4a 48 49 42 40 41 46 44 45 5a 58 59 52 50 51 56 54 55 1aa 1a8 1a9 1a2 1a0 1a1 1a6 1a4 1a5 18a 188 189 182 180 181 186 184 185 19a 198 199 192 190 191 196 194 195 12a 128 129 122 120 121 126 124 125 10a 108 109 102 100 101 106 104 105 11a 118 119 112 110 111 116 114 115 16a 168 169 162 160 161 166 164 165 14a 148 149 142 140 141 146 144 145 15a 158 159 152 150 151 156 154 155 13*0 2aa 2a8 2a9 2a2 2a0 2a1 2a6 2a4 2a5 28a 288 289 282 280 281 286 284 285 29a...

In case of TRIADOR we have 6-trit address for program memory - it has addresses from -364 to +364 and each read-only memory cell should have 5-trit value - to simplify things in my Logisim model I addressed 2K binary ROM directly when every TRIT of ternary address is converted to 2 BITS of binary address, but in this case it has to bebits total, but we have only(2^11=2048) - my idea was to allow user to use ternary addresses from ONNNNN to PPPPPP only (it is 66% of all 6-trit address space and should be more than enough for start) and we need to convert 1-byte data to 5-trit program word by another smaller ROM (or CPLD):