On May 4th, 2011, Intel Corporation announced a radical shift in the semiconductor technology in the last 50 years, the first 3D (three-dimensional) transistors. The new 3-dimensional transistor design enables the production of integrated circuit chips that operate faster with less power. It was Intel’s first FinFET technology. 2.5D and 3D are the best alternatives to transistor scaling in order to sustain Moore’s law.

How is 3D Structure different than 2.5D?

In 2.5D structure, there is no stacking of dies on dies, but dies are on Silicon Interposer. The dies are packed into a single package in a single plan and both are flip-chipped on a silicon interposer.

In 3D structure, Interposer and dies are stacked one above another. Dies interact among each other with TSVs (Through Silicon Vias). TSV is a high performance interconnects made of a pillar-like structure with Copper, Tungsten or Poly through silicon that provides electrical interconnects through a silicon die or through-wafer.

Lowest die directly talks to the package through the interposer. µbumps for connecting dies to TSVs, C4 bumps for interposer/die to package connections. BGA balls for a package to board.

How do 3D ICs help in Semiconductor industry?

3D integration promises to further increase integration density, beyond Moore’s Law and offers the potential to significantly reduce interconnect delays and improve system performance. Furthermore, the shortened wire length especially that of the clock net, also lessens the power consumption of circuits. 3D integration also provides a flexible way to carry out the heterogeneous system-on-chip (SoC) design by integrating disparate technologies, such as memory and logic circuits, radio frequency (RF) and mixed-signal components, optoelectronic devices, etc., onto different dies of a 3D integrated circuit (IC)

Factors that need to be considered for 3D ICs

System-level exploration:

Selecting appropriate silicon technology, choose the most advantageous die for optimization.

3D floor planning, placement, and routing:

3D floorplanner must function in the X, Y and Z direction

Whole PD flow should be Thermal-Aware. For example: Moving hot blocks/cells closer to heat sinks or apart from each other Deliberately insert thermal vias to 3D circuits Thermal vias can act as a pipe that allows the heat to be conducted from the higher temp region to lower temp region

3D Routing of ICs must take care of wire delay due to the effect of temperature Critical wires should avoid hottest regions Interlayer vias are a valuable resource that must be optimally allocated among nets

TSV stress, coupling and keep out areas penalty

Extraction and analysis:

Tools must consider RLC parasitics for TSVs, micro-bumps and interposer routing

IC/package co-design:

I/O feasibility planning, connectivity management, 3D visualization

To conclude, 2.5D and 3D are the best alternatives to transistor scaling in order to sustain Moore’s law and can achieve better throughput with an optimized area, performance and cost. It is most suitable for high-performance ASICs like HMCs (Hybrid Memory Cube), NAND flash, Optical sensors and Networking ASICs.

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