Testbench Verilog code for debouncing buttons:

`timescale 1 ns / 1 ps // testbench verilog code for debouncing button without creating another clock module tb_button; // Inputs reg pb_1; reg clk; // Outputs wire pb_out; // Instantiate the debouncing Verilog code debounce_better_version uut ( .pb_1(pb_1), .clk(clk), .pb_out(pb_out) ); initial begin clk = 0 ; forever # 10 clk = ~ clk; end initial begin pb_1 = 0 ; # 10 ; pb_1 = 1 ; # 20 ; pb_1 = 0 ; # 10 ; pb_1 = 1 ; # 30 ; pb_1 = 0 ; # 10 ; pb_1 = 1 ; # 40 ; pb_1 = 0 ; # 10 ; pb_1 = 1 ; # 30 ; pb_1 = 0 ; # 10 ; pb_1 = 1 ; #10 00 ; pb_1 = 0 ; # 10 ; pb_1 = 1 ; # 20 ; pb_1 = 0 ; # 10 ; pb_1 = 1 ; # 30 ; pb_1 = 0 ; # 10 ; pb_1 = 1 ; # 40 ; pb_1 = 0 ; end endmodule

Simulation Waveform of the Verilog code for debouncing buttons:

As shown in the simulation waveform, only a pulse with a period of the slow clock enable signal is generated when a button is pressed, held enough, and released as expected. Note that the divisor of 9 is used for faster simulation. If you want a single pulse with a period of the clock input to be generated, simply modify the output assignment "