As advanced packaging moves into the mainstream, packaging houses and equipment makers are ratcheting up efforts to solve persistent metrology and inspection issues. The goal is to lower the cost of fan-outs, 2.5D and 3D-IC, along with a number of other packaging variants consistent with the kinds of gains that are normally associated with Moore’s Law.

Many of these technologies have been under development for more than a decade, but much of that time was spent in researching the viability of these approaches and figuring out how various parts of the supply chain would need to coalesce. Until about two years ago, advanced packaging was seen as just one of several possible options by most chipmakers. Commercial versions of these packages for mainstream applications only started to appear in the past year or so for high-end networking. The iPhone 7, which is based on a wafer-level fan-out, was only introduced last September. And some some chipmakers say they are still waiting to see the impact of EUV on the cost of developing SoCs at the most advanced nodes before deciding what to do next after 28nm.

Still, there are a number of advantages to advanced packaging versus cramming everything on one die:

• Advanced packaging can offer improved throughput between logic, memory and I/O because the interconnects are wider. That can significantly improve performance and reduce RC delay.

• By bridging two or more chips, the distance signals have to travel may be less than across a single die.

• Contention for resources can be reduced by using multiple chips in a package, and so can routing congestion.

• Yields of smaller chips are higher than very large, integrated SoCs.

But the cost of the interconnects, the newness of the packaging flow, and the uncertainty of the outcome still give chipmakers pause before moving to advanced packaging.

“The metrology and inspection solutions available today are reasonably adequate, although a lower cost of ownership is still very much needed,” said Pandi Chelvam Marimuthu, senior director of STATS ChipPAC‘s Technology Division. “However, as the envelope of technology gets pushed further, certainly new metrology/inspection tools are needed for these packaging technologies, as well. 3D NAND is dealing with feature sizes that are finer by a few orders of magnitude (than planar), and layer count is significantly higher than what is seen in the packaging world. Hence, the challenge is much more complex.”

There is no single tool or methodology that will solve all of these problems. “We certainly need new equipment and methodologies to meet the challenges in the near future,” said Marimuthu. “This could be in multiple fronts such as lighting techniques, image capturing and processing to get better signal to noise in identifying defects. Defect review has been a huge burden in manufacturing. Innovation is very much needed here to get a breakthrough.”

There is no shortage of money and effort being thrown at this problem. But so far, the conclusion is that only so much of the inspection and metrology can be automated. As a result, cost savings will have to come from different places.

“You don’t want to miss a problem because you didn’t see it, so we have tightened up our final test equipment,” said Ou Li, senior director of engineering at ASE. “We test the functionality, and sometimes we take an image and send that image back to digital processing to figure out what kind of particle is on the device. If you automate that, you might miss it. Another problem comes when you have a large manufacturing line, because you’re not able to do a thorough inspection. A third problem involves supply chain collaboration. We’ve seen a number of arguments because we see a lot of chips from fabs and a lot of components from different vendors. If you don’t do a thorough inspection, you can have a quality and yield problem, and then it’s hard to argue whose fault it is. So, from different levels and different perspectives, there is a need for better inspection and a much higher standard for that inspection methodology.”

Just finding defects and other potential problems can be a challenge, though. “From a purely quantity inspection standpoint, in the old days you could get by using a 30X microscope,” Li said. “That doesn’t work anymore. You need a 300X scope even for basic things. You have to define the lighting and the procedures. Even for traditional manual approaches there is a higher standard. For a dimensional or small feature check, you used to be able to use a microscope to check the warpage dimension. That’s not enough anymore. Now we’re using automated optical inspection, or AOI, for in-line or final ratio inspection. This machine can tell us down to a few microns if there are particles, defects, discolorations, or dimensional offset.”



Fig. 1: Cu pillar sizes are decreasing, making fine pitch essential and inspection and metrology much more difficult. Source: ASE

Thinner is better…sometimes

All of this adds to the overall cost of advanced packaging. There are a number of ways to deal with this. One is to thin out the chips in the package. This is like Moore’s Law applied to a third dimension, because what you don’t save in 2D area you can save by thinning out wafers.

But thinning adds a new set of problems, because thinner wafers are subject to warpage, cracking, as well as damage in the packaging operation. They also can be destroyed with rough handling in the inspection and metrology.

“The warpage presents significant challenges in handling and inspection, since it requires the system to maintain focus required for sub-micron sensitivity,” said Gurvinder Singh, director of inspection product management at Rudolph Technologies. “But as the economies of traditional scaling become difficult and expensive, scaling the package will drive the performance of next-generation devices. Our customers are driving down the pitch for copper pillars, as well as reducing the RDL (redistribution layer) line and space. Dimension integrity (overlay, RDL metrology, bump height) becomes a key challenge for performance and integration of these devices in 2.5D and 3D packages. This shrink also leads to a tremendous challenge with cleaning off residue in these tighter-pitch applications. The residue in many cases is faint or transparent to conventional illumination techniques, so it’s not easily detectable. That impacts the performance or leads to field failures of the package.”

All companies working in this space report similar issues, as a whole. However, those issues are not necessarily the same from one customer to the next, or from one package design to the next.

“Defects can manifest in many ways,” said STATS’ Marimuthu. “It could be a residue issue that leads to higher contact resistance, a broken RDL metal layer, a short between 2 RDLs, or it can be a void. While an open/short can be identified by electrical testing, a reduction in space between conductor lines can be tricky. It can cause a leakage issue or potential reliability issue with electromigration when used in the end application. Such escapees are the challenges to inspection and metrology tools.”

Solutions to those problems aren’t consistent, either. Even within a particular packaging approach, such as fan-out wafer-level packaging, packaging houses and foundries often use similar technology differently.

“With fan-out wafer-level packaging, you have to measure the block compounds, the thickness, the RDL and the stack of layers,” said Gilles Fresquet, CEO of UnitySC, a wholly owned subsidiary of FOGALE nanotech. “The requirements for process control are deepening, and that has a direct impact on what you provide today. So the tools for process control are similar, but they are not necessarily in the same configuration. One foundry may have a wafer control molding compound where the thickness is in the 1 micron range, while with another approach it may be in the 10 micron range.”

Fresquet noted that a new slate of tools coming to market in the future will be able to work at the nanometer level, which will be critical for devices that include nanowires. “Using optics, you can reach the angstrom level on the Z axis,” he said. “But it’s still difficult to go to less than the nanometer level on the X and Y axes. You need to decrease the wavelength and increase the lateral resolution, which is difficult. And the only way to use optics at the nanometer level is with modeling. Right now, the focus is on 2-micron RDL, with 5/10/20µm microbumping.”



Fig. 2: TSV depth mapping. Source: UnitySC.

Even that comes in different flavors because more layers can be added into a package.

“Depending on the flavor of fan-out, there are different challenges,” said Stephen Hiebert, senior director of marketing at KLA-Tencor. “A 2-micron line/space is in development with chip-first and RDL-first. But if you have two or more chips in the same package, you have more redistribution layers. The trend right now is smaller dimensions with bigger packages and more metal layers. That moves everything in the direction of harder-to-achieve high yield, because as critical defects get smaller and density increases, yield goes down.”

Hiebert noted that the original fan-outs and embedded wafer-level ball grid array (eWLB) required fewer steps. “The process was more tolerant to defect density. But as you get more complexity, acceptable yields allow fewer defects per layer.”

Overlap between inspection and metrology

Unlike an SoC, where inspection and measurement are two very different steps, the lines tend to blur in advanced packaging because those steps so interdependent. An error of several nanometers could change the characteristics of chips in a package, for example.

“We do see the transformation of the inspection technology from traditional packaging to knowledge-based advanced system in package,” said ASE’s Li. “Metrology and inspection started to overlap because of the miniaturization. When devices got smaller and smaller, all the features that are critical for inspection methodology cannot work using old equipment and old methodology.”

There is general agreement on that point. “The old paradigm of a single discipline is no longer valid in this evolving and continuously innovating world of advanced packaging,” said Rudolph’s Singh. “Data is the key ingredient in understanding the impact of integration of these solutions on manufacturing and packaging. Fan-out panel level packaging (FO-PLP) is an excellent example where you see these different system and solutions being integrated. FOPLP requires key inspection and metrology steps, including kerf control, die shift measurement, correcting die placement systems and feeding forward to lithography systems, overlay and critical dimension measurement, polyimide/photoresist or metal residue detection, RDL defect (open/short/nick) detection, redistribution layer metrology (width, height), bump height and co-planarity.”

What’s important here is that combining these two steps can yield cost advantages, both in terms of faster time to yield and quicker identification of defects.

“Inspection has been a major cost adder and it scales with the number of mask layers,” said STATS’ Marimuthu. “As packaging solutions of the future require a higher number of masks to achieve higher levels of integration, reliance on Inspection is only going to go up. Since 100% inspection is needed to ensure quality and reliability, packaging houses cannot skip inspection in critical layers. Smart, innovative solutions are needed to lower the cost of inspection. To drive costs lower, we move away from circular formats to large, rectangular panel formats. Inspection/metrology solutions at a lower cost of ownership is very essential in this drive.



End-to-end cost issues

Still, packaging requires a different way of looking at problems than a single chip. There are more components from more vendors, and more steps in which these devices can be damaged.

“This is something of a mindset change,” said Lena Nicolaides, vice president and general manager at KLA-Tencor. “If you do chip first versus chip last, you need very high confidence in the yield. And you certainly need a system that is able to focus on the individual dies. Whether it’s thick or thin, if it’s autofocus and not adjustable, you are not able to inspect something adequately. You also need to be able to take out the warpage.”

That is easier said than done, particularly as the chips inside a package become smaller and thinner and the interconnect density increases.

“Higher density interconnect is pushing the packaging technology’s design and process control requirements beyond the current standards implemented,” said Singh. “Dimensions of some redistributed layers, through-silicon vias and other components have reached the size where sub-micron sensitivity is required for reliable defect detection. The industry already has driven the RDL L/S to 5µm, with a number of customers executing on a roadmap to drive this further down to 2µm L/S by the end of 2017. Conventional techniques for inspection and metrology employed in the traditional packaging world are running into limits requiring the need for a novel approach to new solutions or transferring some front-end solutions to the advanced packaging arena in a cost-effective manner.”

The cost of a mistake is rising, as well.

“Customers are committing multiple known good dies (KGD) to these packages so the cost of yield loss of the package is significantly high,” he said. “As a result, new process control steps with tighter tolerances have been added. A good example here is the addition of the kerf control check after saw. Customers are requiring a closed loop system that records the conditions of the dicer during the saw process and correlates it to inspection (die chipping and cracking) and metrology (kerf margins and offset). The ability to use the data to predict system issues and halt the system to prevent any further yield loss is an example of how our customers have adapted their manufacturing processes.”



Conclusion

After more than five decades of shrinking features, every facet of the supply chain and process has been tweaked for developing chips on a single die. Adding multiple chips into a package can greatly improve the speed, lower the power and eliminate some of the issues that are slowing the migration to the next process nodes, but it will take time to add the kinds of efficiencies and achieve the predictable yields that chipmakers have come to expect over the years.

“There are no standards today for advanced packaging,” said UnitySC’s Fresquet. “But the requirement for process control is deepening.”

This hardly raises a barrier to prevent chipmakers from utilizing the benefits of advanced packaging, but it does mean there is room for significant improvement in the process and methodology—and huge cost savings from both of those.

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