Europe is trailing the other major HPC powers in its quest to field exascale supercomputers. The first such European Union machines aren’t scheduled to come online until 2023, at which point the United States, China, and maybe even Japan are likely to have their initial systems up and running. But while Europe may ultimately lose the exascale horserace, it has used the milestone to do something more important – to develop homegrown processors and the requisite expertise to fuel its domestic HPC ambitions for years to come.

The processor development is being performed under the European Processor Initiative (EPI), an effort funded from the EU’s Horizon 2020 program. While the initial driver for EPI is to develop exascale-capable processors, the technology will also be used to target the broader markets of AI, data analytics, edge computing, and autonomous vehicles.

As we reported last year, when the project set out its initial roadmap, the effort will ultimately produce a processor package that incorporates Arm general-purpose cores with a RISC-V-based accelerator, along with a number of more specialized coprocessors. Since the initial roadmap was made public, the EPI developers have been busy pulling all the pieces together and filling in some of the details. The updated roadmap below, presented at an HPC User Forum meeting in September 2019 at Argonne National Laboratory, offers some additional details, including target delivery dates for the prototype and production HPC processors and the anticipated process nodes to be used.

In a recent conversation we had with EPI Board Chair Jean-Marc Denis, he outlined what has been going on behind the scenes to get the prototype out the door. That initial version, Denis confirmed, will be manufactured on Taiwan Semiconductor Manufacturing Corp’s 6 nanometer extreme ultraviolet (EUV N6) process and is expected to tape-out by the end of 2020 or the beginning of 2021. Testing will probably commence in Q2 2021 and continue through Q4.

The timeline depends on execution of the various members of the EPI consortium, not the least of which is SiPearl, a French company tasked with the commercial development and marketing of the different iterations of the platform. The company, which officially launched on January 21, was created as to be the principle business partner of EPI.

As we said, the near-term task will be to construct the EPI prototype. It will incorporate the Arm general-purpose processor, the RISC-V accelerator, Kalray’s MPPA and Menta’s eFPGA, as well as a cryptographic engine to support EU-specific sovereignty requirements. All this IP will be laid down on the same chunk of silicon, most of which will be devoted to the general-purpose Arm processor and supporting infrastructure. In the prototype only a small fraction of the die will be allocated to the other components, which will be implemented in a minimal form. The objective here, said Denis, is to qualify all the relevant IP on the N6 technology, not to build a fully functional HPC platform or hit particular performance metrics.

Note that this initial die will be part of a larger 2.5D interposer-based package that includes HBM memory, PCI-Express 5.0 links, plus interfaces to DDR memory. In subsequent implementations, the RISC-V and other accelerators could be split off into discrete dies and integrated into the package in the form of chiplets. But for now, everything will be etched on a single chip.

Denis told us that it’s still to be determined which accelerators and components make sense for the EU’s upcoming exascale supercomputers and how they will be apportioned across these machines. He suggested that different nodes could house different accelerator components or even none at all, with the common denominator across the system being the general-purpose Arm processor.

Programming such complexity would be made possible with the use of OpenMP 5.0 which would offer an abstraction layer between the accelerator hardware and the application. “So you unify the machine through programming model,” explained Denis, “with the same general-purpose processor everywhere, and just the backend of the compilers and libraries different when you offload to an accelerator.”

In this case, that general-purpose processor is based on Arm’s “Zeus” core, part of the third-generation of Neoverse line of processor designs, which the company invented to carry its namesake architecture into datacenter and edge environments going forward. Arm has said precious little about the what Zeus will contain, other than to report it will support the AI-inspired bfloat16 format.

Denis told us that Zeus component will be taken as is from Arm (EPI did not seek an architectural license) and is the main focus of the prototype. But given the inclusion of the RISC-V accelerator, as well the MPPA, and eFPGA components, it stands to reason that most of the platform’s performance will eventually be derived from these more specialized elements.

The RISC-V-based EPI accelerator (EPAC), code-named Titan, is itself of heterogeneous design, incorporating Vector Processing Units (VPUs) and Stencil/Tensor accelerators (STX). With an eye toward both HPC and AI acceleration, EPAC will support every standard numeric format from INT8 through FP64, as well as bfloat16. According to Denis, they’re also looking into something called variable precision, where the number of bits devoted to processing is adapted at runtime depending on the desired precision. That’s still in the early research stage.

EPI is also looking to bring other third-party IP to its common platform. To do this, the project plans to open up its hardware to other chipmakers by publishing the interface that glues the various components to one another. “The idea is quite simple,” said Denis. “Developing a general-purpose microprocessor is extra-difficult. It takes time and requires very, very high-end expertise that only a few companies with deep pockets can offer. At the same time, we see on the market many, many startups launching accelerators.”

Here he is mainly referring to the myriad of AI chipmakers looking to make their way into the market over the next several years. While it’s easy enough to build a PCIe-based accelerator card with these accelerators, there is extra value (and performance) to be had if this same IP can be integrated more closely with the host processor in a multi-chiplet package. And since EPI is essentially offering an EU-approved computing platform, these third-party IP providers may see this as an attractive market opportunity.

The project’s more immediate goal is to ensure the first-generation of the HPC product is available to its system partners, Atos and E4 Computer Engineering, for testing and qualification. If all goes according to plan, that should happen in the second half of 2021. The production hardware will then follow in the second half of 2022, which should line up with EuroHPC’s plans to deploy its first two exascale supercomputers on the continent in 2023.

Of course, when it comes to chip development, plans often get upended by unforeseen events. Denis is well aware of this, which is why the prototype is a relatively low-risk implementation. “It’s a long way to go before the launch,” he said, “but we are indeed moving forward.”