156.25MHz Output Clock Phase Jitter of 175fs RMS

Si5332 jitter performance is optimized to meet reference clock requirements in 10/25/100G data center, communications, and industrial markets. Integrated on-chip noise regulation eliminates the need for external LDOs and passive networks, providing added immunity to board and power supply noise to reduce effects on output clock jitter performance.

Achieving low jitter often comes at the sacrifice of high current consumption. Si5332 breaks that barrier, attaining current consumption levels 50% lower than competing solutions to help meet system current consumption budgets in energy friendly applications.