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The first three steps in the production process are related to the refining (Step 1), crystallization (Step 2), and wafering (Step 3) of the Si materials/substrates. The costs reported in this work (details in Appendix A ) are calculated considering the difference in the wafer spot prices between high purity Cz silicon and high-performance mc-Si, as retrieved in February 2018 [ 40 ]. As mentioned above, the spot prices are considered in this work since the calculated costs are to be applicable also to not fully vertically-integrated PV manufacturers. The following step in the black mc-Si PERC process (Step 4+5) includes only the single-side nanostructuring of b-Si via a deep reactive ion etching (DRIE). This is a pivotal step in the black mc-Si PERC process flow, since it allows the simplification of the overall process sequence by effectively removing the saw damage during the etching of the nanostructures. The complete removal of saw damage reduces the risk of contamination, which cannot be guaranteed with the current standard mc-Si texturing technology (acidic texturing), which requires saw damage as the initiator of the texture formation process. Furthermore, b-Si allows the adoption of the diamond wire sawing technology for mc-Si block wafering [ 25 ], which is broadly used for Cz-Si ingot wafering since it reduces the kerf-losses compared to the slurry-based wafering. Note that other b-Si etching technologies currently employed in the PV industry require additional steps for the b-Si etching process, i.e., metal-assisted chemical etching (MACE) [ 32 42 ] or atmospheric dry etching (ADE) [ 43 ]. Furthermore, it has been shown that black mc-Si etched by DRIE can be directly effectively passivated via double-side atomic layer deposition (ALD) [ 44 45 ], which further contributes to reducing the number of processing steps necessary for mc-Si PERC cells. Note that the thick SiNantireflection coating which is used in standard PERC cells, cannot be used on black-Si surfaces. The double-sided ALD passivation in the p-type black mc-Si PERC process (Steps 8 to 10) requires positively-charged layers for a good passivation. The costs were provided by an industrial manufacturer as detailed in Appendix A , and are calculated assuming (i) double-side 10 nm aluminum oxide (AlO) layer, (ii) deposition done by spatial ALD [ 46 ] and (iii) surface area enhancement factor equal to 3. Although AlOis not an optimized passivation layer for p-type crystalline Si due to its negative fixed charges [ 47 50 ], the use of ALD to grow passivation layers with positive fixed charges have been shown to be effective for application in Si solar cells, e.g., HfO 51 ]. Thus, the costs related to the use of the ALD precursors may differ slightly for the PV applications needed for the black mc-Si PERC. Nevertheless, the contribution of the precursor type in the total ALD process cost is of secondary order of magnitude compared to the other cost elements, and the error introduced in the calculation is thus negligible. The surface area factor is the ratio between the front effective area of the nanostructured surface and the flat projected area (i.e., the substrate area) [ 52 ], and it thus impacts the ALD costs due to an increased consumption of the precursors. A surface area factor of 3 has shown to be sufficient for low carrier recombination values at the surface [ 52 ], i.e., good electrical properties for power conversion in the final cell, while still maintaining excellent optical properties. Note that higher surface area factors are achievable by DRIE, and values of up to 7 have been shown to provide still good quality b-Si surfaces [ 53 ]; however, the step costs for spatial ALD would increase by a factor of 1.5 compared to the surface area factor of 3. Finally, the front-side metallization costs are also slightly affected by the total surface area, similarly to the ALD passivation, and by a possible difference in the firing temperature profile due to the different passivation layer. However, the contribution to the step costs due to the use of metal paste and firing profile can be considered negligible. It may be argued that the (uncapped) ALD AlOfront layer in the black mc-Si PERC impacts the front-side screen-printing process due to a change in the contact resistance compared to the SiNin the standard Cz-Si PERC. To et al. [ 54 ], however, showed that a thin AlOcapping layer (up to 5 nm) on the front side of a p-type PERC cell actually reduces the contact resistance compared to the uncapped SiN