Tiptop

Motivation

Hardware performance monitoring counters have recently received a lot of attention. They have been used by diverse communities to understand and improve the quality of computing systems: for example, architects use them to extract application characteristics and propose new hardware mechanisms; compiler writers study how generated code behaves on particular hardware; software developers identify critical regions of their applications and evaluate design choices to select the best performing implementation. We propose that counters be used by all categories of users, in particular non-experts, and we advocate that a few simple metrics derived from these counters are relevant and useful. For example, a low IPC (number of executed instructions per cycle) indicates that the hardware is not performing at its best; a high cache miss ratio can suggest several causes, such as conflicts between processes in a multicore environment.

Citing

Tiptop: Hardware Performance Counters for the Masses, Erven Rohou,

Inria Research Report 7789, Nov 2011.

<tiptop> <options> <option name="cpu_threshold" value="0.00001"/> <option name="delay" value="2.000000" /> <option name="batch" value="0" /> </options> <screen name="default" desc="Screen by default"> <counter alias="CYCLE" config="CPU_CYCLES" /> <counter alias="INSN" config="INSTRUCTIONS" /> <counter alias="MISS" config="CACHE_MISSES" /> <counter alias="BR" config="BRANCH_MISSES" /> <column header=" %CPU" format="%5.1f" desc="(unknown)" expr="CPU_TOT" /> <column header=" P" format=" %2.0f" desc="(unknown)" expr="PROC_ID" /> <column header=" Mcycle" format="%8.2f" desc="Cycles (millions)" expr="delta(CYCLE)/1000000"/> <column header=" Minstr" format="%8.2f" desc="Instructions (millions)" expr="delta(INSN)/1000000"/> <column header=" IPC" format="%4.2f" desc="Executed instructions per cycle" expr="delta(INSN) / delta(CYCLE)" /> <column header=" %MISS" format="%6.2f" desc="Cache miss per instruction" expr="100 * (delta(MISS) / delta(INSN))" /> <column header=" %BMIS" format="%6.2f" desc="Branch misprediction per 100 instructions" expr="100 * delta(BR) / delta(INSN)" /> </screen> </tiptop>

Features

No root privilege needed

No patch to OS

No module to load

No need to instrument applications

No need to even restart applications

Any event supported by the hardware some predefined: instructions, cycles, LLC misses (easy) any hardware supported event (slightly harder)

Live mode and batch mode

Configure file to define counters and screens

Pretty much like top

Requirements

Linux 2.6.31+

Nice to have: libcurses and libxml2

Download

Tiptop is available in source code on the Inria forge: https://gforge.inria.fr/projects/tiptop.

More Information

More information on tiptop is available in our Research Report RR-7789.

Be sure to check the README and the man page included in the distribution.

Specific counters for Intel architectures can be found in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.

Credits and Legal

Tiptop is proposed by the ALF project team at Inria Rennes Bretagne Atlantique. The main developer is Erven Rohou.

Tiptop is copyright Inria and released under GPL v2.

It is registered at the APP (Agence de Protection des Programmes) under number IDDN.FR.001.450006.000.S.P.2011.000.10800.