By Adam Taylor

Last week, we got AMP (asymmetric multiprocessing) up and running on the Zynq SoC and looked at the basic software running on the Zynq SoC’s two ARM Cortex-A9 MPCore processors. I now want to explore how we can use the Zynq SoC’s OCM (On-Chip Memory) to communicate between the cores. In the previous 48 instalments of the MicroZed Chronicles, we have not discussed the OCM except in passing. As we plan to use the OCM going forward, we need to understand more about what it is and how it functions. Like most things on the Zynq SoC, the OCM is much more powerful than its simple name suggests.

Zynq SoCs have 256Kbytes of on-chip SRAM that can be accessed from one of four sources, as shown in the figure of the Zynq PS (processing system) below:

The OCM can be accessed:

From either of the on-chip ARM Cortex-A9 MPcore processors via the SCU (Snoop Control Unit) From the PL (Programmable Logic) using the AXI ACP (Accelerator Coherency Port) via the Snoop Control Unit From the PL using one of the four AXI High Performance ports via the OCM Interconnect From the Central Interconnect again via the OCM Interconnect

With all of these different sources able to access the OCM, it is especially important we understand the OCM’s operation in detail before we use it.

With multiple sources accessing the OCM, it is only sensible that a form of arbitration and priority is defined for the access protocols. SCU reads and writes have the highest priority. (Reads have higher priority than writes.) Reads and writes initiated by the OCM interconnect have the next highest priority. Note: You can invert the priority between the SCU write and the OCM interconnect access by setting the SCU Write Priority Low in the OCM Control Register.

The OCM itself is organized into 128-bit words, split into four 64Kbyte regions placed at different locations within the PS address space. The initial configuration has the first three 64Kbyte blocks arranged at the start of the address space and the last 64Kbyte block located towards the end of the address space. You can see this in the linker files below for both applications (Core 0 top, Core 1 bottom):

Note the ps7_ram__XXX and ps7_ram_1 relate to memory regions 0 and 1 and not Core 0 and Core 1.

The OCM memory map can be re organized so that it’s completely contiguous and located at the end of the address space. You can set this configuration using the System Level Control Registers, the OCM Configuration register, and by setting the appropriate RAM Hi bits.

The OCM is single-port memory but you can emulate a dual-port memory using the Zynq SoC’s DMA engine to access the OCM in parallel with the OCM’s other transaction sources. To do this, the accesses must be 128-bit aligned and consist of even burst multiples of AXI commands. This approach achieves high throughput levels because the DMA engine can move large data volumes efficiently.

We can also add error protection to the OCM using the OCM Control Parity control register if we are using it for a particularly critical application. You can set odd or even parity individually on each of the 16 bytes that make up the 128-bit word stored at each OCM address. Through this register we can also configure how the Zynq SoC handles parity errors (by issuing the OCM shared interrupt (number 35) or by sending an AXI read error (SLVERR) when a read error is detected, for example).

Having now looked at the OCM in some detail, the next blog will look at how we can use this versatile resource for communication between the two Zynq processor cores.

Please see the previous entries in this MicroZed series by Adam Taylor:

Adam Taylor’s MicroZed Chronicles Part 48: Bare-Metal AMP (Asymmetric Multiprocessing)

Adam Taylor’s MicroZed Chronicles Part 47: AMP—Asymmetric Multiprocessing on the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores

Adam Taylor’s MicroZed Chronicles Part 44: MicroZed Operating Systems—FreeRTOS

Adam Taylor’s MicroZed Chronicles Part 43: XADC Alarms and Interrupts

Adam Taylor’s MicroZed Chronicles MicroZed Part 42: MicroZed Operating Systems Part 4

Adam Taylor’s MicroZed Chronicles MicroZed Part 41: MicroZed Operating Systems Part 3

Adam Taylor’s MicroZed Chronicles MicroZed Part 40: MicroZed Operating Systems Part Two

Adam Taylor’s MicroZed Chronicles MicroZed Part 39: MicroZed Operating Systems Part One

Adam Taylor’s MicroZed Chronicles MicroZed Part 38 – Answering a question on Interrupts

Adam Taylor’s MicroZed Chronicles Part 37: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 8

Adam Taylor’s MicroZed Chronicles Part 36: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 7

Adam Taylor’s MicroZed Chronicles Part 35: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 6

Adam Taylor’s MicroZed Chronicles Part 34: Driving Adafruit RGB NeoPixel LED arrays with MicroZed Part 5

Adam Taylor’s MicroZed Chronicles Part 33: Driving Adafruit RGB NeoPixel LED arrays with the Zynq SoC

Adam Taylor’s MicroZed Chronicles Part 32: Driving Adafruit RGB NeoPixel LED arrays

Adam Taylor’s MicroZed Chronicles Part 31: Systems of Modules, Driving RGB NeoPixel LED arrays

Adam Taylor’s MicroZed Chronicles Part 30: The MicroZed I/O Carrier Card

Zynq DMA Part Two – Adam Taylor’s MicroZed Chronicles Part 29

The Zynq PS/PL, Part Eight: Zynq DMA – Adam Taylor’s MicroZed Chronicles Part 28

The Zynq PS/PL, Part Seven: Adam Taylor’s MicroZed Chronicles Part 27

The Zynq PS/PL, Part Six: Adam Taylor’s MicroZed Chronicles Part 26

The Zynq PS/PL, Part Five: Adam Taylor’s MicroZed Chronicles Part 25

The Zynq PS/PL, Part Four: Adam Taylor’s MicroZed Chronicles Part 24

The Zynq PS/PL, Part Three: Adam Taylor’s MicroZed Chronicles Part 23

The Zynq PS/PL, Part Two: Adam Taylor’s MicroZed Chronicles Part 22

The Zynq PS/PL, Part One: Adam Taylor’s MicroZed Chronicles Part 21

Introduction to the Zynq Triple Timer Counter Part Four: Adam Taylor’s MicroZed Chronicles Part 20

Introduction to the Zynq Triple Timer Counter Part Three: Adam Taylor’s MicroZed Chronicles Part 19

Introduction to the Zynq Triple Timer Counter Part Two: Adam Taylor’s MicroZed Chronicles Part 18

Introduction to the Zynq Triple Timer Counter Part One: Adam Taylor’s MicroZed Chronicles Part 17

The Zynq SoC’s Private Watchdog: Adam Taylor’s MicroZed Chronicles Part 16

Implementing the Zynq SoC’s Private Timer: Adam Taylor’s MicroZed Chronicles Part 15

MicroZed Timers, Clocks and Watchdogs: Adam Taylor’s MicroZed Chronicles Part 14

More About MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 13

MicroZed Interrupts: Adam Taylor’s MicroZed Chronicles Part 12

Using the MicroZed Button for Input: Adam Taylor’s MicroZed Chronicles Part 11

Driving the Zynq SoC's GPIO: Adam Taylor’s MicroZed Chronicles Part 10

Meet the Zynq MIO: Adam Taylor’s MicroZed Chronicles Part 9

MicroZed XADC Software: Adam Taylor’s MicroZed Chronicles Part 8

Getting the XADC Running on the MicroZed: Adam Taylor’s MicroZed Chronicles Part 7

A Boot Loader for MicroZed. Adam Taylor’s MicroZed Chronicles, Part 6

Figuring out the MicroZed Boot Loader – Adam Taylor’s MicroZed Chronicles, Part 5

Running your programs on the MicroZed – Adam Taylor’s MicroZed Chronicles, Part 4

Zynq and MicroZed say “Hello World”-- Adam Taylor’s MicroZed Chronicles, Part 3

Adam Taylor’s MicroZed Chronicles: Setting the SW Scene

Bringing up the Avnet MicroZed with Vivado