Verilog code for Rising Edge D Flip-Flop with Synchronous Reset:

// FPGA projects using Verilog/ VHDL // fpga4student.com // Verilog code for D Flip FLop // Verilog code for Rising edge D flip flop with Synchronous Reset input module RisingEdge_DFlipFlop_SyncReset(D,clk,sync_reset,Q); input D; // Data input input clk; // clock input input sync_reset; // synchronous reset output reg Q; // output Q always @( posedge clk) begin if (sync_reset== 1'b1 ) Q <= 1'b0 ; else Q <= D; end endmodule

Verilog code for Rising Edge D Flip-Flop with Asynchronous Reset High Level:

// FPGA projects using Verilog/ VHDL // fpga4student.com // Verilog code for D Flip FLop // Verilog code for Rising edge D flip flop with Asynchronous Reset high module RisingEdge_DFlipFlop_AsyncResetHigh(D,clk,async_reset,Q); input D; // Data input input clk; // clock input input async_reset; // asynchronous reset high level output reg Q; // output Q always @( posedge clk or posedge async_reset) begin if (async_reset== 1'b1 ) Q <= 1'b0 ; else Q <= D; end endmodule

Verilog code for Rising Edge D Flip-Flop with Asynchronous Reset Low Level:

// FPGA projects using Verilog/ VHDL // fpga4student.com // Verilog code for D Flip FLop // Verilog code for Rising edge D flip flop with Asynchronous Reset Low module RisingEdge_DFlipFlop_AsyncResetLow(D,clk,async_reset,Q); input D; // Data input input clk; // clock input input async_reset; // asynchronous reset low level output reg Q; // output Q always @( posedge clk or negedge async_reset) begin if (async_reset== 1'b0 ) Q <= 1'b0 ; else Q <= D; end endmodule

Verilog code for Falling Edge D Flip Flop:

// FPGA projects using Verilog/ VHDL // fpga4student.com // Verilog code for D Flip FLop // Verilog code for falling edge D flip flop module FallingEdge_DFlipFlop(D,clk,Q); input D; // Data input input clk; // clock input output reg Q; // output Q always @( negedge clk) begin Q <= D; end endmodule