In this project, a 16-bit single-cycle MIPS processor is implemented in Verilog HDL. MIPS is an RISC processor , which is widely used by many universities in academic courses related to computer organization and architecture.

The Instruction Format and Instruction Set Architecture for the 16-bit single-cycle MIPS are as follows:

Instruction set for the MIPS processor

Instruction Set Architecture for the MIPS processor

Below is the description for instructions being implemented in Verilog:

Add : R[rd] = R[rs] + R[rt] Subtract : R[rd] = R[rs] - R[rt] And: R[rd] = R[rs] & R[rt] Or : R[rd] = R[rs] | R[rt] SLT: R[rd] = 1 if R[rs] < R[rt] else 0 Jr: PC=R[rs] Lw: R[rt] = M[R[rs]+SignExtImm] Sw : M[R[rs]+SignExtImm] = R[rt] Beq : if(R[rs]==R[rt]) PC=PC+1+BranchAddr Addi: R[rt] = R[rs] + SignExtImm J : PC=JumpAddr Jal : R[7]=PC+2;PC=JumpAddr SLTI: R[rt] = 1 if R[rs] < imm else 0

SignExtImm = { 9{immediate[6]}, imm

JumpAddr = { (PC+1)[15:13], address}

BranchAddr = { 7{immediate[6]}, immediate, 1’b0 }

Based on the provided instruction set, the data-path and control unit are designed and implemented.

Control unit design:





Control signals Instruction Reg Dst ALUSrc Memto Reg Reg Write MemRead Mem Write Branch ALUOp Jump R-type 1 0 0 1 0 0 0 00 0 LW 0 1 1 1 1 0 0 11 0 SW 0 1 0 0 0 1 0 11 0 addi 0 1 0 1 0 0 0 11 0 beq 0 0 0 0 0 0 1 01 0 j 0 0 0 0 0 0 0 00 1 jal 2 0 2 1 0 0 0 00 1 slti 0 1 0 1 0 0 0 10 0









ALU Control ALU op Function ALUcnt ALU Operation Instruction 11 xxxx 000 ADD Addi,lw,sw 01 xxxx 001 SUB BEQ 00 00 000 ADD R-type: ADD 00 01 001 SUB R-type: sub 00 02 010 AND R-type: AND 00 03 011 OR R-type: OR 00 04 100 slt R-type: slt 10 xxxxxx 100 slt i-type: slti





Data-path and control unit of the 16-bit MIPS processor