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The 32 nanometer (32 nm) lithography process is a full node semiconductor manufacturing process following the 40 nm process stopgap. Commercial integrated circuit manufacturing using 32 nm process began in 2010. This technology was superseded by the 28 nm process (HN) / 22 nm process (FN) in 2012.

Industry [ edit ]

TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the self-aligned via patterning.





Process Name 1st Production Lithography Lithography Immersion Exposure Wafer Type Size Transistor Type Voltage Metal Layers Gate Length (L g ) Contacted Gate Pitch (CPP) Minimum Metal Pitch (MMP) SRAM bitcell High-Perf (HP) High-Density (HD) Low-Voltage (LV) DRAM bitcell eDRAM

Design Rules [ edit ]

Intel 32nm Design Rules Layer Pitch Thick Aspect Ratio Image Isolation 140 nm 200 - Contacted Gate 112.5 nm 35 nm -- Metal 1 112.5 nm 95 nm 1.7 Metal 2 112.5 nm 95 nm 1.7 Metal 3 112.5 nm 95 nm 1.7 Metal 4 168.8 nm 151 nm 1.8 Metal 5 225.0 nm 204 nm 1.8 Metal 6 337.6 nm 303 nm 1.8 Metal 7 450.1 nm 388 nm 1.7 Metal 8 566.5 nm 504 nm 1.8 Metal 9 19.4 µm 8 µm 1.5 Bump 145.9 µm 25.5 µm -

Find models [ edit ]

Click to browse all 32 nm MPU models

32 nm Microprocessors [ edit ]

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32 nm Microarchitectures [ edit ]

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Documents [ edit ]

References [ edit ]