While giving very little detail about its future production plans, Intel used its investor meeting last week to re-emphasize how importantly it views Moore's Law, the statement from co-founder Gordon Moore that chip density will double every two years. The company talked about how its 14nm production process, now being used for its Core M and forthcoming broader Broadwell lines, showed a full generation's worth of scaling and said it expected similar scaling from its future 10 and 7nm nodes, despite increasing capital expenditures necessary at each node.

CEO Brian Krzanich began the meeting by talking about how Moore's Law will reach its 50th anniversary next year and said it remains one of the key strategic imperatives for the company. "It's our job to keep it going as long as possible," he said.

But it fell mostly to Bill Holt (above), general manager of the technology and management group, to explain how the company will get there.

Holt noted the issues that Intel has had in ramping the 14nm technology, noting it took more than 2.5 years to get the 14nm process on a good yield, instead of the normal two-year cadence. Currently, the 14nm yield is still not as good as the company gets at 22nm, but it's "in a healthy range" and is beginning to converge with the earlier process, which he said was Intel's highest yielding process ever. As a result, he said, the costs of manufacturing those parts are a bit higher in Q4, which will impact margins early next year, but that he expected that to change later in 2015. "True cost reduction remains possible in a capital intensive environment," Holt said.

Following some of the presentations I saw at the Intel Developer Forum a couple of months ago, Holt explained why the 14nm node was a true shrink, even as he agreed the 14nm nomenclature was essentially meaningless. "There's nothing that's 14 about that," he said.

But in comparison to its 22nm Haswell predecessor, the pitch between fins in the FinFET design was reduced to 0.70x (which he noted was the goal, since a reduction of 30 percent in each dimension would result in a full halving of the area of a die, assuming it had the same number of transistors), but that the gate pitch only shrunk to 0.78x. But, he noted, the interconnect pitch scaled further than normal to 0.65x (from 80nm to 52 nm) and the combination makes the full chip close to a full 50 percent smaller (all other things being equal). He noted this varies in different parts of the chip, with the SRAM's scaling by 0.54x, but the interconnects and graphics show more scaling.

To make this work, Intel created transistors from fewer, tighter, and longer fins to create the transistors. In other words, not only did the fins become closer together, they are now longer.

Other changes in this version include Intel's first use of "intentional" air gaps between components, enabling better interconnect performance.

Comparing a 14nm Broadwell chip to a 22nm Haswell version, Holt said the new chip has 35 percent more transistors—1.3 billion—but is 37 percent smaller, so it shows a 2.2x increase in transistor density with the extra transistors going toward things like improved graphics performance.

Overall, he said, you have to "actually get scaling" to reduce costs—an area where Holt said he believed Intel was ahead of competitors like Samsung and Taiwan Semiconductor Manufacturing Corp. (TSMC). He said the cost per transistor is still dropping and is even slightly below the historical trend line at 14nm, and predicted it would continue to be below the line at 10nm and at 7nm. And, he said, the new nodes would provide not only cost, but also performance improvements. At least through 7nm, he said, "we can continue to deliver the promises of Moore's Law."

In another presentation, Chief Financial Officer Stacy Smith explained the high cost of getting to each new node, showing the relative capital expenditure necessary to produce each node. He said it was getting harder and more capital intensive.

He noted that there has been an "uptick" in costs starting at 22nm, because of the necessity of multi-patterning (the need to use lithography multiple times on certain layers of the die), but said the number of wafer starts has gone down since the 32nm node because the weighted average die size is now smaller. Overall, though, the 14nm node is about 30 percent more capital intensive than the previous generation, but the basic chip is 37 percent smaller.

In total, Intel will spend about $11 billion in capital expenses in 2014 with plans to spend about $10.5 billion in 2015. About $7.3 billion of the 2014 expense is for building manufacturing capacity, with the rest going to research and development for future nodes and for development of 450mm wafers and typical corporate expenses such as office buildings and computers.

The expenses are so much, he said, that in part that's why there are now only four companies in the world creating leading-edge logic manufacturing: Intel, Global Foundries, Samsung, and TSMC.

In questions after their presentations, the Intel executives were careful not to give out too much information. Asked about costs and the possibility of switching to EUV lithography, Holt said the cost chart was "intentionally ambiguous" because they don't know how far below the historical cost per transistor line the next nodes would be. He said he believed they can get below the line without EUV, "but I don't want to."

Krzanich said the company thinks it signaled too much of its intentions to the industry about its 14nm plans, so "we'll be a bit more prudent in releasing information" about new manufacturing nodes. He wouldn't commit to the company's familiar Tick/Tock cadence of releasing a new process node one year and a new architecture the following year, though Smith said the company expects to be on a "fairly normal cadence" and "will talk about 10 nm in the next 12 or 18 months when appropriate."

3D NAND and the Road to 10TB SSDs

In another area of technology, Rob Crooke, general manager of Intel's Non-Volatile Memory Solutions Group (above), discussed new 3D technology in the making of NAND flash chips used in SSDs and similar devices. He suggested that solid-state devices are "only at the beginning of the adoption curve" and said that data wants to be closer to the CPU with just economics keeping them apart.

He noted that Intel made its first SSD—a 12 megabyte model—way back in 1992 and said the current technology is 200,000 times more dense today. Intel's current technology—developed in a joint venture with Micron—created a 256 gigabit NAND memory chip using 3D technology. In this technology, memory is held in cubes of transistors instead of the traditional "checkerboard" design and involves 32 layers of materials with about 4 billion holes for storing the bits. As a result, he said, you could create 1 terabyte of storage in about 2mm and more than 10TB in a traditional SSD form factor.

In addition to the small size, Crooke said SSDs offered huge performance improvements, saying 4 inches of NAND storage could deliver 11 million IOPS (input/output operations per second), which would otherwise require 500 feet of traditional hard drive storage. (He noted that while hard drives continue to get more dense, they haven't really gained in speed.)