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Announced at the 2017 Symposia on VLSI Technology and Circuits conference in Kyoto this week, IBM and our research alliance partners, GLOBALFOUNDRIES and Samsung built a new type of transistor for chips at the 5 nanometer (nm) node.

To achieve this feat, the architecture – how the elements of a chip are arranged and the materials used – had to change.

We stacked layers of silicon nanosheets together, horizontally, in order for this new architecture to enable our 5nm transistor to deliver the power and performance boost future applications will demand. The change from today’s vertical architecture to horizontal layers of silicon opened a fourth “gate” on the transistor that enabled electrical signals to pass through and between other transistors on a chip. At these dimensions, it means that those signals are passing through a switch that’s no larger than the width of two to three DNA strands, side-by-side.

More ways to send a signal on more 5nm transistors equates to a 40 percent performance improvement over 10nm chips, using the same amount of power; or a 75 percent power savings, at the same performance level. (Let that sink in while reading this article on a mobile device with 10 percent power left: 5nm chips would give you hours, not minutes, before needing to recharge. A future 5nm-chip-powered mobile device will last days longer than what’s in your hand right now.)

Opening the path to more gates

Today’s chips with vertical “fin” transistors, called FinFET, power today’s most-powerful 14nm and 10nm chips, and even our own 7nm test chip announced two years ago. That third dimension of a fin allows for three gates for improved power and efficiency (versus, as you may have guessed, the previous generation’s 2D “planar” chips). These FinFET chips, only recently beginning to make their way into servers, computers, and devices, will be the standard for years to come. For reference, it takes 10 to 15 years of research and development before a groundbreaking new chip technology proliferates the market.

The industry has long understood the limits of the various chip architectures. Our alliance working at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY has known that, for example, it’s possible to build a 5nm FinFET transistor from a structural perspective. But scaling from our 7nm chip’s 20 billion FinFET transistors per chip, to 30 billion 5nm FinFET transistors would not deliver the significant power and performance boost mentioned above.

After about a decade of studying the idea of putting gates all around the transistor – often referred to as Gate-All-Around (GAA) – stacked nanosheets delivered a GAA transistor for the 5nm node that actually improved density, performance, and power – all built with industry manufacturable tools and processes.

Wait! What about Moore’s Law?

The mere introduction of new chip technology means this question comes up. Today, Moore’s Law, in the context of logic technology scaling, breaks down into four parts: density, performance, power and economy. Density, or the number of transistors per square inch of a chip, has gone from Gordon Moore’s original observation in 1965 of doubling every 12 months, to now taking three years. Performance improvements have experienced a similar slowing. Power, while less influential at its introduction, has grown in importance due to our battery-hungry mobile devices. The economy, or cost per transistor, is the only element of the “law” that’s kept similar pace over the last 50 years.

A future 5nm node chip with nanosheet transistors, and its scaled density, will deliver the expected value of performance, power, and economy.

At IBM, we think years ahead about what cognitive computing, cloud computing, blockchain, mobile, and security advances should be able to do – and what will make running those algorithms, and apps possible. We believe that billions of 5nm nanosheet transistors will soon serve as the silicon engine for these capabilities.