Architects and the semiconductor industry as a whole is faced with a unique challenge of improving performance and reducing power consumption of future microprocessors with almost no gain coming from device scaling. The role of architecture is perhaps more important today than it has ever been. Industry has reacted with a short-term goal of domain or application-specific accelerators which do little to improve performance of “general-purpose” applications, suffer from programming challenges, are by design obsoletion-prone, and introduce severe design pressure in maintaining so many designs. Is there a principled way to build future processors that can avoid this trap of adhoc integration?

In this talk, I will describe how the underlying principles of explicit dataflow based computation can be applied to both the design of cores and accelerators. Specifically I will highlight a simple observation: a hybrid execution model that allows both sequential and dataflow based execution can be extremely beneficial. When applied to the design of cores, I will show such a hybrid model can increase performance of the state-of-art high performance processors by more than a factor of two while reducing power consumption. Applying these same principles to the design of accelerators, shows we can build a single programmable accelerator that can match the efficiency and performance of “any” domain-specific accelerator.