Key features

Efficient Out-of-Order Pipeline

Microarchitecture performance and power improvements to maximize efficiency of the 2-wide out-of-order pipeline. High and sustained performance at frequencies up to 2.8GHz in advanced process technology for premium smartphones.

State-of-the-art Branch Prediction and Power-Optimized Instruction Fetching

Advanced sophisticated prediction algorithm with power-optimized 64kB instruction cache.

High-performance Memory System

Full out-of-order dual-issue load/store capability combined with up to 64kB data cache. Enhanced data prefetching with automatic complex pattern detection.

Optimized mobile and consumer feature set

Combined with Cortex-A53 or Cortex-35 in big.LITTLE configuration using Arm CCI interconnect for high scalability.