The PWM topic appears to be popular lately on the fpgarelated site. This is coincidence, but I typically find the topic of modulating and demodulating signals interesting. For digital systems it is always entertaining to play with PWMs. The following PWM RTL description is quite a bit different than the PWM module described by Anton Babushkin. The module presented here is a minimal PWM engine defined at design time (i.e. not run-time).

As mentioned, the following is a basic MyHDL module to generate a PWM signal. This module is intended to be used in an FPGA. The PWM module is configured for the application at design time and compiled (synthesized, P&R) for a particular FPGA. Other than the PCM input to the PWM module there are no real-time configurations that occur. The typical use of a PWM is to configure it for the application and let it run.

To learn more about PWM signals see this overview buried in a filtering example. The following PWM module has a couple primary parameters: the system clock frequency (attribute of the clock port) and the frequency (1/period) of the output PWM (pwm_frequency). From these two parameters the number of bits will be determined. If the PWM number of bits is less than the input, the input will be truncated.

The following is a code snip that exercises the parameters and a summary given the parameters.

>>> from myhdl import * >>> from myhdl_tools import Clock,Reset >>> from pwm import m_pwm >>> cfreq = (50e6,100e6,200e6,333e6,500e6) >>> pfreq = (.5e3,1e3,10e3) >>> Xmax,Xmin = (2**15,-2**15) >>> reset = Reset(0, active=0, async=False) >>> x = Signal(intbv(0, min=Xmin, max=Xmax)) >>> y = Signal(bool(0)) >>> ts = Signal(bool(0)) >>> for cf in cfreq: for pf in pfreq: clock = Clock(0, frequency=cf) tb_dut = m_pwm(clock,reset,x,y,ts,pwm_frequency=pf)

... ~~~[PWM Module]~~~ clock frequency ................... 50.000 MHz pwm frequency ..................... 1.000 kHz local counter max ................. 32768 pwm number of bits ................ 15 pwm offset ........................ 32768 pwm shift ......................... 1 ... ~~~[PWM Module]~~~ clock frequency ................... 500.000 MHz pwm frequency ..................... 10.000 kHz local counter max ................. 32768 pwm number of bits ................ 15 pwm offset ........................ 32768 pwm shift ......................... 1 ...

The following is the complete code for the module.

The following is a waveform from a simulation of the module. The waveform shows the input signal (x) and the output modulated signal (y).