While working on projects in C/C++ , compiling several files at once from the terminal is a tedious task as you have to type compiling command everytime you want to do it. To Solve such issue, we use Makefile .

Makefile is a tool to organize code for compilation. It is a set of commands with variable names and targets to create object file and also to remove them. Makefiles uses make utility that will automatically build and manage your projects. Lets understand the makefile concept with example.

Here we have 4 files inside a directory which we will compile using make utility.

main.cpp

example.cpp

sum.cpp

headerfile.h

make :

When we run “make” on the terminal. This program will look for a file named makefile in the directory and execute it.

This was when we have a single makefile in the directory. If we have several makefiles, then one can execute them with the below command.

make -f Makefile



Makefile Syntax

Makefile is composed of target,dependencies and system command.

target: dependencies

[tab] system command

Makefile Example

When we don’t have makefile, we compile the files and obtain the executable, by running the below commands

g++ main.cpp example.cpp add.cpp -o example



We can add these commands to Makefile which will look like this

all:

g++ main.cpp example.cpp add.cpp -o example

Now to run this makefile on your files, type:

make -f Makefile_name

If we have the Makefile name as Makefile then we can directly execute make . On the above example we see that our target is called all . This is the default target if none is specified. Since there are no dependencies for target all, so make safely executes the system commands specified.

Makefile with Dependencies

It is quite useful to use different targets in Makefile as when you modify a single file in your project, you don’t have to recompile everything, only dependencies with target file(changed file) will be recompiled.

Below is an example:

all: example



example: main.o add.o example.o

g++ main.o add.o example.o -o example



main.o: main.cpp

g++ -c main.cpp



add.o: add.cpp

g++ -c add.cpp



example.o: example.cpp

g++ -c example.cpp



clean:

rm *o example

Here we see that the target all has only dependencies, but no system commands. To execute “make” , it should meet all the dependencies of the called target (“all”).

Each dependency will be searched for all the targets available and executed if found.

Clean is use to remove all the object files and executables. This is done by executing “make clean“

Makefile using Variables

We can also use variables in the Makefile to generalize Makefile. Lets see an example:

#make file - This is Comment

CC=g++ #compiler

Target=main #target_file_name



all: example



example: main.o add.o example.o

$(CC) main.o add.o example.o -o example



main.o: main.cpp

$(CC) -c main.cpp



add.o: add.cpp

$(CC) -c add.cpp



example.o: example.cpp

$(CC) -c example.cpp



clean:

rm *o example

As we see above , variables can be very useful . To use them, just assign a value to a variable before you write your targets . You can then use their values by dereferencing them with $(VAR).

This was just an introduction to Makefile. You can make use of it and ease your compiling process by using makefile variables for complex projects.

If you find anything wrong or want to add something . Please leave a feedback in the comment section.