Introduction to Xilinx System Generator

Posted by Shannon Hilbert in Digital Signal Processing on 5-5-13

The Xilinx System Generator design flow is a fantastic tool for implementing digtial signal processing (DSP) designs in Xilinx FPGAs.

This video series will introduce Xilinx System Generator and cover the basic principles of the design flow. The video will also contrast the System Generator design flow with typical HDL-only design flow.

The full video series (still under development) consists of several parts:

Introduction Creating a New Design and the Xilinx Blockset Designing DSP Algorithms for FPGAs with the Xilinx Blockset Driving FPGA Designs with Simulink Sources Capturing End and Intermediate Results Using the Wave Scope Block Capturing End and Intermediate Results Using the MATLAB Environment Examining Timing Performance Generating Implementation Files Setting Up a Hardware Co-Simulation using a Xilinx Development Board Communicating Data Between the MATLAB Environment and a Hardware Co-Simulation Opening a Design for Hardware Co-Simulation Running a Design in Hardware Co-Simulation

The video outline is located below the video.



Overview

What is Xilinx System Generator

Design flow using system generator

Why use system generator for DSP designs

Design outputs from system generator

What Is Xilinx System Generator

Xilinx System generator is a design methodology for creating digital signal processing designs for FPGA.

Integrates MATLAB/Simulink with Xilinx design tools to target Xilinx FPGAs

Design Flow

Compare Traditional HDL vs System Generator

Typical HDL design flow

Create floating point algorithm models

Verify floating point algorithm operation in MATLAB

Implement fixed point design in Verilog or VHDL (create floating point design)

Verify HDL outputs in MATLAB (re-verify algorithm)

Target FPGA and deploy

System generator design flow

Create floating point test signals

Create FPGA design using Xilinx blocks in Simulink

Simulate design and verify outputs

Target FPGA and deploy

System Generator Design Environment

Why Use System Generator for DSP Designs

Reduction of algorithmic design to implementation time

Design, simulate, verify and target FPGA in one step

Outputs

Simulink simulation

Timing, resources, and power

Implementation files (bit, .ngc, etc)

Hardware co-simulation using Xilinx development boards (or custom)



