The program for the 2007 International Solid State Circuits Conference (ISSCC) in early February is out, and Stephen Shankland over at CNET spotted it before I did. You might have seen his article a few days ago, so here's my own take on the program's highlights.

POWER6 and Cell

The short description for IBM's POWER6 session (quoted below) doesn't really tell us much about the processor that we didn't already know:

5.1 Design of the POWER6TM Microprocessor J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G. Mittal, E. Chan, Y. Chan, D. Plass, S. Chu, H. Le, L. Clark, J. Ripley, S. Taylor1, J. Dilullo, M. Lanzerotti The POWER6TM microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

This session will probably reveal long-awaited details of the POWER6 microarchitecture. We should finally be able to solve the long-standing riddle of how close POWER6 is to the POWER4/5/970 lineage, and how close it is to the PPE architecture that powers parts of Cell and the Xbox 360. We might also learn more about how IBM managed to combine a clock frequency north of 5GHz with such a low power envelope (100W in some applications) on a 65nm process.

Note that there are some implications here with respect to The Switch, but any musings about POWER6's apparently miraculously high clockspeed/watt ratio, Jobs' claims about reasons for moving to Intel, and what Jobs knew about POWER6 when he made the decision to switch are all academic at this point. This is especially true in light of what Bootcamp has done to the Mac vs. Windows switcher equation. Mac marketshare is up, and many current Windows users are now considering the Mac because if they decide they don't like OS X, they can always install Windows on the machine.

The program also contains a session on a new version of Cell that's clocked at 6GHz and fabbed on a 65nm process. High-performance computing buyers of Cell will be happy to have that options, but the impact on Sony is less clear. Basically, IBM could downclock this chip so that it runs at the same speed as the PS3's current processor, thereby saving on power consumption. This would make the PS3 cheaper, because you could get rid of some of the elaborate cooling apparatus.

Note that the same would be true of a 65nm Xbox 360 chip from IBM, though no such chip is mentioned in the program.

PA Semi to unveil 2GHz dual-core PowerPC chip at 25W max

Speaking of PowerPC and stunning clockspeed/watt numbers, PA Semi will host a session on their heavily anticipated dual-core 2GHz PowerPC chip. You may recall this chip from earlier reporting, as it was announced shortly after The Switch and it blew everyone's mind. The specs are worth repeating, because they're so out of control for a laptop-capable chip:

Two 64-bit, superscalar, out-of-order PowerPC processor cores with Altivec/VMX

Two DDR2 memory controllers (one per core!)

2MB shared L2 cache

I/O unit that has support for: eight PCIe controllers, two 10 Gigabit Ethernet controllers, four Gigabit Ethernet controllers

65nm process

5-13 watts typical @ 2GHz, depending on the application

This looks like a great SoC, and it would've made for a fabulous Apple portable. Oh well; life goes on.

Anyway, this chip will probably see use in markets from embedded all the way up to HPC. With all of that per-chip I/O bandwidth and at 25W (max) a pop, you can go nuts ganging these together in a blade chassis.

(As with POWER6, David Kanter at RWT has the in-depth scoop on this chip, if you're looking for more details.)

Intel touts Terascale research chip, AMD opens up quad-core Opteron

When news of Intel's 80-core, floating-point-centric, "Terascale" prototype chip broke, it was pretty clear that this was a research project that wasn't intended for market anytime soon. I suppose the project is going well enough that Intel is doing a session at ISSSC on it, a fact that may up the likelihood of this thing becoming a reality.

For my part, I wonder if this has any relation to the whole Intel GPGPU skunkworks project that the Register has been on about recently. If Intel uses the Terascale chip's TSV (through silicon via) interconnect technology to stack a bunch of fast SRAM onto a cutting-edge GPU design, they may eat everyone's lunch.

On the AMD side of the fence, the quad-core Opteron gets its own session. Hopefully, AMD will release even more microarchitectural details on the new design, so that we can get a better sense of how it stacks up to Woodcrest.